passes/pmgen/ice40_dsp.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 #include "passes/pmgen/ice40_dsp_pm.h"
  27
  28 void create_ice40_dsp(ice40_dsp_pm &pm)
  29 {
  30         auto &st = pm.st_ice40_dsp;
  31
  32         log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
  33
  34         log_debug("ffA:    %s %s %s\n", log_id(st.ffA, "--"), log_id(st.ffAholdmux, "--"), log_id(st.ffArstmux, "--"));
  35         log_debug("ffB:    %s %s %s\n", log_id(st.ffB, "--"), log_id(st.ffBholdmux, "--"), log_id(st.ffBrstmux, "--"));
  36         log_debug("ffCD:   %s %s\n", log_id(st.ffCD, "--"), log_id(st.ffCDholdmux, "--"));
  37         log_debug("mul:    %s\n", log_id(st.mul, "--"));
  38         log_debug("ffFJKG: %s\n", log_id(st.ffFJKG, "--"));
  39         log_debug("ffH:    %s\n", log_id(st.ffH, "--"));
  40         log_debug("add:    %s\n", log_id(st.add, "--"));
  41         log_debug("mux:    %s\n", log_id(st.mux, "--"));
  42         log_debug("ffO:    %s %s %s\n", log_id(st.ffO, "--"), log_id(st.ffOholdmux, "--"), log_id(st.ffOrstmux, "--"));
  43         log_debug("\n");
  44
  45         if (GetSize(st.sigA) > 16) {
  46                 log("  input A (%s) is too large (%d > 16).\n", log_signal(st.sigA), GetSize(st.sigA));
  47                 return;
  48         }
  49
  50         if (GetSize(st.sigB) > 16) {
  51                 log("  input B (%s) is too large (%d > 16).\n", log_signal(st.sigB), GetSize(st.sigB));
  52                 return;
  53         }
  54
  55         if (GetSize(st.sigO) > 33) {
  56                 log("  adder/accumulator (%s) is too large (%d > 33).\n", log_signal(st.sigO), GetSize(st.sigO));
  57                 return;
  58         }
  59
  60         if (GetSize(st.sigH) > 32) {
  61                 log("  output (%s) is too large (%d > 32).\n", log_signal(st.sigH), GetSize(st.sigH));
  62                 return;
  63         }
  64
  65         Cell *cell = st.mul;
  66         if (cell->type == ID($mul)) {
  67                 log("  replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
  68
  69                 cell = pm.module->addCell(NEW_ID, ID(SB_MAC16));
  70                 pm.module->swap_names(cell, st.mul);
  71         }
  72         else log_assert(cell->type == ID(SB_MAC16));
  73
  74         // SB_MAC16 Input Interface
  75         SigSpec A = st.sigA;
  76         A.extend_u0(16, st.mul->getParam(ID::A_SIGNED).as_bool());
  77         log_assert(GetSize(A) == 16);
  78
  79         SigSpec B = st.sigB;
  80         B.extend_u0(16, st.mul->getParam(ID::B_SIGNED).as_bool());
  81         log_assert(GetSize(B) == 16);
  82
  83         SigSpec CD = st.sigCD;
  84         if (CD.empty())
  85                 CD = RTLIL::Const(0, 32);
  86         else
  87                 log_assert(GetSize(CD) == 32);
  88
  89         cell->setPort(ID::A, A);
  90         cell->setPort(ID::B, B);
  91         cell->setPort(ID::C, CD.extract(16, 16));
  92         cell->setPort(ID::D, CD.extract(0, 16));
  93
  94         cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0);
  95         cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0);
  96         cell->setParam(ID(C_REG), st.ffCD ? State::S1 : State::S0);
  97         cell->setParam(ID(D_REG), st.ffCD ? State::S1 : State::S0);
  98
  99         SigSpec AHOLD, BHOLD, CDHOLD;
 100         if (st.ffAholdmux)
 101                 AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID::S));
 102         else
 103                 AHOLD = State::S0;
 104         if (st.ffBholdmux)
 105                 BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID::S));
 106         else
 107                 BHOLD = State::S0;
 108         if (st.ffCDholdmux)
 109                 CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID::S));
 110         else
 111                 CDHOLD = State::S0;
 112         cell->setPort(ID(AHOLD), AHOLD);
 113         cell->setPort(ID(BHOLD), BHOLD);
 114         cell->setPort(ID(CHOLD), CDHOLD);
 115         cell->setPort(ID(DHOLD), CDHOLD);
 116
 117         SigSpec IRSTTOP, IRSTBOT;
 118         if (st.ffArstmux)
 119                 IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID::S));
 120         else
 121                 IRSTTOP = State::S0;
 122         if (st.ffBrstmux)
 123                 IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID::S));
 124         else
 125                 IRSTBOT = State::S0;
 126         cell->setPort(ID(IRSTTOP), IRSTTOP);
 127         cell->setPort(ID(IRSTBOT), IRSTBOT);
 128
 129         if (st.clock != SigBit())
 130         {
 131                 cell->setPort(ID::CLK, st.clock);
 132                 cell->setPort(ID(CE), State::S1);
 133                 cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1);
 134
 135                 log("  clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
 136
 137                 if (st.ffA)
 138                         log(" ffA:%s", log_id(st.ffA));
 139
 140                 if (st.ffB)
 141                         log(" ffB:%s", log_id(st.ffB));
 142
 143                 if (st.ffCD)
 144                         log(" ffCD:%s", log_id(st.ffCD));
 145
 146                 if (st.ffFJKG)
 147                         log(" ffFJKG:%s", log_id(st.ffFJKG));
 148
 149                 if (st.ffH)
 150                         log(" ffH:%s", log_id(st.ffH));
 151
 152                 if (st.ffO)
 153                         log(" ffO:%s", log_id(st.ffO));
 154
 155                 log("\n");
 156         }
 157         else
 158         {
 159                 cell->setPort(ID::CLK, State::S0);
 160                 cell->setPort(ID(CE), State::S0);
 161                 cell->setParam(ID(NEG_TRIGGER), State::S0);
 162         }
 163
 164         // SB_MAC16 Cascade Interface
 165
 166         cell->setPort(ID(SIGNEXTIN), State::Sx);
 167         cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID));
 168
 169         cell->setPort(ID::CI, State::Sx);
 170
 171         cell->setPort(ID(ACCUMCI), State::Sx);
 172         cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID));
 173
 174         // SB_MAC16 Output Interface
 175
 176         SigSpec O = st.sigO;
 177         int O_width = GetSize(O);
 178         if (O_width == 33) {
 179                 log_assert(st.add);
 180                 // If we have a signed multiply-add, then perform sign extension
 181                 if (st.add->getParam(ID::A_SIGNED).as_bool() && st.add->getParam(ID::B_SIGNED).as_bool())
 182                         pm.module->connect(O[32], O[31]);
 183                 else
 184                         cell->setPort(ID::CO, O[32]);
 185                 O.remove(O_width-1);
 186         }
 187         else
 188                 cell->setPort(ID::CO, pm.module->addWire(NEW_ID));
 189         log_assert(GetSize(O) <= 32);
 190         if (GetSize(O) < 32)
 191                 O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
 192
 193         cell->setPort(ID::O, O);
 194
 195         bool accum = false;
 196         if (st.add) {
 197                 accum = (st.ffO && st.add->getPort(st.addAB == ID::A ? ID::B : ID::A) == st.sigO);
 198                 if (accum)
 199                         log("  accumulator %s (%s)\n", log_id(st.add), log_id(st.add->type));
 200                 else
 201                         log("  adder %s (%s)\n", log_id(st.add), log_id(st.add->type));
 202                 cell->setPort(ID(ADDSUBTOP), st.add->type == ID($add) ? State::S0 : State::S1);
 203                 cell->setPort(ID(ADDSUBBOT), st.add->type == ID($add) ? State::S0 : State::S1);
 204         } else {
 205                 cell->setPort(ID(ADDSUBTOP), State::S0);
 206                 cell->setPort(ID(ADDSUBBOT), State::S0);
 207         }
 208
 209         SigSpec OHOLD;
 210         if (st.ffOholdmux)
 211                 OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID::S));
 212         else
 213                 OHOLD = State::S0;
 214         cell->setPort(ID(OHOLDTOP), OHOLD);
 215         cell->setPort(ID(OHOLDBOT), OHOLD);
 216
 217         SigSpec ORST;
 218         if (st.ffOrstmux)
 219                 ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID::S));
 220         else
 221                 ORST = State::S0;
 222         cell->setPort(ID(ORSTTOP), ORST);
 223         cell->setPort(ID(ORSTBOT), ORST);
 224
 225         SigSpec acc_reset = State::S0;
 226         if (st.mux) {
 227                 if (st.muxAB == ID::A)
 228                         acc_reset = st.mux->getPort(ID::S);
 229                 else
 230                         acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S));
 231         }
 232         cell->setPort(ID(OLOADTOP), acc_reset);
 233         cell->setPort(ID(OLOADBOT), acc_reset);
 234
 235         // SB_MAC16 Remaining Parameters
 236
 237         cell->setParam(ID(TOP_8x8_MULT_REG), st.ffFJKG ? State::S1 : State::S0);
 238         cell->setParam(ID(BOT_8x8_MULT_REG), st.ffFJKG ? State::S1 : State::S0);
 239         cell->setParam(ID(PIPELINE_16x16_MULT_REG1), st.ffFJKG ? State::S1 : State::S0);
 240         cell->setParam(ID(PIPELINE_16x16_MULT_REG2), st.ffH ? State::S1 : State::S0);
 241
 242         cell->setParam(ID(TOPADDSUB_LOWERINPUT), Const(2, 2));
 243         cell->setParam(ID(TOPADDSUB_UPPERINPUT), accum ? State::S0 : State::S1);
 244         cell->setParam(ID(TOPADDSUB_CARRYSELECT), Const(3, 2));
 245
 246         cell->setParam(ID(BOTADDSUB_LOWERINPUT), Const(2, 2));
 247         cell->setParam(ID(BOTADDSUB_UPPERINPUT), accum ? State::S0 : State::S1);
 248         cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
 249
 250         cell->setParam(ID(MODE_8x8), State::S0);
 251         cell->setParam(ID::A_SIGNED, st.mul->getParam(ID::A_SIGNED).as_bool());
 252         cell->setParam(ID::B_SIGNED, st.mul->getParam(ID::B_SIGNED).as_bool());
 253
 254         if (st.ffO) {
 255                 if (st.o_lo)
 256                         cell->setParam(ID(TOPOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
 257                 else
 258                         cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
 259
 260                 st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
 261                 cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
 262         }
 263         else {
 264                 cell->setParam(ID(TOPOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
 265                 cell->setParam(ID(BOTOUTPUT_SELECT), Const(st.add ? 0 : 3, 2));
 266         }
 267
 268         if (cell != st.mul)
 269                 pm.autoremove(st.mul);
 270         else
 271                 pm.blacklist(st.mul);
 272         pm.autoremove(st.ffFJKG);
 273         pm.autoremove(st.add);
 274 }
 275
 276 struct Ice40DspPass : public Pass {
 277         Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
 278         void help() YS_OVERRIDE
 279         {
 280                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 281                 log("\n");
 282                 log("    ice40_dsp [options] [selection]\n");
 283                 log("\n");
 284                 log("Map multipliers ($mul/SB_MAC16) and multiply-accumulate ($mul/SB_MAC16 + $add)\n");
 285                 log("cells into iCE40 DSP resources.\n");
 286                 log("Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.\n");
 287                 log("\n");
 288                 log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
 289                 log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
 290                 log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
 291                 log("\n");
 292                 log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
 293                 log("input will be folded into the DSP. In this scenario only, resetting the\n");
 294                 log("the accumulator to an arbitrary value can be inferred to use the {C,D} input.\n");
 295                 log("\n");
 296         }
 297         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 298         {
 299                 log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
 300
 301                 size_t argidx;
 302                 for (argidx = 1; argidx < args.size(); argidx++)
 303                 {
 304                         // if (args[argidx] == "-singleton") {
 305                         //      singleton_mode = true;
 306                         //      continue;
 307                         // }
 308                         break;
 309                 }
 310                 extra_args(args, argidx, design);
 311
 312                 for (auto module : design->selected_modules())
 313                         ice40_dsp_pm(module, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);
 314         }
 315 } Ice40DspPass;
 316
 317 PRIVATE_NAMESPACE_END