passes/pmgen/ice40_dsp.pmg

   1 pattern ice40_dsp
   2
   3 state <SigBit> clock
   4 state <bool> clock_pol cd_signed o_lo
   5 state <SigSpec> sigA sigB sigCD sigH sigO
   6 state <Cell*> add mux
   7 state <IdString> addAB muxAB
   8
   9 state <bool> ffAholdpol ffBholdpol ffCDholdpol ffOholdpol
  10 state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
  11
  12 state <Cell*> ffA ffAholdmux ffArstmux ffB ffBholdmux ffBrstmux ffCD ffCDholdmux
  13 state <Cell*> ffFJKG ffH ffO ffOholdmux ffOrstmux
  14
  15 // subpattern
  16 state <SigSpec> argQ argD
  17 state <bool> ffholdpol ffrstpol
  18 state <int> ffoffset
  19 udata <SigSpec> dffD dffQ
  20 udata <SigBit> dffclock
  21 udata <Cell*> dff dffholdmux dffrstmux
  22 udata <bool> dffholdpol dffrstpol dffclock_pol
  23
  24 match mul
  25         select mul->type.in($mul, \SB_MAC16)
  26         select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
  27 endmatch
  28
  29 code sigA sigB sigH
  30         SigSpec O;
  31         if (mul->type == $mul)
  32                 O = mul->getPort(\Y);
  33         else if (mul->type == \SB_MAC16)
  34                 O = mul->getPort(\O);
  35         else log_abort();
  36         if (GetSize(O) <= 10)
  37                 reject;
  38
  39         sigA = port(mul, \A);
  40         int i;
  41         for (i = GetSize(sigA)-1; i > 0; i--)
  42                 if (sigA[i] != sigA[i-1])
  43                         break;
  44         // Do not remove non-const sign bit
  45         if (sigA[i].wire)
  46                 ++i;
  47         sigA.remove(i, GetSize(sigA)-i);
  48         sigB = port(mul, \B);
  49         for (i = GetSize(sigB)-1; i > 0; i--)
  50                 if (sigB[i] != sigB[i-1])
  51                         break;
  52         // Do not remove non-const sign bit
  53         if (sigB[i].wire)
  54                 ++i;
  55         sigB.remove(i, GetSize(sigB)-i);
  56
  57         // Only care about those bits that are used
  58         for (i = 0; i < GetSize(O); i++) {
  59                 if (nusers(O[i]) <= 1)
  60                         break;
  61                 sigH.append(O[i]);
  62         }
  63         log_assert(nusers(O.extract_end(i)) <= 1);
  64 endcode
  65
  66 code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
  67         if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
  68                 argQ = sigA;
  69                 subpattern(in_dffe);
  70                 if (dff) {
  71                         ffA = dff;
  72                         clock = dffclock;
  73                         clock_pol = dffclock_pol;
  74                         if (dffrstmux) {
  75                                 ffArstmux = dffrstmux;
  76                                 ffArstpol = dffrstpol;
  77                         }
  78                         if (dffholdmux) {
  79                                 ffAholdmux = dffholdmux;
  80                                 ffAholdpol = dffholdpol;
  81                         }
  82                         sigA = dffD;
  83                 }
  84         }
  85 endcode
  86
  87 code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
  88         if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
  89                 argQ = sigB;
  90                 subpattern(in_dffe);
  91                 if (dff) {
  92                         ffB = dff;
  93                         clock = dffclock;
  94                         clock_pol = dffclock_pol;
  95                         if (dffrstmux) {
  96                                 ffBrstmux = dffrstmux;
  97                                 ffBrstpol = dffrstpol;
  98                         }
  99                         if (dffholdmux) {
 100                                 ffBholdmux = dffholdmux;
 101                                 ffBholdpol = dffholdpol;
 102                         }
 103                         sigB = dffD;
 104                 }
 105         }
 106 endcode
 107
 108 code argD ffFJKG sigH sigO clock clock_pol
 109         if (nusers(sigH) == 2 &&
 110                         (mul->type != \SB_MAC16 ||
 111                          (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
 112                 argD = sigH;
 113                 subpattern(out_dffe);
 114                 if (dff) {
 115                         // F/J/K/G do not have a CE-like (hold) input
 116                         if (dffholdmux)
 117                                 goto reject_ffFJKG;
 118
 119                         // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
 120                         //   shared with A and B
 121                         if ((ffArstmux != NULL) != (dffrstmux != NULL))
 122                                 goto reject_ffFJKG;
 123                         if ((ffBrstmux != NULL) != (dffrstmux != NULL))
 124                                 goto reject_ffFJKG;
 125                         if (ffArstmux) {
 126                                 if (port(ffArstmux, \S) != port(dffrstmux, \S))
 127                                         goto reject_ffFJKG;
 128                                 if (ffArstpol != dffrstpol)
 129                                         goto reject_ffFJKG;
 130                         }
 131                         if (ffBrstmux) {
 132                                 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
 133                                         goto reject_ffFJKG;
 134                                 if (ffBrstpol != dffrstpol)
 135                                         goto reject_ffFJKG;
 136                         }
 137
 138                         ffFJKG = dff;
 139                         clock = dffclock;
 140                         clock_pol = dffclock_pol;
 141                         sigH = dffQ;
 142                 }
 143         }
 144
 145         if (0) {
 146 reject_ffFJKG: ;
 147         }
 148 endcode
 149
 150 code argD ffH sigH sigO clock clock_pol
 151         if (ffFJKG && nusers(sigH) == 2 &&
 152                         (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
 153                 argD = sigH;
 154                 subpattern(out_dffe);
 155                 if (dff) {
 156                         // H does not have a CE-like (hold) input
 157                         if (dffholdmux)
 158                                 goto reject_ffH;
 159
 160                         // Reset signal of H (IRSTBOT) shared with B
 161                         if ((ffBrstmux != NULL) != (dffrstmux != NULL))
 162                                 goto reject_ffH;
 163                         if (ffBrstmux) {
 164                                 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
 165                                         goto reject_ffH;
 166                                 if (ffBrstpol != dffrstpol)
 167                                         goto reject_ffH;
 168                         }
 169
 170                         ffH = dff;
 171                         clock = dffclock;
 172                         clock_pol = dffclock_pol;
 173                         sigH = dffQ;
 174                 }
 175         }
 176
 177         if (0) {
 178 reject_ffH: ;
 179         }
 180
 181         sigO = sigH;
 182 endcode
 183
 184 match add
 185         if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
 186         select add->type.in($add)
 187         choice <IdString> AB {\A, \B}
 188         select nusers(port(add, AB)) == 2
 189         index <SigBit> port(add, AB)[0] === sigH[0]
 190         filter GetSize(port(add, AB)) <= GetSize(sigH)
 191         filter port(add, AB) ==  sigH.extract(0, GetSize(port(add, AB)))
 192         set addAB AB
 193         optional
 194 endmatch
 195
 196 code sigCD sigO cd_signed
 197         if (add) {
 198                 sigCD = port(add, addAB == \A ? \B : \A);
 199                 cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
 200
 201                 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
 202                 int actual_mul_width = GetSize(sigH);
 203                 int actual_acc_width = GetSize(sigCD);
 204
 205                 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
 206                         reject;
 207                 // If accumulator, check adder width and signedness
 208                 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
 209                         reject;
 210
 211                 sigO = port(add, \Y);
 212         }
 213 endcode
 214
 215 match mux
 216         select mux->type == $mux
 217         choice <IdString> AB {\A, \B}
 218         index <int> nusers(port(mux, AB)) === 2
 219         index <SigSpec> port(mux, AB) === sigO
 220         set muxAB AB
 221         optional
 222 endmatch
 223
 224 code sigO
 225         if (mux)
 226                 sigO = port(mux, \Y);
 227 endcode
 228
 229 code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
 230         if (mul->type != \SB_MAC16 ||
 231                         // Ensure that register is not already used
 232                         ((mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) &&
 233                          // Ensure that OLOADTOP/OLOADBOT is unused or zero
 234                          (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero()))) {
 235
 236                 dff = nullptr;
 237
 238                 // First try entire sigO
 239                 if (nusers(sigO) == 2) {
 240                         argD = sigO;
 241                         subpattern(out_dffe);
 242                 }
 243
 244                 // Otherwise try just its least significant 16 bits
 245                 if (!dff && GetSize(sigO) > 16) {
 246                         argD = sigO.extract(0, 16);
 247                         if (nusers(argD) == 2) {
 248                                 subpattern(out_dffe);
 249                                 o_lo = dff;
 250                         }
 251                 }
 252
 253                 if (dff) {
 254                         ffO = dff;
 255                         clock = dffclock;
 256                         clock_pol = dffclock_pol;
 257                         if (dffrstmux) {
 258                                 ffOrstmux = dffrstmux;
 259                                 ffOrstpol = dffrstpol;
 260                         }
 261                         if (dffholdmux) {
 262                                 ffOholdmux = dffholdmux;
 263                                 ffOholdpol = dffholdpol;
 264                         }
 265
 266                         sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
 267                 }
 268
 269                 // Loading value into output register is not
 270                 //   supported unless using accumulator
 271                 if (mux) {
 272                         if (sigCD != sigO)
 273                                 reject;
 274                         sigCD = port(mux, muxAB == \B ? \A : \B);
 275
 276                         cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
 277                 }
 278         }
 279 endcode
 280
 281 code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
 282         if (!sigCD.empty() &&
 283                         (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
 284                 argQ = sigCD;
 285                 subpattern(in_dffe);
 286                 if (dff) {
 287                         if (dffholdmux) {
 288                                 ffCDholdmux = dffholdmux;
 289                                 ffCDholdpol = dffholdpol;
 290                         }
 291
 292                         // Reset signal of C (IRSTTOP) and D (IRSTBOT)
 293                         //   shared with A and B
 294                         if ((ffArstmux != NULL) != (dffrstmux != NULL))
 295                                 goto reject_ffCD;
 296                         if ((ffBrstmux != NULL) != (dffrstmux != NULL))
 297                                 goto reject_ffCD;
 298                         if (ffArstmux) {
 299                                 if (port(ffArstmux, \S) != port(dffrstmux, \S))
 300                                         goto reject_ffCD;
 301                                 if (ffArstpol != dffrstpol)
 302                                         goto reject_ffCD;
 303                         }
 304                         if (ffBrstmux) {
 305                                 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
 306                                         goto reject_ffCD;
 307                                 if (ffBrstpol != dffrstpol)
 308                                         goto reject_ffCD;
 309                         }
 310
 311                         ffCD = dff;
 312                         clock = dffclock;
 313                         clock_pol = dffclock_pol;
 314                         sigCD = dffD;
 315                 }
 316         }
 317
 318         if (0) {
 319 reject_ffCD: ;
 320         }
 321 endcode
 322
 323 code sigCD
 324         sigCD.extend_u0(32, cd_signed);
 325 endcode
 326
 327 code
 328         accept;
 329 endcode
 330
 331 // #######################
 332
 333 subpattern in_dffe
 334 arg argD argQ clock clock_pol
 335
 336 code
 337         dff = nullptr;
 338         for (auto c : argQ.chunks()) {
 339                 if (!c.wire)
 340                         reject;
 341                 if (c.wire->get_bool_attribute(\keep))
 342                         reject;
 343         }
 344 endcode
 345
 346 match ff
 347         select ff->type.in($dff)
 348         // DSP48E1 does not support clock inversion
 349         select param(ff, \CLK_POLARITY).as_bool()
 350
 351         slice offset GetSize(port(ff, \D))
 352         index <SigBit> port(ff, \Q)[offset] === argQ[0]
 353
 354         // Check that the rest of argQ is present
 355         filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 356         filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 357
 358         set ffoffset offset
 359 endmatch
 360
 361 code argQ argD
 362 {
 363         if (clock != SigBit()) {
 364                 if (port(ff, \CLK) != clock)
 365                         reject;
 366                 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
 367                         reject;
 368         }
 369
 370         SigSpec Q = port(ff, \Q);
 371         dff = ff;
 372         dffclock = port(ff, \CLK);
 373         dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
 374         dffD = argQ;
 375         argD = port(ff, \D);
 376         argQ = Q;
 377         dffD.replace(argQ, argD);
 378         // Only search for ffrstmux if dffD only
 379         //   has two (ff, ffrstmux) users
 380         if (nusers(dffD) > 2)
 381                 argD = SigSpec();
 382 }
 383 endcode
 384
 385 match ffrstmux
 386         if !argD.empty()
 387         select ffrstmux->type.in($mux)
 388         index <SigSpec> port(ffrstmux, \Y) === argD
 389
 390         choice <IdString> BA {\B, \A}
 391         // DSP48E1 only supports reset to zero
 392         select port(ffrstmux, BA).is_fully_zero()
 393
 394         define <bool> pol (BA == \B)
 395         set ffrstpol pol
 396         semioptional
 397 endmatch
 398
 399 code argD
 400         if (ffrstmux) {
 401                 dffrstmux = ffrstmux;
 402                 dffrstpol = ffrstpol;
 403                 argD = port(ffrstmux, ffrstpol ? \A : \B);
 404                 dffD.replace(port(ffrstmux, \Y), argD);
 405
 406                 // Only search for ffholdmux if argQ has at
 407                 //   least 3 users (ff, <upstream>, ffrstmux) and
 408                 //   dffD only has two (ff, ffrstmux)
 409                 if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
 410                         argD = SigSpec();
 411         }
 412         else
 413                 dffrstmux = nullptr;
 414 endcode
 415
 416 match ffholdmux
 417         if !argD.empty()
 418         select ffholdmux->type.in($mux)
 419         index <SigSpec> port(ffholdmux, \Y) === argD
 420         choice <IdString> BA {\B, \A}
 421         index <SigSpec> port(ffholdmux, BA) === argQ
 422         define <bool> pol (BA == \B)
 423         set ffholdpol pol
 424         semioptional
 425 endmatch
 426
 427 code argD
 428         if (ffholdmux) {
 429                 dffholdmux = ffholdmux;
 430                 dffholdpol = ffholdpol;
 431                 argD = port(ffholdmux, ffholdpol ? \A : \B);
 432                 dffD.replace(port(ffholdmux, \Y), argD);
 433         }
 434         else
 435                 dffholdmux = nullptr;
 436 endcode
 437
 438 // #######################
 439
 440 subpattern out_dffe
 441 arg argD argQ clock clock_pol
 442
 443 code
 444         dff = nullptr;
 445         for (auto c : argD.chunks())
 446                 if (c.wire->get_bool_attribute(\keep))
 447                         reject;
 448 endcode
 449
 450 match ffholdmux
 451         select ffholdmux->type.in($mux)
 452         // ffholdmux output must have two users: ffholdmux and ff.D
 453         select nusers(port(ffholdmux, \Y)) == 2
 454
 455         choice <IdString> BA {\B, \A}
 456         // keep-last-value net must have at least three users: ffholdmux, ff, downstream sink(s)
 457         select nusers(port(ffholdmux, BA)) >= 3
 458
 459         slice offset GetSize(port(ffholdmux, \Y))
 460         define <IdString> AB (BA == \B ? \A : \B)
 461         index <SigBit> port(ffholdmux, AB)[offset] === argD[0]
 462
 463         // Check that the rest of argD is present
 464         filter GetSize(port(ffholdmux, AB)) >= offset + GetSize(argD)
 465         filter port(ffholdmux, AB).extract(offset, GetSize(argD)) == argD
 466
 467         set ffoffset offset
 468         define <bool> pol (BA == \B)
 469         set ffholdpol pol
 470
 471         semioptional
 472 endmatch
 473
 474 code argD argQ
 475         dffholdmux = ffholdmux;
 476         if (ffholdmux) {
 477                 SigSpec AB = port(ffholdmux, ffholdpol ? \A : \B);
 478                 SigSpec Y = port(ffholdmux, \Y);
 479                 argQ = argD;
 480                 argD.replace(AB, Y);
 481                 argQ.replace(AB, port(ffholdmux, ffholdpol ? \B : \A));
 482
 483                 dffholdmux = ffholdmux;
 484                 dffholdpol = ffholdpol;
 485         }
 486 endcode
 487
 488 match ffrstmux
 489         select ffrstmux->type.in($mux)
 490         // ffrstmux output must have two users: ffrstmux and ff.D
 491         select nusers(port(ffrstmux, \Y)) == 2
 492
 493         choice <IdString> BA {\B, \A}
 494         // DSP48E1 only supports reset to zero
 495         select port(ffrstmux, BA).is_fully_zero()
 496
 497         slice offset GetSize(port(ffrstmux, \Y))
 498         define <IdString> AB (BA == \B ? \A : \B)
 499         index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
 500
 501         // Check that offset is consistent
 502         filter !ffholdmux || ffoffset == offset
 503         // Check that the rest of argD is present
 504         filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
 505         filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
 506
 507         set ffoffset offset
 508         define <bool> pol (AB == \A)
 509         set ffrstpol pol
 510
 511         semioptional
 512 endmatch
 513
 514 code argD argQ
 515         dffrstmux = ffrstmux;
 516         if (ffrstmux) {
 517                 SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
 518                 SigSpec Y = port(ffrstmux, \Y);
 519                 argD.replace(AB, Y);
 520
 521                 dffrstmux = ffrstmux;
 522                 dffrstpol = ffrstpol;
 523         }
 524 endcode
 525
 526 match ff
 527         select ff->type.in($dff)
 528         // DSP48E1 does not support clock inversion
 529         select param(ff, \CLK_POLARITY).as_bool()
 530
 531         slice offset GetSize(port(ff, \D))
 532         index <SigBit> port(ff, \D)[offset] === argD[0]
 533
 534         // Check that offset is consistent
 535         filter (!ffholdmux && !ffrstmux) || ffoffset == offset
 536         // Check that the rest of argD is present
 537         filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
 538         filter port(ff, \D).extract(offset, GetSize(argD)) == argD
 539         // Check that FF.Q is connected to CE-mux
 540         filter !ffholdmux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 541
 542         set ffoffset offset
 543 endmatch
 544
 545 code argQ
 546         if (ff) {
 547                 if (clock != SigBit()) {
 548                         if (port(ff, \CLK) != clock)
 549                                 reject;
 550                         if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
 551                                 reject;
 552                 }
 553                 SigSpec D = port(ff, \D);
 554                 SigSpec Q = port(ff, \Q);
 555                 if (!ffholdmux) {
 556                         argQ = argD;
 557                         argQ.replace(D, Q);
 558                 }
 559
 560                 for (auto c : argQ.chunks()) {
 561                         Const init = c.wire->attributes.at(\init, State::Sx);
 562                         if (!init.is_fully_undef() && !init.is_fully_zero())
 563                                 reject;
 564                 }
 565
 566                 dff = ff;
 567                 dffQ = argQ;
 568                 dffclock = port(ff, \CLK);
 569                 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
 570         }
 571         // No enable/reset mux possible without flop
 572         else if (dffholdmux || dffrstmux)
 573                 reject;
 574 endcode