passes/pmgen/ice40_dsp.pmg

   1 pattern ice40_dsp
   2
   3 state <SigBit> clock
   4 state <bool> clock_pol
   5 state <std::set<SigBit>> sigAset sigBset
   6 state <SigSpec> sigA sigB sigCD sigH sigO sigOused
   7 state <Cell*> addAB muxAB
   8
   9 match mul
  10         select mul->type.in($mul, \SB_MAC16)
  11         select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
  12 endmatch
  13
  14 code sigAset sigBset
  15         SigSpec A = port(mul, \A);
  16         A.remove_const();
  17         sigAset = A.to_sigbit_set();
  18         SigSpec B = port(mul, \B);
  19         B.remove_const();
  20         sigBset = B.to_sigbit_set();
  21 endcode
  22
  23 code sigH
  24         if (mul->type == $mul)
  25                 sigH = mul->getPort(\Y);
  26         else if (mul->type == \SB_MAC16)
  27                 sigH = mul->getPort(\O);
  28         else log_abort();
  29         if (GetSize(sigH) <= 10)
  30                 reject;
  31 endcode
  32
  33 match ffA
  34         if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
  35         if !sigAset.empty()
  36         select ffA->type.in($dff)
  37         filter includes(port(ffA, \Q).to_sigbit_set(), sigAset)
  38         optional
  39 endmatch
  40
  41 code sigA clock clock_pol
  42         sigA = port(mul, \A);
  43
  44         if (ffA) {
  45                 for (auto b : port(ffA, \Q))
  46                         if (b.wire->get_bool_attribute(\keep))
  47                                 reject;
  48
  49                 clock = port(ffA, \CLK).as_bit();
  50                 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
  51
  52                 sigA.replace(port(ffA, \Q), port(ffA, \D));
  53         }
  54 endcode
  55
  56 match ffB
  57         if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
  58         if !sigBset.empty()
  59         select ffB->type.in($dff)
  60         filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
  61         optional
  62 endmatch
  63
  64 code sigB clock clock_pol
  65         sigB = port(mul, \B);
  66
  67         if (ffB) {
  68                 for (auto b : port(ffB, \Q))
  69                         if (b.wire->get_bool_attribute(\keep))
  70                                 reject;
  71
  72                 SigBit c = port(ffB, \CLK).as_bit();
  73                 bool cp = param(ffB, \CLK_POLARITY).as_bool();
  74
  75                 if (clock != SigBit() && (c != clock || cp != clock_pol))
  76                         reject;
  77
  78                 clock = c;
  79                 clock_pol = cp;
  80
  81                 sigB.replace(port(ffB, \Q), port(ffB, \D));
  82         }
  83 endcode
  84
  85 match ffH
  86         if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
  87         select ffH->type.in($dff)
  88         select nusers(port(ffH, \D)) == 2
  89         index <SigSpec> port(ffH, \D) === sigH
  90         // Ensure pipeline register is not already used
  91         optional
  92 endmatch
  93
  94 code sigH sigO clock clock_pol
  95         sigO = sigH;
  96
  97         if (ffH) {
  98                 sigH = port(ffH, \Q);
  99                 for (auto b : sigH)
 100                         if (b.wire->get_bool_attribute(\keep))
 101                                 reject;
 102
 103                 sigO = sigH;
 104
 105                 SigBit c = port(ffH, \CLK).as_bit();
 106                 bool cp = param(ffH, \CLK_POLARITY).as_bool();
 107
 108                 if (clock != SigBit() && (c != clock || cp != clock_pol))
 109                         reject;
 110
 111                 clock = c;
 112                 clock_pol = cp;
 113         }
 114 endcode
 115
 116 match addA
 117         select addA->type.in($add)
 118         select nusers(port(addA, \A)) == 2
 119         filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
 120         //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
 121         filter port(addA, \A) ==  sigH.extract(0, param(addA, \A_WIDTH).as_int())
 122         optional
 123 endmatch
 124
 125 match addB
 126         if !addA
 127         select addB->type.in($add, $sub)
 128         select nusers(port(addB, \B)) == 2
 129         filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
 130         //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
 131         filter port(addB, \B) ==  sigH.extract(0, param(addB, \B_WIDTH).as_int())
 132         optional
 133 endmatch
 134
 135 code addAB sigCD sigO
 136         bool CD_SIGNED = false;
 137         if (addA) {
 138                 addAB = addA;
 139                 sigCD = port(addAB, \B);
 140                 CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
 141         }
 142         if (addB) {
 143                 addAB = addB;
 144                 sigCD = port(addAB, \A);
 145                 CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
 146         }
 147         if (addAB) {
 148                 if (mul->type == \SB_MAC16) {
 149                         // Ensure that adder is not used
 150                         if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
 151                                         param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
 152                                 reject;
 153                 }
 154
 155                 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
 156                 int actual_mul_width = GetSize(sigH);
 157                 int actual_acc_width = GetSize(sigCD);
 158
 159                 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
 160                         reject;
 161                 // If accumulator, check adder width and signedness
 162                 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
 163                         reject;
 164
 165                 sigO = port(addAB, \Y);
 166                 sigCD.extend_u0(32, CD_SIGNED);
 167         }
 168 endcode
 169
 170 match muxA
 171         select muxA->type.in($mux)
 172         index <int> nusers(port(muxA, \A)) === 2
 173         index <SigSpec> port(muxA, \A) === sigO
 174         optional
 175 endmatch
 176
 177 match muxB
 178         if !muxA
 179         select muxB->type.in($mux)
 180         index <int> nusers(port(muxB, \B)) === 2
 181         index <SigSpec> port(muxB, \B) === sigO
 182         optional
 183 endmatch
 184
 185 code muxAB
 186         if (muxA)
 187                 muxAB = muxA;
 188         else if (muxB)
 189                 muxAB = muxB;
 190 endcode
 191
 192 // Extract the bits of P that actually have a consumer
 193 // (as opposed to being a dummy)
 194 code sigOused
 195         for (int i = 0; i < GetSize(sigO); i++)
 196                 if (!sigO[i].wire || nusers(sigO[i]) == 1)
 197                         sigOused.append(State::Sx);
 198                 else
 199                         sigOused.append(sigO[i]);
 200 endcode
 201
 202 match ffO_lo
 203         if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
 204         select ffO_lo->type.in($dff)
 205         optional
 206 endmatch
 207
 208 code
 209         SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
 210         O.remove_const();
 211         if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set()))
 212                 reject;
 213 endcode
 214
 215 match ffO_hi
 216         if GetSize(sigOused) > 16
 217         if nusers(sigOused.extract_end(16)) == 2
 218         select ffO_hi->type.in($dff)
 219         optional
 220 endmatch
 221
 222 code
 223         SigSpec O = sigOused.extract_end(16);
 224         O.remove_const();
 225         if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set()))
 226                 reject;
 227 endcode
 228
 229 code clock clock_pol sigO sigCD
 230         if (ffO_lo || ffO_hi) {
 231                 if (mul->type == \SB_MAC16) {
 232                         // Ensure that register is not already used
 233                         if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
 234                                         param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
 235                                 reject;
 236
 237                         // Ensure that OLOADTOP/OLOADBOT is unused or zero
 238                         if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
 239                                 || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
 240                                 reject;
 241                 }
 242
 243                 if (ffO_lo) {
 244                         for (auto b : port(ffO_lo, \Q))
 245                                 if (b.wire->get_bool_attribute(\keep))
 246                                         reject;
 247
 248                         SigBit c = port(ffO_lo, \CLK).as_bit();
 249                         bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
 250
 251                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 252                                 reject;
 253
 254                         clock = c;
 255                         clock_pol = cp;
 256
 257                         sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
 258                 }
 259
 260                 if (ffO_hi) {
 261                         for (auto b : port(ffO_hi, \Q))
 262                                 if (b.wire->get_bool_attribute(\keep))
 263                                         reject;
 264
 265                         SigBit c = port(ffO_hi, \CLK).as_bit();
 266                         bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
 267
 268                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 269                                 reject;
 270
 271                         clock = c;
 272                         clock_pol = cp;
 273
 274                         sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
 275                 }
 276
 277                 // Loading value into output register is not
 278                 //   supported unless using accumulator
 279                 if (muxAB) {
 280                         if (sigCD != sigO)
 281                                 reject;
 282                         if (muxA)
 283                                 sigCD = port(muxAB, \B);
 284                         else if (muxB)
 285                                 sigCD = port(muxAB, \A);
 286                         else log_abort();
 287                         sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
 288                 }
 289         }
 290 endcode