5 state <SigSpec> sigA sigB sigCD sigH sigO sigOused
6 state <Cell*> addAB muxAB
9 select mul->type.in($mul, \SB_MAC16)
10 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
14 if (mul->type == $mul)
15 sigH = mul->getPort(\Y);
16 else if (mul->type == \SB_MAC16)
17 sigH = mul->getPort(\O);
19 if (GetSize(sigH) <= 10)
24 select ffA->type.in($dff)
25 filter mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
26 filter !port(mul, \A).remove_const().empty()
27 filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
31 code sigA clock clock_pol
35 for (auto b : port(ffA, \Q))
36 if (b.wire->get_bool_attribute(\keep))
39 clock = port(ffA, \CLK).as_bit();
40 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
42 sigA.replace(port(ffA, \Q), port(ffA, \D));
47 select ffB->type.in($dff)
48 filter mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
49 filter !port(mul, \B).remove_const().empty()
50 filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
54 code sigB clock clock_pol
58 for (auto b : port(ffB, \Q))
59 if (b.wire->get_bool_attribute(\keep))
62 SigBit c = port(ffB, \CLK).as_bit();
63 bool cp = param(ffB, \CLK_POLARITY).as_bool();
65 if (clock != SigBit() && (c != clock || cp != clock_pol))
71 sigB.replace(port(ffB, \Q), port(ffB, \D));
76 select ffH->type.in($dff)
77 select nusers(port(ffH, \D)) == 2
78 index <SigSpec> port(ffH, \D) === sigH
79 // Ensure pipeline register is not already used
80 filter mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
84 code sigH sigO clock clock_pol
90 if (b.wire->get_bool_attribute(\keep))
95 SigBit c = port(ffH, \CLK).as_bit();
96 bool cp = param(ffH, \CLK_POLARITY).as_bool();
98 if (clock != SigBit() && (c != clock || cp != clock_pol))
107 select addA->type.in($add)
108 select nusers(port(addA, \A)) == 2
109 index <SigSpec> port(addA, \A) === sigH
115 select addB->type.in($add, $sub)
116 select nusers(port(addB, \B)) == 2
117 index <SigSpec> port(addB, \B) === sigH
121 code addAB sigCD sigO
124 sigCD = port(addAB, \B);
125 sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool());
129 sigCD = port(addAB, \A);
130 sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
133 if (mul->type == \SB_MAC16) {
134 // Ensure that adder is not used
135 if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
136 param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
140 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
141 int actual_mul_width = GetSize(sigH);
142 int actual_acc_width = GetSize(sigO);
144 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
146 if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \B_SIGNED).as_bool()))
149 sigO = port(addAB, \Y);
154 select muxA->type.in($mux)
155 select nusers(port(muxA, \A)) == 2
156 index <SigSpec> port(muxA, \A) === sigO
162 select muxB->type.in($mux)
163 select nusers(port(muxB, \B)) == 2
164 index <SigSpec> port(muxB, \B) === sigO
175 // Extract the bits of P that actually have a consumer
176 // (as opposed to being a dummy)
178 for (int i = 0; i < GetSize(sigO); i++)
179 if (!sigO[i].wire || nusers(sigO[i]) == 1)
180 sigOused.append(State::Sx);
182 sigOused.append(sigO[i]);
186 select ffO_lo->type.in($dff)
187 filter nusers(sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()))) == 2
188 filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
193 select ffO_hi->type.in($dff)
194 filter GetSize(sigOused) > 16
195 filter nusers(sigOused.extract_end(16)) == 2
196 filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
200 code clock clock_pol sigO sigCD
201 if (ffO_lo || ffO_hi) {
202 if (mul->type == \SB_MAC16) {
203 // Ensure that register is not already used
204 if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
205 param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
208 // Ensure that OLOADTOP/OLOADBOT is unused or zero
209 if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
210 || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
215 for (auto b : port(ffO_lo, \Q))
216 if (b.wire->get_bool_attribute(\keep))
219 SigBit c = port(ffO_lo, \CLK).as_bit();
220 bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
222 if (clock != SigBit() && (c != clock || cp != clock_pol))
228 sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
232 for (auto b : port(ffO_hi, \Q))
233 if (b.wire->get_bool_attribute(\keep))
236 SigBit c = port(ffO_hi, \CLK).as_bit();
237 bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
239 if (clock != SigBit() && (c != clock || cp != clock_pol))
245 sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
248 // Loading value into output register is not
249 // supported unless using accumulator
254 sigCD = port(muxAB, \B);
256 sigCD = port(muxAB, \A);
258 sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());