passes/pmgen/ice40_dsp.pmg

   1 pattern ice40_dsp
   2
   3 state <SigBit> clock
   4 state <bool> clock_pol
   5 state <std::set<SigBit>> sigAset sigBset
   6 state <SigSpec> sigA sigB sigCD sigH sigO sigOused
   7 state <Cell*> addAB muxAB
   8
   9 match mul
  10         select mul->type.in($mul, \SB_MAC16)
  11         select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
  12 endmatch
  13
  14 code sigAset sigBset
  15         SigSpec A = port(mul, \A);
  16         A.remove_const();
  17         sigAset = A.to_sigbit_set();
  18         SigSpec B = port(mul, \B);
  19         B.remove_const();
  20         sigBset = B.to_sigbit_set();
  21 endcode
  22
  23 code sigH
  24         if (mul->type == $mul)
  25                 sigH = mul->getPort(\Y);
  26         else if (mul->type == \SB_MAC16)
  27                 sigH = mul->getPort(\O);
  28         else log_abort();
  29         if (GetSize(sigH) <= 10)
  30                 reject;
  31 endcode
  32
  33 match ffA
  34         if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
  35         if !sigAset.empty()
  36         select ffA->type.in($dff)
  37         optional
  38 endmatch
  39
  40 code sigA clock clock_pol
  41         sigA = port(mul, \A);
  42
  43         if (ffA) {
  44                 auto ffAset = port(ffA, \Q).to_sigbit_set();
  45                 if (!std::includes(ffAset.begin(), ffAset.end(), sigAset.begin(), sigAset.end()))
  46                         reject;
  47
  48                 for (auto b : port(ffA, \Q))
  49                         if (b.wire->get_bool_attribute(\keep))
  50                                 reject;
  51
  52                 clock = port(ffA, \CLK).as_bit();
  53                 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
  54
  55                 sigA.replace(port(ffA, \Q), port(ffA, \D));
  56         }
  57 endcode
  58
  59 match ffB
  60         if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
  61         if !sigBset.empty()
  62         select ffB->type.in($dff)
  63         optional
  64 endmatch
  65
  66 code sigB clock clock_pol
  67         sigB = port(mul, \B);
  68
  69         if (ffB) {
  70                 auto ffBset = port(ffB, \Q).to_sigbit_set();
  71                 if (!std::includes(ffBset.begin(), ffBset.end(), sigBset.begin(), sigBset.end()))
  72                         reject;
  73
  74                 for (auto b : port(ffB, \Q))
  75                         if (b.wire->get_bool_attribute(\keep))
  76                                 reject;
  77
  78                 SigBit c = port(ffB, \CLK).as_bit();
  79                 bool cp = param(ffB, \CLK_POLARITY).as_bool();
  80
  81                 if (clock != SigBit() && (c != clock || cp != clock_pol))
  82                         reject;
  83
  84                 clock = c;
  85                 clock_pol = cp;
  86
  87                 sigB.replace(port(ffB, \Q), port(ffB, \D));
  88         }
  89 endcode
  90
  91 match ffFJKG
  92         // Ensure pipeline register is not already used
  93         if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
  94         select ffFJKG->type.in($dff)
  95         select nusers(port(ffFJKG, \D)) == 2
  96         index <SigSpec> port(ffFJKG, \D) === sigH
  97         optional
  98 endmatch
  99
 100 code sigH sigO clock clock_pol
 101         if (ffFJKG) {
 102                 sigH = port(ffFJKG, \Q);
 103                 for (auto b : sigH)
 104                         if (b.wire->get_bool_attribute(\keep))
 105                                 reject;
 106
 107                 SigBit c = port(ffFJKG, \CLK).as_bit();
 108                 bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
 109
 110                 if (clock != SigBit() && (c != clock || cp != clock_pol))
 111                         reject;
 112
 113                 clock = c;
 114                 clock_pol = cp;
 115         }
 116
 117         sigO = sigH;
 118 endcode
 119
 120 match addA
 121         select addA->type.in($add)
 122         select nusers(port(addA, \A)) == 2
 123         filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
 124         //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
 125         filter port(addA, \A) ==  sigH.extract(0, param(addA, \A_WIDTH).as_int())
 126         optional
 127 endmatch
 128
 129 match addB
 130         if !addA
 131         select addB->type.in($add, $sub)
 132         select nusers(port(addB, \B)) == 2
 133         filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
 134         //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
 135         filter port(addB, \B) ==  sigH.extract(0, param(addB, \B_WIDTH).as_int())
 136         optional
 137 endmatch
 138
 139 code addAB sigCD sigO
 140         bool CD_SIGNED = false;
 141         if (addA) {
 142                 addAB = addA;
 143                 sigCD = port(addAB, \B);
 144                 CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
 145         }
 146         if (addB) {
 147                 addAB = addB;
 148                 sigCD = port(addAB, \A);
 149                 CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
 150         }
 151         if (addAB) {
 152                 if (mul->type == \SB_MAC16) {
 153                         // Ensure that adder is not used
 154                         if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
 155                                         param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
 156                                 reject;
 157                 }
 158
 159                 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
 160                 int actual_mul_width = GetSize(sigH);
 161                 int actual_acc_width = GetSize(sigCD);
 162
 163                 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
 164                         reject;
 165                 // If accumulator, check adder width and signedness
 166                 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
 167                         reject;
 168
 169                 sigO = port(addAB, \Y);
 170                 sigCD.extend_u0(32, CD_SIGNED);
 171         }
 172 endcode
 173
 174 match muxA
 175         select muxA->type.in($mux)
 176         index <int> nusers(port(muxA, \A)) === 2
 177         index <SigSpec> port(muxA, \A) === sigO
 178         optional
 179 endmatch
 180
 181 match muxB
 182         if !muxA
 183         select muxB->type.in($mux)
 184         index <int> nusers(port(muxB, \B)) === 2
 185         index <SigSpec> port(muxB, \B) === sigO
 186         optional
 187 endmatch
 188
 189 code muxAB
 190         if (muxA)
 191                 muxAB = muxA;
 192         else if (muxB)
 193                 muxAB = muxB;
 194 endcode
 195
 196 // Extract the bits of P that actually have a consumer
 197 // (as opposed to being a dummy)
 198 code sigOused
 199         for (int i = 0; i < GetSize(sigO); i++)
 200                 if (!sigO[i].wire || nusers(sigO[i]) == 1)
 201                         sigOused.append(State::Sx);
 202                 else
 203                         sigOused.append(sigO[i]);
 204 endcode
 205
 206 match ffO_lo
 207         if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
 208         select ffO_lo->type.in($dff)
 209         optional
 210 endmatch
 211
 212 code
 213         if (ffO_lo) {
 214                 SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
 215                 O.remove_const();
 216                 auto ffO_loSet = port(ffO_lo, \D).to_sigbit_set();
 217                 auto Oset = O.to_sigbit_set();
 218                 if (!std::includes(ffO_loSet.begin(), ffO_loSet.end(), Oset.begin(), Oset.end()))
 219                         reject;
 220         }
 221 endcode
 222
 223 match ffO_hi
 224         if GetSize(sigOused) > 16
 225         if nusers(sigOused.extract_end(16)) == 2
 226         select ffO_hi->type.in($dff)
 227         optional
 228 endmatch
 229
 230 code
 231         if (ffO_hi) {
 232                 SigSpec O = sigOused.extract_end(16);
 233                 O.remove_const();
 234                 auto ffO_hiSet = port(ffO_hi, \D).to_sigbit_set();
 235                 auto Oset = O.to_sigbit_set();
 236                 if (!std::includes(ffO_hiSet.begin(), ffO_hiSet.end(), Oset.begin(), Oset.end()))
 237                         reject;
 238         }
 239 endcode
 240
 241 code clock clock_pol sigO sigCD
 242         if (ffO_lo || ffO_hi) {
 243                 if (mul->type == \SB_MAC16) {
 244                         // Ensure that register is not already used
 245                         if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
 246                                         param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
 247                                 reject;
 248
 249                         // Ensure that OLOADTOP/OLOADBOT is unused or zero
 250                         if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
 251                                 || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
 252                                 reject;
 253                 }
 254
 255                 if (ffO_lo) {
 256                         for (auto b : port(ffO_lo, \Q))
 257                                 if (b.wire->get_bool_attribute(\keep))
 258                                         reject;
 259
 260                         SigBit c = port(ffO_lo, \CLK).as_bit();
 261                         bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
 262
 263                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 264                                 reject;
 265
 266                         clock = c;
 267                         clock_pol = cp;
 268
 269                         sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
 270                 }
 271
 272                 if (ffO_hi) {
 273                         for (auto b : port(ffO_hi, \Q))
 274                                 if (b.wire->get_bool_attribute(\keep))
 275                                         reject;
 276
 277                         SigBit c = port(ffO_hi, \CLK).as_bit();
 278                         bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
 279
 280                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 281                                 reject;
 282
 283                         clock = c;
 284                         clock_pol = cp;
 285
 286                         sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
 287                 }
 288
 289                 // Loading value into output register is not
 290                 //   supported unless using accumulator
 291                 if (muxAB) {
 292                         if (sigCD != sigO)
 293                                 reject;
 294                         if (muxA)
 295                                 sigCD = port(muxAB, \B);
 296                         else if (muxB)
 297                                 sigCD = port(muxAB, \A);
 298                         else log_abort();
 299                         sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
 300                 }
 301         }
 302         accept;
 303 endcode