4 state <bool> clock_pol cd_signed o_lo
5 state <SigSpec> sigA sigB sigCD sigH sigO
7 state <IdString> addAB muxAB
9 state <bool> ffAholdpol ffBholdpol ffCDholdpol ffOholdpol
10 state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
12 state <Cell*> ffA ffAholdmux ffArstmux ffB ffBholdmux ffBrstmux ffCD ffCDholdmux
13 state <Cell*> ffFJKG ffH ffO ffOholdmux ffOrstmux
16 state <SigSpec> argQ argD
17 state <bool> ffholdpol ffrstpol
19 udata <SigSpec> dffD dffQ
20 udata <SigBit> dffclock
21 udata <Cell*> dff dffholdmux dffrstmux
22 udata <bool> dffholdpol dffrstpol dffclock_pol
25 select mul->type.in($mul, \SB_MAC16)
26 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
30 auto unextend = [](const SigSpec &sig) {
32 for (i = GetSize(sig)-1; i > 0; i--)
33 if (sig[i] != sig[i-1])
35 // Do not remove non-const sign bit
38 return sig.extract(0, i);
40 sigA = unextend(port(mul, \A));
41 sigB = unextend(port(mul, \B));
44 if (mul->type == $mul)
46 else if (mul->type == \SB_MAC16)
52 // Only care about those bits that are used
54 for (i = 0; i < GetSize(O); i++) {
55 if (nusers(O[i]) <= 1)
59 log_assert(nusers(O.extract_end(i)) <= 1);
65 code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
66 if (mul->type != \SB_MAC16 || !param(mul, \A_REG, State::S0).as_bool()) {
72 clock_pol = dffclock_pol;
74 ffArstmux = dffrstmux;
75 ffArstpol = dffrstpol;
78 ffAholdmux = dffholdmux;
79 ffAholdpol = dffholdpol;
86 code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
87 if (mul->type != \SB_MAC16 || !param(mul, \B_REG, State::S0).as_bool()) {
93 clock_pol = dffclock_pol;
95 ffBrstmux = dffrstmux;
96 ffBrstpol = dffrstpol;
99 ffBholdmux = dffholdmux;
100 ffBholdpol = dffholdpol;
107 code argD ffFJKG sigH clock clock_pol
108 if (nusers(sigH) == 2 &&
109 (mul->type != \SB_MAC16 ||
110 (!param(mul, \TOP_8x8_MULT_REG, State::S0).as_bool() && !param(mul, \BOT_8x8_MULT_REG, State::S0).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1, State::S0).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1, State::S0).as_bool()))) {
112 subpattern(out_dffe);
114 // F/J/K/G do not have a CE-like (hold) input
118 // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
119 // shared with A and B
120 if ((ffArstmux != NULL) != (dffrstmux != NULL))
122 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
125 if (port(ffArstmux, \S) != port(dffrstmux, \S))
127 if (ffArstpol != dffrstpol)
131 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
133 if (ffBrstpol != dffrstpol)
139 clock_pol = dffclock_pol;
147 code argD ffH sigH sigO clock clock_pol
148 if (ffFJKG && nusers(sigH) == 2 &&
149 (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2, State::S0).as_bool())) {
151 subpattern(out_dffe);
153 // H does not have a CE-like (hold) input
157 // Reset signal of H (IRSTBOT) shared with B
158 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
161 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
163 if (ffBrstpol != dffrstpol)
169 clock_pol = dffclock_pol;
180 if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT, State::S0).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT, State::S0).as_int() == 3)
182 select add->type.in($add)
183 choice <IdString> AB {\A, \B}
184 select nusers(port(add, AB)) == 2
186 index <SigBit> port(add, AB)[0] === sigH[0]
187 filter GetSize(port(add, AB)) <= GetSize(sigH)
188 filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
189 filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
194 code sigCD sigO cd_signed
196 sigCD = port(add, addAB == \A ? \B : \A);
197 cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
199 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
200 int actual_mul_width = GetSize(sigH);
201 int actual_acc_width = GetSize(sigCD);
203 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
205 // If accumulator, check adder width and signedness
206 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED, State::S0).as_bool() != param(add, \A_SIGNED).as_bool()))
209 sigO = port(add, \Y);
214 select mux->type == $mux
215 choice <IdString> AB {\A, \B}
216 select nusers(port(mux, AB)) == 2
217 index <SigSpec> port(mux, AB) === sigO
224 sigO = port(mux, \Y);
227 code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
228 if (mul->type != \SB_MAC16 ||
229 // Ensure that register is not already used
230 ((param(mul, \TOPOUTPUT_SELECT, 0).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT, 0).as_int() != 1) &&
231 // Ensure that OLOADTOP/OLOADBOT is unused or zero
232 (port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
236 // First try entire sigO
237 if (nusers(sigO) == 2) {
239 subpattern(out_dffe);
242 // Otherwise try just its least significant 16 bits
243 if (!dff && GetSize(sigO) > 16) {
244 argD = sigO.extract(0, 16);
245 if (nusers(argD) == 2) {
246 subpattern(out_dffe);
254 clock_pol = dffclock_pol;
256 ffOrstmux = dffrstmux;
257 ffOrstpol = dffrstpol;
260 ffOholdmux = dffholdmux;
261 ffOholdpol = dffholdpol;
264 sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
267 // Loading value into output register is not
268 // supported unless using accumulator
272 sigCD = port(mux, muxAB == \B ? \A : \B);
274 cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
279 code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
280 if (!sigCD.empty() && sigCD != sigO &&
281 (mul->type != \SB_MAC16 || (!param(mul, \C_REG, State::S0).as_bool() && !param(mul, \D_REG, State::S0).as_bool()))) {
286 ffCDholdmux = dffholdmux;
287 ffCDholdpol = dffholdpol;
290 // Reset signal of C (IRSTTOP) and D (IRSTBOT)
291 // shared with A and B
292 if ((ffArstmux != NULL) != (dffrstmux != NULL))
294 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
297 if (port(ffArstmux, \S) != port(dffrstmux, \S))
299 if (ffArstpol != dffrstpol)
303 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
305 if (ffBrstpol != dffrstpol)
311 clock_pol = dffclock_pol;
320 sigCD.extend_u0(32, cd_signed);
327 // #######################
330 arg argD argQ clock clock_pol
336 for (auto c : argQ.chunks()) {
339 if (c.wire->get_bool_attribute(\keep))
341 Const init = c.wire->attributes.at(\init, State::Sx);
342 if (!init.is_fully_undef() && !init.is_fully_zero())
348 select ff->type.in($dff)
349 // DSP48E1 does not support clock inversion
350 select param(ff, \CLK_POLARITY).as_bool()
352 slice offset GetSize(port(ff, \D))
353 index <SigBit> port(ff, \Q)[offset] === argQ[0]
355 // Check that the rest of argQ is present
356 filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
357 filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
364 if (clock != SigBit()) {
365 if (port(ff, \CLK) != clock)
367 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
371 SigSpec Q = port(ff, \Q);
373 dffclock = port(ff, \CLK);
374 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
378 dffD.replace(argQ, argD);
379 // Only search for ffrstmux if dffD only
380 // has two (ff, ffrstmux) users
381 if (nusers(dffD) > 2)
387 if false /* TODO: ice40 resets are actually async */
390 select ffrstmux->type.in($mux)
391 index <SigSpec> port(ffrstmux, \Y) === argD
393 choice <IdString> BA {\B, \A}
394 // DSP48E1 only supports reset to zero
395 select port(ffrstmux, BA).is_fully_zero()
397 define <bool> pol (BA == \B)
404 dffrstmux = ffrstmux;
405 dffrstpol = ffrstpol;
406 argD = port(ffrstmux, ffrstpol ? \A : \B);
407 dffD.replace(port(ffrstmux, \Y), argD);
409 // Only search for ffholdmux if argQ has at
410 // least 3 users (ff, <upstream>, ffrstmux) and
411 // dffD only has two (ff, ffrstmux)
412 if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
421 select ffholdmux->type.in($mux)
422 index <SigSpec> port(ffholdmux, \Y) === argD
423 choice <IdString> BA {\B, \A}
424 index <SigSpec> port(ffholdmux, BA) === argQ
425 define <bool> pol (BA == \B)
432 dffholdmux = ffholdmux;
433 dffholdpol = ffholdpol;
434 argD = port(ffholdmux, ffholdpol ? \A : \B);
435 dffD.replace(port(ffholdmux, \Y), argD);
438 dffholdmux = nullptr;
441 // #######################
444 arg argD argQ clock clock_pol
448 for (auto c : argD.chunks())
449 if (c.wire->get_bool_attribute(\keep))
454 select ffholdmux->type.in($mux)
455 // ffholdmux output must have two users: ffholdmux and ff.D
456 select nusers(port(ffholdmux, \Y)) == 2
458 choice <IdString> BA {\B, \A}
459 // keep-last-value net must have at least three users: ffholdmux, ff, downstream sink(s)
460 select nusers(port(ffholdmux, BA)) >= 3
462 slice offset GetSize(port(ffholdmux, \Y))
463 define <IdString> AB (BA == \B ? \A : \B)
464 index <SigBit> port(ffholdmux, AB)[offset] === argD[0]
466 // Check that the rest of argD is present
467 filter GetSize(port(ffholdmux, AB)) >= offset + GetSize(argD)
468 filter port(ffholdmux, AB).extract(offset, GetSize(argD)) == argD
471 define <bool> pol (BA == \B)
478 dffholdmux = ffholdmux;
480 SigSpec AB = port(ffholdmux, ffholdpol ? \A : \B);
481 SigSpec Y = port(ffholdmux, \Y);
484 argQ.replace(AB, port(ffholdmux, ffholdpol ? \B : \A));
486 dffholdmux = ffholdmux;
487 dffholdpol = ffholdpol;
492 if false /* TODO: ice40 resets are actually async */
494 select ffrstmux->type.in($mux)
495 // ffrstmux output must have two users: ffrstmux and ff.D
496 select nusers(port(ffrstmux, \Y)) == 2
498 choice <IdString> BA {\B, \A}
499 // DSP48E1 only supports reset to zero
500 select port(ffrstmux, BA).is_fully_zero()
502 slice offset GetSize(port(ffrstmux, \Y))
503 define <IdString> AB (BA == \B ? \A : \B)
504 index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
506 // Check that offset is consistent
507 filter !ffholdmux || ffoffset == offset
508 // Check that the rest of argD is present
509 filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
510 filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
513 define <bool> pol (AB == \A)
520 dffrstmux = ffrstmux;
522 SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
523 SigSpec Y = port(ffrstmux, \Y);
526 dffrstmux = ffrstmux;
527 dffrstpol = ffrstpol;
532 select ff->type.in($dff)
533 // DSP48E1 does not support clock inversion
534 select param(ff, \CLK_POLARITY).as_bool()
536 slice offset GetSize(port(ff, \D))
537 index <SigBit> port(ff, \D)[offset] === argD[0]
539 // Check that offset is consistent
540 filter (!ffholdmux && !ffrstmux) || ffoffset == offset
541 // Check that the rest of argD is present
542 filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
543 filter port(ff, \D).extract(offset, GetSize(argD)) == argD
544 // Check that FF.Q is connected to CE-mux
545 filter !ffholdmux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
552 if (clock != SigBit()) {
553 if (port(ff, \CLK) != clock)
555 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
558 SigSpec D = port(ff, \D);
559 SigSpec Q = port(ff, \Q);
565 for (auto c : argQ.chunks()) {
566 Const init = c.wire->attributes.at(\init, State::Sx);
567 if (!init.is_fully_undef() && !init.is_fully_zero())
573 dffclock = port(ff, \CLK);
574 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
576 // No enable/reset mux possible without flop
577 else if (dffholdmux || dffrstmux)