passes/pmgen/ice40_dsp.pmg

   1 pattern ice40_dsp
   2
   3 state <SigBit> clock
   4 state <bool> clock_pol
   5 state <SigSpec> sigA sigB sigCD sigH sigO sigOused
   6 state <Cell*> addAB muxAB
   7
   8 match mul
   9         select mul->type.in($mul, \SB_MAC16)
  10         select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
  11 endmatch
  12
  13 code sigH
  14         if (mul->type == $mul)
  15                 sigH = mul->getPort(\Y);
  16         else if (mul->type == \SB_MAC16)
  17                 sigH = mul->getPort(\O);
  18         else log_abort();
  19         if (GetSize(sigH) <= 10)
  20                 reject;
  21 endcode
  22
  23 match ffA
  24         if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
  25         if !port(mul, \A).remove_const().empty()
  26         select ffA->type.in($dff)
  27         filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
  28         optional
  29 endmatch
  30
  31 code sigA clock clock_pol
  32         sigA = port(mul, \A);
  33
  34         if (ffA) {
  35                 for (auto b : port(ffA, \Q))
  36                         if (b.wire->get_bool_attribute(\keep))
  37                                 reject;
  38
  39                 clock = port(ffA, \CLK).as_bit();
  40                 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
  41
  42                 sigA.replace(port(ffA, \Q), port(ffA, \D));
  43         }
  44 endcode
  45
  46 match ffB
  47         if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
  48         if !port(mul, \B).remove_const().empty()
  49         select ffB->type.in($dff)
  50         filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
  51         optional
  52 endmatch
  53
  54 code sigB clock clock_pol
  55         sigB = port(mul, \B);
  56
  57         if (ffB) {
  58                 for (auto b : port(ffB, \Q))
  59                         if (b.wire->get_bool_attribute(\keep))
  60                                 reject;
  61
  62                 SigBit c = port(ffB, \CLK).as_bit();
  63                 bool cp = param(ffB, \CLK_POLARITY).as_bool();
  64
  65                 if (clock != SigBit() && (c != clock || cp != clock_pol))
  66                         reject;
  67
  68                 clock = c;
  69                 clock_pol = cp;
  70
  71                 sigB.replace(port(ffB, \Q), port(ffB, \D));
  72         }
  73 endcode
  74
  75 match ffH
  76         if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
  77         select ffH->type.in($dff)
  78         select nusers(port(ffH, \D)) == 2
  79         index <SigSpec> port(ffH, \D) === sigH
  80         // Ensure pipeline register is not already used
  81         optional
  82 endmatch
  83
  84 code sigH sigO clock clock_pol
  85         sigO = sigH;
  86
  87         if (ffH) {
  88                 sigH = port(ffH, \Q);
  89                 for (auto b : sigH)
  90                         if (b.wire->get_bool_attribute(\keep))
  91                                 reject;
  92
  93                 sigO = sigH;
  94
  95                 SigBit c = port(ffH, \CLK).as_bit();
  96                 bool cp = param(ffH, \CLK_POLARITY).as_bool();
  97
  98                 if (clock != SigBit() && (c != clock || cp != clock_pol))
  99                         reject;
 100
 101                 clock = c;
 102                 clock_pol = cp;
 103         }
 104 endcode
 105
 106 match addA
 107         select addA->type.in($add)
 108         select nusers(port(addA, \A)) == 2
 109         filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
 110         //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
 111         filter port(addA, \A) ==  sigH.extract(0, param(addA, \A_WIDTH).as_int())
 112         optional
 113 endmatch
 114
 115 match addB
 116         if !addA
 117         select addB->type.in($add, $sub)
 118         select nusers(port(addB, \B)) == 2
 119         filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
 120         //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
 121         filter port(addB, \B) ==  sigH.extract(0, param(addB, \B_WIDTH).as_int())
 122         optional
 123 endmatch
 124
 125 code addAB sigCD sigO
 126         bool CD_SIGNED = false;
 127         if (addA) {
 128                 addAB = addA;
 129                 sigCD = port(addAB, \B);
 130                 CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
 131         }
 132         if (addB) {
 133                 addAB = addB;
 134                 sigCD = port(addAB, \A);
 135                 CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
 136         }
 137         if (addAB) {
 138                 if (mul->type == \SB_MAC16) {
 139                         // Ensure that adder is not used
 140                         if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
 141                                         param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
 142                                 reject;
 143                 }
 144
 145                 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
 146                 int actual_mul_width = GetSize(sigH);
 147                 int actual_acc_width = GetSize(sigCD);
 148
 149                 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
 150                         reject;
 151                 // If accumulator, check adder width and signedness
 152                 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
 153                         reject;
 154
 155                 sigO = port(addAB, \Y);
 156                 sigCD.extend_u0(32, CD_SIGNED);
 157         }
 158 endcode
 159
 160 match muxA
 161         select muxA->type.in($mux)
 162         index <int> nusers(port(muxA, \A)) === 2
 163         index <SigSpec> port(muxA, \A) === sigO
 164         optional
 165 endmatch
 166
 167 match muxB
 168         if !muxA
 169         select muxB->type.in($mux)
 170         index <int> nusers(port(muxB, \B)) === 2
 171         index <SigSpec> port(muxB, \B) === sigO
 172         optional
 173 endmatch
 174
 175 code muxAB
 176         if (muxA)
 177                 muxAB = muxA;
 178         else if (muxB)
 179                 muxAB = muxB;
 180 endcode
 181
 182 // Extract the bits of P that actually have a consumer
 183 // (as opposed to being a dummy)
 184 code sigOused
 185         for (int i = 0; i < GetSize(sigO); i++)
 186                 if (!sigO[i].wire || nusers(sigO[i]) == 1)
 187                         sigOused.append(State::Sx);
 188                 else
 189                         sigOused.append(sigO[i]);
 190 endcode
 191
 192 match ffO_lo
 193         if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
 194         select ffO_lo->type.in($dff)
 195         filter includes(port(ffO_lo, \D).to_sigbit_set(), sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int())).remove_const().to_sigbit_set())
 196         optional
 197 endmatch
 198
 199 match ffO_hi
 200         if GetSize(sigOused) > 16
 201         if nusers(sigOused.extract_end(16)) == 2
 202         select ffO_hi->type.in($dff)
 203         filter includes(port(ffO_hi, \D).to_sigbit_set(), sigOused.extract_end(16).remove_const().to_sigbit_set())
 204         optional
 205 endmatch
 206
 207 code clock clock_pol sigO sigCD
 208         if (ffO_lo || ffO_hi) {
 209                 if (mul->type == \SB_MAC16) {
 210                         // Ensure that register is not already used
 211                         if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
 212                                         param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
 213                                 reject;
 214
 215                         // Ensure that OLOADTOP/OLOADBOT is unused or zero
 216                         if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
 217                                 || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
 218                                 reject;
 219                 }
 220
 221                 if (ffO_lo) {
 222                         for (auto b : port(ffO_lo, \Q))
 223                                 if (b.wire->get_bool_attribute(\keep))
 224                                         reject;
 225
 226                         SigBit c = port(ffO_lo, \CLK).as_bit();
 227                         bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
 228
 229                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 230                                 reject;
 231
 232                         clock = c;
 233                         clock_pol = cp;
 234
 235                         sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
 236                 }
 237
 238                 if (ffO_hi) {
 239                         for (auto b : port(ffO_hi, \Q))
 240                                 if (b.wire->get_bool_attribute(\keep))
 241                                         reject;
 242
 243                         SigBit c = port(ffO_hi, \CLK).as_bit();
 244                         bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
 245
 246                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 247                                 reject;
 248
 249                         clock = c;
 250                         clock_pol = cp;
 251
 252                         sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
 253                 }
 254
 255                 // Loading value into output register is not
 256                 //   supported unless using accumulator
 257                 if (muxAB) {
 258                         if (sigCD != sigO)
 259                                 reject;
 260                         if (muxA)
 261                                 sigCD = port(muxAB, \B);
 262                         else if (muxB)
 263                                 sigCD = port(muxAB, \A);
 264                         else log_abort();
 265                         sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
 266                 }
 267         }
 268         accept;
 269 endcode