5 state <std::set<SigBit>> sigAset sigBset
6 state <SigSpec> sigA sigB sigCD sigH sigO sigOused
7 state <Cell*> addAB muxAB
10 select mul->type.in($mul, \SB_MAC16)
11 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
15 SigSpec A = port(mul, \A);
17 sigAset = A.to_sigbit_set();
18 SigSpec B = port(mul, \B);
20 sigBset = B.to_sigbit_set();
24 if (mul->type == $mul)
25 sigH = mul->getPort(\Y);
26 else if (mul->type == \SB_MAC16)
27 sigH = mul->getPort(\O);
29 if (GetSize(sigH) <= 10)
34 if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
36 select ffA->type.in($dff)
40 code sigA clock clock_pol
44 auto ffAset = port(ffA, \Q).to_sigbit_set();
45 if (!std::includes(ffAset.begin(), ffAset.end(), sigAset.begin(), sigAset.end()))
48 for (auto b : port(ffA, \Q))
49 if (b.wire->get_bool_attribute(\keep))
52 clock = port(ffA, \CLK).as_bit();
53 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
55 sigA.replace(port(ffA, \Q), port(ffA, \D));
60 if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
62 select ffB->type.in($dff)
66 code sigB clock clock_pol
70 auto ffBset = port(ffB, \Q).to_sigbit_set();
71 if (!std::includes(ffBset.begin(), ffBset.end(), sigBset.begin(), sigBset.end()))
74 for (auto b : port(ffB, \Q))
75 if (b.wire->get_bool_attribute(\keep))
78 SigBit c = port(ffB, \CLK).as_bit();
79 bool cp = param(ffB, \CLK_POLARITY).as_bool();
81 if (clock != SigBit() && (c != clock || cp != clock_pol))
87 sigB.replace(port(ffB, \Q), port(ffB, \D));
92 if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
93 select ffFJKG->type.in($dff)
94 select nusers(port(ffFJKG, \D)) == 2
95 index <SigSpec> port(ffFJKG, \D) === sigH
96 // Ensure pipeline register is not already used
100 code sigH sigO clock clock_pol
102 sigH = port(ffFJKG, \Q);
104 if (b.wire->get_bool_attribute(\keep))
107 SigBit c = port(ffFJKG, \CLK).as_bit();
108 bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
110 if (clock != SigBit() && (c != clock || cp != clock_pol))
121 select addA->type.in($add)
122 select nusers(port(addA, \A)) == 2
123 filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
124 //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
125 filter port(addA, \A) == sigH.extract(0, param(addA, \A_WIDTH).as_int())
131 select addB->type.in($add, $sub)
132 select nusers(port(addB, \B)) == 2
133 filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
134 //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
135 filter port(addB, \B) == sigH.extract(0, param(addB, \B_WIDTH).as_int())
139 code addAB sigCD sigO
140 bool CD_SIGNED = false;
143 sigCD = port(addAB, \B);
144 CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
148 sigCD = port(addAB, \A);
149 CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
152 if (mul->type == \SB_MAC16) {
153 // Ensure that adder is not used
154 if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
155 param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
159 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
160 int actual_mul_width = GetSize(sigH);
161 int actual_acc_width = GetSize(sigCD);
163 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
165 // If accumulator, check adder width and signedness
166 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
169 sigO = port(addAB, \Y);
170 sigCD.extend_u0(32, CD_SIGNED);
175 select muxA->type.in($mux)
176 index <int> nusers(port(muxA, \A)) === 2
177 index <SigSpec> port(muxA, \A) === sigO
183 select muxB->type.in($mux)
184 index <int> nusers(port(muxB, \B)) === 2
185 index <SigSpec> port(muxB, \B) === sigO
196 // Extract the bits of P that actually have a consumer
197 // (as opposed to being a dummy)
199 for (int i = 0; i < GetSize(sigO); i++)
200 if (!sigO[i].wire || nusers(sigO[i]) == 1)
201 sigOused.append(State::Sx);
203 sigOused.append(sigO[i]);
207 if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
208 select ffO_lo->type.in($dff)
214 SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
216 auto ffO_loSet = port(ffO_lo, \D).to_sigbit_set();
217 auto Oset = O.to_sigbit_set();
218 if (!std::includes(ffO_loSet.begin(), ffO_loSet.end(), Oset.begin(), Oset.end()))
224 if GetSize(sigOused) > 16
225 if nusers(sigOused.extract_end(16)) == 2
226 select ffO_hi->type.in($dff)
232 SigSpec O = sigOused.extract_end(16);
234 auto ffO_hiSet = port(ffO_hi, \D).to_sigbit_set();
235 auto Oset = O.to_sigbit_set();
236 if (!std::includes(ffO_hiSet.begin(), ffO_hiSet.end(), Oset.begin(), Oset.end()))
241 code clock clock_pol sigO sigCD
242 if (ffO_lo || ffO_hi) {
243 if (mul->type == \SB_MAC16) {
244 // Ensure that register is not already used
245 if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
246 param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
249 // Ensure that OLOADTOP/OLOADBOT is unused or zero
250 if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
251 || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
256 for (auto b : port(ffO_lo, \Q))
257 if (b.wire->get_bool_attribute(\keep))
260 SigBit c = port(ffO_lo, \CLK).as_bit();
261 bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
263 if (clock != SigBit() && (c != clock || cp != clock_pol))
269 sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
273 for (auto b : port(ffO_hi, \Q))
274 if (b.wire->get_bool_attribute(\keep))
277 SigBit c = port(ffO_hi, \CLK).as_bit();
278 bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
280 if (clock != SigBit() && (c != clock || cp != clock_pol))
286 sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
289 // Loading value into output register is not
290 // supported unless using accumulator
295 sigCD = port(muxAB, \B);
297 sigCD = port(muxAB, \A);
299 sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());