5 state <std::set<SigBit>> sigAset sigBset
6 state <SigSpec> sigA sigB sigCD sigH sigO sigOused
7 state <Cell*> addAB muxAB
10 select mul->type.in($mul, \SB_MAC16)
11 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
15 SigSpec A = port(mul, \A);
17 sigAset = A.to_sigbit_set();
18 SigSpec B = port(mul, \B);
20 sigBset = B.to_sigbit_set();
24 if (mul->type == $mul)
25 sigH = mul->getPort(\Y);
26 else if (mul->type == \SB_MAC16)
27 sigH = mul->getPort(\O);
29 if (GetSize(sigH) <= 10)
34 if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
36 select ffA->type.in($dff)
37 filter includes(port(ffA, \Q).to_sigbit_set(), sigAset)
41 code sigA clock clock_pol
45 for (auto b : port(ffA, \Q))
46 if (b.wire->get_bool_attribute(\keep))
49 clock = port(ffA, \CLK).as_bit();
50 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
52 sigA.replace(port(ffA, \Q), port(ffA, \D));
57 if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
59 select ffB->type.in($dff)
60 filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
64 code sigB clock clock_pol
68 for (auto b : port(ffB, \Q))
69 if (b.wire->get_bool_attribute(\keep))
72 SigBit c = port(ffB, \CLK).as_bit();
73 bool cp = param(ffB, \CLK_POLARITY).as_bool();
75 if (clock != SigBit() && (c != clock || cp != clock_pol))
81 sigB.replace(port(ffB, \Q), port(ffB, \D));
86 if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
87 select ffFJKG->type.in($dff)
88 select nusers(port(ffFJKG, \D)) == 2
89 index <SigSpec> port(ffFJKG, \D) === sigH
90 // Ensure pipeline register is not already used
94 code sigH sigO clock clock_pol
98 sigH = port(ffFJKG, \Q);
100 if (b.wire->get_bool_attribute(\keep))
105 SigBit c = port(ffFJKG, \CLK).as_bit();
106 bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
108 if (clock != SigBit() && (c != clock || cp != clock_pol))
117 select addA->type.in($add)
118 select nusers(port(addA, \A)) == 2
119 filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
120 //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
121 filter port(addA, \A) == sigH.extract(0, param(addA, \A_WIDTH).as_int())
127 select addB->type.in($add, $sub)
128 select nusers(port(addB, \B)) == 2
129 filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
130 //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
131 filter port(addB, \B) == sigH.extract(0, param(addB, \B_WIDTH).as_int())
135 code addAB sigCD sigO
136 bool CD_SIGNED = false;
139 sigCD = port(addAB, \B);
140 CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
144 sigCD = port(addAB, \A);
145 CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
148 if (mul->type == \SB_MAC16) {
149 // Ensure that adder is not used
150 if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
151 param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
155 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
156 int actual_mul_width = GetSize(sigH);
157 int actual_acc_width = GetSize(sigCD);
159 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
161 // If accumulator, check adder width and signedness
162 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
165 sigO = port(addAB, \Y);
166 sigCD.extend_u0(32, CD_SIGNED);
171 select muxA->type.in($mux)
172 index <int> nusers(port(muxA, \A)) === 2
173 index <SigSpec> port(muxA, \A) === sigO
179 select muxB->type.in($mux)
180 index <int> nusers(port(muxB, \B)) === 2
181 index <SigSpec> port(muxB, \B) === sigO
192 // Extract the bits of P that actually have a consumer
193 // (as opposed to being a dummy)
195 for (int i = 0; i < GetSize(sigO); i++)
196 if (!sigO[i].wire || nusers(sigO[i]) == 1)
197 sigOused.append(State::Sx);
199 sigOused.append(sigO[i]);
203 if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
204 select ffO_lo->type.in($dff)
210 SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
212 if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set()))
218 if GetSize(sigOused) > 16
219 if nusers(sigOused.extract_end(16)) == 2
220 select ffO_hi->type.in($dff)
226 SigSpec O = sigOused.extract_end(16);
228 if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set()))
233 code clock clock_pol sigO sigCD
234 if (ffO_lo || ffO_hi) {
235 if (mul->type == \SB_MAC16) {
236 // Ensure that register is not already used
237 if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
238 param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
241 // Ensure that OLOADTOP/OLOADBOT is unused or zero
242 if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
243 || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
248 for (auto b : port(ffO_lo, \Q))
249 if (b.wire->get_bool_attribute(\keep))
252 SigBit c = port(ffO_lo, \CLK).as_bit();
253 bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
255 if (clock != SigBit() && (c != clock || cp != clock_pol))
261 sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
265 for (auto b : port(ffO_hi, \Q))
266 if (b.wire->get_bool_attribute(\keep))
269 SigBit c = port(ffO_hi, \CLK).as_bit();
270 bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
272 if (clock != SigBit() && (c != clock || cp != clock_pol))
278 sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
281 // Loading value into output register is not
282 // supported unless using accumulator
287 sigCD = port(muxAB, \B);
289 sigCD = port(muxAB, \A);
291 sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());