passes/pmgen/ice40_dsp.pmg

   1 pattern ice40_dsp
   2
   3 state <SigBit> clock
   4 state <bool> clock_pol
   5 state <std::set<SigBit>> sigAset sigBset
   6 state <SigSpec> sigA sigB sigCD sigH sigO sigOused
   7 state <Cell*> addAB muxAB
   8
   9 match mul
  10         select mul->type.in($mul, \SB_MAC16)
  11         select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
  12 endmatch
  13
  14 code sigAset sigBset
  15         SigSpec A = port(mul, \A);
  16         A.remove_const();
  17         sigAset = A.to_sigbit_set();
  18         SigSpec B = port(mul, \B);
  19         B.remove_const();
  20         sigBset = B.to_sigbit_set();
  21 endcode
  22
  23 code sigH
  24         if (mul->type == $mul)
  25                 sigH = mul->getPort(\Y);
  26         else if (mul->type == \SB_MAC16)
  27                 sigH = mul->getPort(\O);
  28         else log_abort();
  29         if (GetSize(sigH) <= 10)
  30                 reject;
  31 endcode
  32
  33 match ffA
  34         if mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()
  35         if !sigAset.empty()
  36         select ffA->type.in($dff)
  37         filter includes(port(ffA, \Q).to_sigbit_set(), sigAset)
  38         optional
  39 endmatch
  40
  41 code sigA clock clock_pol
  42         sigA = port(mul, \A);
  43
  44         if (ffA) {
  45                 for (auto b : port(ffA, \Q))
  46                         if (b.wire->get_bool_attribute(\keep))
  47                                 reject;
  48
  49                 clock = port(ffA, \CLK).as_bit();
  50                 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
  51
  52                 sigA.replace(port(ffA, \Q), port(ffA, \D));
  53         }
  54 endcode
  55
  56 match ffB
  57         if mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()
  58         if !sigBset.empty()
  59         select ffB->type.in($dff)
  60         filter includes(port(ffB, \Q).to_sigbit_set(), sigBset)
  61         optional
  62 endmatch
  63
  64 code sigB clock clock_pol
  65         sigB = port(mul, \B);
  66
  67         if (ffB) {
  68                 for (auto b : port(ffB, \Q))
  69                         if (b.wire->get_bool_attribute(\keep))
  70                                 reject;
  71
  72                 SigBit c = port(ffB, \CLK).as_bit();
  73                 bool cp = param(ffB, \CLK_POLARITY).as_bool();
  74
  75                 if (clock != SigBit() && (c != clock || cp != clock_pol))
  76                         reject;
  77
  78                 clock = c;
  79                 clock_pol = cp;
  80
  81                 sigB.replace(port(ffB, \Q), port(ffB, \D));
  82         }
  83 endcode
  84
  85 match ffFJKG
  86         if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
  87         select ffFJKG->type.in($dff)
  88         select nusers(port(ffFJKG, \D)) == 2
  89         index <SigSpec> port(ffFJKG, \D) === sigH
  90         // Ensure pipeline register is not already used
  91         optional
  92 endmatch
  93
  94 code sigH sigO clock clock_pol
  95         if (ffFJKG) {
  96                 sigH = port(ffFJKG, \Q);
  97                 for (auto b : sigH)
  98                         if (b.wire->get_bool_attribute(\keep))
  99                                 reject;
 100
 101                 SigBit c = port(ffFJKG, \CLK).as_bit();
 102                 bool cp = param(ffFJKG, \CLK_POLARITY).as_bool();
 103
 104                 if (clock != SigBit() && (c != clock || cp != clock_pol))
 105                         reject;
 106
 107                 clock = c;
 108                 clock_pol = cp;
 109         }
 110
 111         sigO = sigH;
 112 endcode
 113
 114 match addA
 115         select addA->type.in($add)
 116         select nusers(port(addA, \A)) == 2
 117         filter param(addA, \A_WIDTH).as_int() <= GetSize(sigH)
 118         //index <SigSpec> port(addA, \A) === sigH.extract(0, param(addA, \A_WIDTH).as_int())
 119         filter port(addA, \A) ==  sigH.extract(0, param(addA, \A_WIDTH).as_int())
 120         optional
 121 endmatch
 122
 123 match addB
 124         if !addA
 125         select addB->type.in($add, $sub)
 126         select nusers(port(addB, \B)) == 2
 127         filter param(addB, \B_WIDTH).as_int() <= GetSize(sigH)
 128         //index <SigSpec> port(addB, \B) === sigH.extract(0, param(addB, \B_WIDTH).as_int())
 129         filter port(addB, \B) ==  sigH.extract(0, param(addB, \B_WIDTH).as_int())
 130         optional
 131 endmatch
 132
 133 code addAB sigCD sigO
 134         bool CD_SIGNED = false;
 135         if (addA) {
 136                 addAB = addA;
 137                 sigCD = port(addAB, \B);
 138                 CD_SIGNED = param(addAB, \B_SIGNED).as_bool();
 139         }
 140         if (addB) {
 141                 addAB = addB;
 142                 sigCD = port(addAB, \A);
 143                 CD_SIGNED = param(addAB, \A_SIGNED).as_bool();
 144         }
 145         if (addAB) {
 146                 if (mul->type == \SB_MAC16) {
 147                         // Ensure that adder is not used
 148                         if (param(mul, \TOPOUTPUT_SELECT).as_int() != 3 ||
 149                                         param(mul, \BOTOUTPUT_SELECT).as_int() != 3)
 150                                 reject;
 151                 }
 152
 153                 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
 154                 int actual_mul_width = GetSize(sigH);
 155                 int actual_acc_width = GetSize(sigCD);
 156
 157                 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
 158                         reject;
 159                 // If accumulator, check adder width and signedness
 160                 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
 161                         reject;
 162
 163                 sigO = port(addAB, \Y);
 164                 sigCD.extend_u0(32, CD_SIGNED);
 165         }
 166 endcode
 167
 168 match muxA
 169         select muxA->type.in($mux)
 170         index <int> nusers(port(muxA, \A)) === 2
 171         index <SigSpec> port(muxA, \A) === sigO
 172         optional
 173 endmatch
 174
 175 match muxB
 176         if !muxA
 177         select muxB->type.in($mux)
 178         index <int> nusers(port(muxB, \B)) === 2
 179         index <SigSpec> port(muxB, \B) === sigO
 180         optional
 181 endmatch
 182
 183 code muxAB
 184         if (muxA)
 185                 muxAB = muxA;
 186         else if (muxB)
 187                 muxAB = muxB;
 188 endcode
 189
 190 // Extract the bits of P that actually have a consumer
 191 // (as opposed to being a dummy)
 192 code sigOused
 193         for (int i = 0; i < GetSize(sigO); i++)
 194                 if (!sigO[i].wire || nusers(sigO[i]) == 1)
 195                         sigOused.append(State::Sx);
 196                 else
 197                         sigOused.append(sigO[i]);
 198 endcode
 199
 200 match ffO_lo
 201         if nusers(sigOused.extract(0,std::min(16,GetSize(sigOused)))) == 2
 202         select ffO_lo->type.in($dff)
 203         optional
 204 endmatch
 205
 206 code
 207         if (ffO_lo) {
 208                 SigSpec O = sigOused.extract(0,std::min(16,param(ffO_lo, \WIDTH).as_int()));
 209                 O.remove_const();
 210                 if (!includes(port(ffO_lo, \D).to_sigbit_set(), O.to_sigbit_set()))
 211                         reject;
 212         }
 213 endcode
 214
 215 match ffO_hi
 216         if GetSize(sigOused) > 16
 217         if nusers(sigOused.extract_end(16)) == 2
 218         select ffO_hi->type.in($dff)
 219         optional
 220 endmatch
 221
 222 code
 223         if (ffO_hi) {
 224                 SigSpec O = sigOused.extract_end(16);
 225                 O.remove_const();
 226                 if (!includes(port(ffO_hi, \D).to_sigbit_set(), O.to_sigbit_set()))
 227                         reject;
 228         }
 229 endcode
 230
 231 code clock clock_pol sigO sigCD
 232         if (ffO_lo || ffO_hi) {
 233                 if (mul->type == \SB_MAC16) {
 234                         // Ensure that register is not already used
 235                         if (param(mul, \TOPOUTPUT_SELECT).as_int() == 1 ||
 236                                         param(mul, \BOTOUTPUT_SELECT).as_int() == 1)
 237                                 reject;
 238
 239                         // Ensure that OLOADTOP/OLOADBOT is unused or zero
 240                         if ((mul->hasPort(\OLOADTOP) && !port(mul, \OLOADTOP).is_fully_zero())
 241                                 || (mul->hasPort(\OLOADBOT) && !port(mul, \OLOADBOT).is_fully_zero()))
 242                                 reject;
 243                 }
 244
 245                 if (ffO_lo) {
 246                         for (auto b : port(ffO_lo, \Q))
 247                                 if (b.wire->get_bool_attribute(\keep))
 248                                         reject;
 249
 250                         SigBit c = port(ffO_lo, \CLK).as_bit();
 251                         bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
 252
 253                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 254                                 reject;
 255
 256                         clock = c;
 257                         clock_pol = cp;
 258
 259                         sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
 260                 }
 261
 262                 if (ffO_hi) {
 263                         for (auto b : port(ffO_hi, \Q))
 264                                 if (b.wire->get_bool_attribute(\keep))
 265                                         reject;
 266
 267                         SigBit c = port(ffO_hi, \CLK).as_bit();
 268                         bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
 269
 270                         if (clock != SigBit() && (c != clock || cp != clock_pol))
 271                                 reject;
 272
 273                         clock = c;
 274                         clock_pol = cp;
 275
 276                         sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
 277                 }
 278
 279                 // Loading value into output register is not
 280                 //   supported unless using accumulator
 281                 if (muxAB) {
 282                         if (sigCD != sigO)
 283                                 reject;
 284                         if (muxA)
 285                                 sigCD = port(muxAB, \B);
 286                         else if (muxB)
 287                                 sigCD = port(muxAB, \A);
 288                         else log_abort();
 289                         sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
 290                 }
 291         }
 292         accept;
 293 endcode