3 udata <std::function<SigSpec(const SigSpec&)>> unextend
5 state <bool> clock_pol cd_signed o_lo
6 state <SigSpec> sigA sigB sigCD sigH sigO
8 state <IdString> addAB muxAB
10 state <bool> ffAholdpol ffBholdpol ffCDholdpol ffOholdpol
11 state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
13 state <Cell*> ffA ffAholdmux ffArstmux ffB ffBholdmux ffBrstmux ffCD ffCDholdmux
14 state <Cell*> ffFJKG ffH ffO ffOholdmux ffOrstmux
17 state <SigSpec> argQ argD
18 state <bool> ffholdpol ffrstpol
20 udata <SigSpec> dffD dffQ
21 udata <SigBit> dffclock
22 udata <Cell*> dff dffholdmux dffrstmux
23 udata <bool> dffholdpol dffrstpol dffclock_pol
26 select mul->type.in($mul, \SB_MAC16)
27 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
31 unextend = [](const SigSpec &sig) {
33 for (i = GetSize(sig)-1; i > 0; i--)
34 if (sig[i] != sig[i-1])
36 // Do not remove non-const sign bit
39 return sig.extract(0, i);
41 sigA = unextend(port(mul, \A));
42 sigB = unextend(port(mul, \B));
45 if (mul->type == $mul)
47 else if (mul->type == \SB_MAC16)
53 // Only care about those bits that are used
55 for (i = 0; i < GetSize(O); i++) {
56 if (nusers(O[i]) <= 1)
60 log_assert(nusers(O.extract_end(i)) <= 1);
63 code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
64 if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
70 clock_pol = dffclock_pol;
72 ffArstmux = dffrstmux;
73 ffArstpol = dffrstpol;
76 ffAholdmux = dffholdmux;
77 ffAholdpol = dffholdpol;
84 code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
85 if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
91 clock_pol = dffclock_pol;
93 ffBrstmux = dffrstmux;
94 ffBrstpol = dffrstpol;
97 ffBholdmux = dffholdmux;
98 ffBholdpol = dffholdpol;
105 code argD ffFJKG sigH clock clock_pol
106 if (nusers(sigH) == 2 &&
107 (mul->type != \SB_MAC16 ||
108 (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
110 subpattern(out_dffe);
112 // F/J/K/G do not have a CE-like (hold) input
116 // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
117 // shared with A and B
118 if ((ffArstmux != NULL) != (dffrstmux != NULL))
120 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
123 if (port(ffArstmux, \S) != port(dffrstmux, \S))
125 if (ffArstpol != dffrstpol)
129 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
131 if (ffBrstpol != dffrstpol)
137 clock_pol = dffclock_pol;
145 code argD ffH sigH sigO clock clock_pol
146 if (ffFJKG && nusers(sigH) == 2 &&
147 (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
149 subpattern(out_dffe);
151 // H does not have a CE-like (hold) input
155 // Reset signal of H (IRSTBOT) shared with B
156 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
159 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
161 if (ffBrstpol != dffrstpol)
167 clock_pol = dffclock_pol;
178 if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
180 select add->type.in($add)
181 choice <IdString> AB {\A, \B}
182 select nusers(port(add, AB)) == 2
184 index <SigBit> port(add, AB)[0] === sigH[0]
185 filter GetSize(port(add, AB)) <= GetSize(sigH)
186 filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
187 filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
192 code sigCD sigO cd_signed
194 sigCD = port(add, addAB == \A ? \B : \A);
195 cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
197 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
198 int actual_mul_width = GetSize(sigH);
199 int actual_acc_width = GetSize(sigCD);
201 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
203 // If accumulator, check adder width and signedness
204 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
207 sigO = port(add, \Y);
212 select mux->type == $mux
213 choice <IdString> AB {\A, \B}
214 select nusers(port(mux, AB)) == 2
215 index <SigSpec> port(mux, AB) === sigO
222 sigO = port(mux, \Y);
225 code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
226 if (mul->type != \SB_MAC16 ||
227 // Ensure that register is not already used
228 ((param(mul, \TOPOUTPUT_SELECT, 0).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT, 0).as_int() != 1) &&
229 // Ensure that OLOADTOP/OLOADBOT is unused or zero
230 (port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
234 // First try entire sigO
235 if (nusers(sigO) == 2) {
237 subpattern(out_dffe);
240 // Otherwise try just its least significant 16 bits
241 if (!dff && GetSize(sigO) > 16) {
242 argD = sigO.extract(0, 16);
243 if (nusers(argD) == 2) {
244 subpattern(out_dffe);
252 clock_pol = dffclock_pol;
254 ffOrstmux = dffrstmux;
255 ffOrstpol = dffrstpol;
258 ffOholdmux = dffholdmux;
259 ffOholdpol = dffholdpol;
262 sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
265 // Loading value into output register is not
266 // supported unless using accumulator
270 sigCD = port(mux, muxAB == \B ? \A : \B);
272 cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
277 code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
278 if (!sigCD.empty() && sigCD != sigO &&
279 (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
284 ffCDholdmux = dffholdmux;
285 ffCDholdpol = dffholdpol;
288 // Reset signal of C (IRSTTOP) and D (IRSTBOT)
289 // shared with A and B
290 if ((ffArstmux != NULL) != (dffrstmux != NULL))
292 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
295 if (port(ffArstmux, \S) != port(dffrstmux, \S))
297 if (ffArstpol != dffrstpol)
301 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
303 if (ffBrstpol != dffrstpol)
309 clock_pol = dffclock_pol;
318 sigCD.extend_u0(32, cd_signed);
325 // #######################
328 arg argD argQ clock clock_pol
332 for (auto c : argQ.chunks()) {
335 if (c.wire->get_bool_attribute(\keep))
341 select ff->type.in($dff)
342 // DSP48E1 does not support clock inversion
343 select param(ff, \CLK_POLARITY).as_bool()
345 slice offset GetSize(port(ff, \D))
346 index <SigBit> port(ff, \Q)[offset] === argQ[0]
348 // Check that the rest of argQ is present
349 filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
350 filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
357 if (clock != SigBit()) {
358 if (port(ff, \CLK) != clock)
360 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
364 SigSpec Q = port(ff, \Q);
366 dffclock = port(ff, \CLK);
367 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
371 dffD.replace(argQ, argD);
372 // Only search for ffrstmux if dffD only
373 // has two (ff, ffrstmux) users
374 if (nusers(dffD) > 2)
380 if false /* TODO: ice40 resets are actually async */
383 select ffrstmux->type.in($mux)
384 index <SigSpec> port(ffrstmux, \Y) === argD
386 choice <IdString> BA {\B, \A}
387 // DSP48E1 only supports reset to zero
388 select port(ffrstmux, BA).is_fully_zero()
390 define <bool> pol (BA == \B)
397 dffrstmux = ffrstmux;
398 dffrstpol = ffrstpol;
399 argD = port(ffrstmux, ffrstpol ? \A : \B);
400 dffD.replace(port(ffrstmux, \Y), argD);
402 // Only search for ffholdmux if argQ has at
403 // least 3 users (ff, <upstream>, ffrstmux) and
404 // dffD only has two (ff, ffrstmux)
405 if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
414 select ffholdmux->type.in($mux)
415 index <SigSpec> port(ffholdmux, \Y) === argD
416 choice <IdString> BA {\B, \A}
417 index <SigSpec> port(ffholdmux, BA) === argQ
418 define <bool> pol (BA == \B)
425 dffholdmux = ffholdmux;
426 dffholdpol = ffholdpol;
427 argD = port(ffholdmux, ffholdpol ? \A : \B);
428 dffD.replace(port(ffholdmux, \Y), argD);
431 dffholdmux = nullptr;
434 // #######################
437 arg argD argQ clock clock_pol
441 for (auto c : argD.chunks())
442 if (c.wire->get_bool_attribute(\keep))
447 select ffholdmux->type.in($mux)
448 // ffholdmux output must have two users: ffholdmux and ff.D
449 select nusers(port(ffholdmux, \Y)) == 2
451 choice <IdString> BA {\B, \A}
452 // keep-last-value net must have at least three users: ffholdmux, ff, downstream sink(s)
453 select nusers(port(ffholdmux, BA)) >= 3
455 slice offset GetSize(port(ffholdmux, \Y))
456 define <IdString> AB (BA == \B ? \A : \B)
457 index <SigBit> port(ffholdmux, AB)[offset] === argD[0]
459 // Check that the rest of argD is present
460 filter GetSize(port(ffholdmux, AB)) >= offset + GetSize(argD)
461 filter port(ffholdmux, AB).extract(offset, GetSize(argD)) == argD
464 define <bool> pol (BA == \B)
471 dffholdmux = ffholdmux;
473 SigSpec AB = port(ffholdmux, ffholdpol ? \A : \B);
474 SigSpec Y = port(ffholdmux, \Y);
477 argQ.replace(AB, port(ffholdmux, ffholdpol ? \B : \A));
479 dffholdmux = ffholdmux;
480 dffholdpol = ffholdpol;
485 if false /* TODO: ice40 resets are actually async */
487 select ffrstmux->type.in($mux)
488 // ffrstmux output must have two users: ffrstmux and ff.D
489 select nusers(port(ffrstmux, \Y)) == 2
491 choice <IdString> BA {\B, \A}
492 // DSP48E1 only supports reset to zero
493 select port(ffrstmux, BA).is_fully_zero()
495 slice offset GetSize(port(ffrstmux, \Y))
496 define <IdString> AB (BA == \B ? \A : \B)
497 index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
499 // Check that offset is consistent
500 filter !ffholdmux || ffoffset == offset
501 // Check that the rest of argD is present
502 filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
503 filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
506 define <bool> pol (AB == \A)
513 dffrstmux = ffrstmux;
515 SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
516 SigSpec Y = port(ffrstmux, \Y);
519 dffrstmux = ffrstmux;
520 dffrstpol = ffrstpol;
525 select ff->type.in($dff)
526 // DSP48E1 does not support clock inversion
527 select param(ff, \CLK_POLARITY).as_bool()
529 slice offset GetSize(port(ff, \D))
530 index <SigBit> port(ff, \D)[offset] === argD[0]
532 // Check that offset is consistent
533 filter (!ffholdmux && !ffrstmux) || ffoffset == offset
534 // Check that the rest of argD is present
535 filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
536 filter port(ff, \D).extract(offset, GetSize(argD)) == argD
537 // Check that FF.Q is connected to CE-mux
538 filter !ffholdmux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
545 if (clock != SigBit()) {
546 if (port(ff, \CLK) != clock)
548 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
551 SigSpec D = port(ff, \D);
552 SigSpec Q = port(ff, \Q);
558 for (auto c : argQ.chunks()) {
559 Const init = c.wire->attributes.at(\init, State::Sx);
560 if (!init.is_fully_undef() && !init.is_fully_zero())
566 dffclock = port(ff, \CLK);
567 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
569 // No enable/reset mux possible without flop
570 else if (dffholdmux || dffrstmux)