4 state <bool> clock_pol cd_signed o_lo
5 state <SigSpec> sigA sigB sigCD sigH sigO
7 state <IdString> addAB muxAB
9 state <Cell*> ffA ffB ffCD
10 state <Cell*> ffFJKG ffH ffO
14 state <SigSpec> argQ argD
15 udata <SigSpec> dffD dffQ
16 udata <SigBit> dffclock
18 udata <bool> dffclock_pol
21 select mul->type.in($mul, \SB_MAC16)
22 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
26 auto unextend = [](const SigSpec &sig) {
28 for (i = GetSize(sig)-1; i > 0; i--)
29 if (sig[i] != sig[i-1])
31 // Do not remove non-const sign bit
34 return sig.extract(0, i);
36 sigA = unextend(port(mul, \A));
37 sigB = unextend(port(mul, \B));
40 if (mul->type == $mul)
42 else if (mul->type == \SB_MAC16)
48 // Only care about those bits that are used
50 for (i = 0; i < GetSize(O); i++) {
51 if (nusers(O[i]) <= 1)
55 // This sigM could have no users if downstream sinks (e.g. $add) is
56 // narrower than $mul result, for example
60 log_assert(nusers(O.extract_end(i)) <= 1);
63 code argQ ffA sigA clock clock_pol
64 if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
70 clock_pol = dffclock_pol;
76 code argQ ffB sigB clock clock_pol
77 if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
83 clock_pol = dffclock_pol;
89 code argD argSdff ffFJKG sigH clock clock_pol
90 if (nusers(sigH) == 2 &&
91 (mul->type != \SB_MAC16 ||
92 (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
97 // F/J/K/G do not have a CE-like (hold) input
98 if (dff->hasPort(\EN))
101 // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
102 // shared with A and B
104 if (ffA->hasPort(\ARST) != dff->hasPort(\ARST))
106 if (ffA->hasPort(\ARST)) {
107 if (port(ffA, \ARST) != port(dff, \ARST))
109 if (param(ffA, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
114 if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
116 if (ffB->hasPort(\ARST)) {
117 if (port(ffB, \ARST) != port(dff, \ARST))
119 if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
126 clock_pol = dffclock_pol;
134 code argD argSdff ffH sigH sigO clock clock_pol
135 if (ffFJKG && nusers(sigH) == 2 &&
136 (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
139 subpattern(out_dffe);
141 // H does not have a CE-like (hold) input
142 if (dff->hasPort(\EN))
145 // Reset signal of H (IRSTBOT) shared with B
146 if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
148 if (ffB->hasPort(\ARST)) {
149 if (port(ffB, \ARST) != port(dff, \ARST))
151 if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
157 clock_pol = dffclock_pol;
168 if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
170 select add->type.in($add)
171 choice <IdString> AB {\A, \B}
172 select nusers(port(add, AB)) == 2
174 index <SigBit> port(add, AB)[0] === sigH[0]
175 filter GetSize(port(add, AB)) <= GetSize(sigH)
176 filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
177 filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
182 code sigCD sigO cd_signed
184 sigCD = port(add, addAB == \A ? \B : \A);
185 cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
187 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
188 int actual_mul_width = GetSize(sigH);
189 int actual_acc_width = GetSize(sigCD);
191 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
193 // If accumulator, check adder width and signedness
194 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
197 sigO = port(add, \Y);
202 select mux->type == $mux
203 choice <IdString> AB {\A, \B}
204 select nusers(port(mux, AB)) == 2
205 index <SigSpec> port(mux, AB) === sigO
212 sigO = port(mux, \Y);
215 code argD argSdff ffO sigO sigCD clock clock_pol cd_signed o_lo
216 if (mul->type != \SB_MAC16 ||
217 // Ensure that register is not already used
218 ((param(mul, \TOPOUTPUT_SELECT).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT).as_int() != 1) &&
219 // Ensure that OLOADTOP/OLOADBOT is unused or zero
220 (port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
224 // First try entire sigO
225 if (nusers(sigO) == 2) {
228 subpattern(out_dffe);
231 // Otherwise try just its least significant 16 bits
232 if (!dff && GetSize(sigO) > 16) {
233 argD = sigO.extract(0, 16);
234 if (nusers(argD) == 2) {
236 subpattern(out_dffe);
244 clock_pol = dffclock_pol;
246 sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
249 // Loading value into output register is not
250 // supported unless using accumulator
254 sigCD = port(mux, muxAB == \B ? \A : \B);
256 cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
257 } else if (dff && dff->hasPort(\SRST)) {
260 sigCD = param(dff, \SRST_VALUE);
262 cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
267 code argQ ffCD sigCD clock clock_pol
268 if (!sigCD.empty() && sigCD != sigO &&
269 (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
273 // Reset signal of C (IRSTTOP) and D (IRSTBOT)
274 // shared with A and B
276 if (ffA->hasPort(\ARST) != dff->hasPort(\ARST))
278 if (ffA->hasPort(\ARST)) {
279 if (port(ffA, \ARST) != port(dff, \ARST))
281 if (param(ffA, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
286 if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
288 if (ffB->hasPort(\ARST)) {
289 if (port(ffB, \ARST) != port(dff, \ARST))
291 if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
298 clock_pol = dffclock_pol;
307 sigCD.extend_u0(32, cd_signed);
314 // #######################
317 arg argD argQ clock clock_pol
323 for (auto c : argQ.chunks()) {
326 if (c.wire->get_bool_attribute(\keep))
328 Const init = c.wire->attributes.at(\init, State::Sx);
329 if (!init.is_fully_undef() && !init.is_fully_zero())
335 select ff->type.in($dff, $dffe)
336 // DSP48E1 does not support clock inversion
337 select param(ff, \CLK_POLARITY).as_bool()
339 slice offset GetSize(port(ff, \D))
340 index <SigBit> port(ff, \Q)[offset] === argQ[0]
342 // Check that the rest of argQ is present
343 filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
344 filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
349 if (clock != SigBit()) {
350 if (port(ff, \CLK) != clock)
352 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
356 SigSpec Q = port(ff, \Q);
358 dffclock = port(ff, \CLK);
359 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
363 dffD.replace(argQ, argD);
367 // #######################
370 arg argD argSdff argQ clock clock_pol
374 for (auto c : argD.chunks())
375 if (c.wire->get_bool_attribute(\keep))
380 select ff->type.in($dff, $dffe, $sdff, $sdffce)
381 // SB_MAC16 does not support clock inversion
382 select param(ff, \CLK_POLARITY).as_bool()
384 slice offset GetSize(port(ff, \D))
385 index <SigBit> port(ff, \D)[offset] === argD[0]
387 // Only allow sync reset if requested.
388 filter argSdff || ff->type.in($dff, $dffe)
389 // Check that the rest of argD is present
390 filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
391 filter port(ff, \D).extract(offset, GetSize(argD)) == argD
396 if (clock != SigBit()) {
397 if (port(ff, \CLK) != clock)
399 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
402 SigSpec D = port(ff, \D);
403 SigSpec Q = port(ff, \Q);
407 for (auto c : argQ.chunks()) {
408 Const init = c.wire->attributes.at(\init, State::Sx);
409 if (!init.is_fully_undef() && !init.is_fully_zero())
415 dffclock = port(ff, \CLK);
416 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();