passes/pmgen/ice40_dsp.pmg

   1 pattern ice40_dsp
   2
   3 state <SigBit> clock
   4 state <bool> clock_pol cd_signed o_lo
   5 state <SigSpec> sigA sigB sigCD sigH sigO
   6 state <Cell*> add mux
   7 state <IdString> addAB muxAB
   8
   9 state <bool> ffAholdpol ffBholdpol ffCDholdpol ffOholdpol
  10 state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
  11
  12 state <Cell*> ffA ffAholdmux ffArstmux ffB ffBholdmux ffBrstmux ffCD ffCDholdmux
  13 state <Cell*> ffFJKG ffH ffO ffOholdmux ffOrstmux
  14
  15 // subpattern
  16 state <SigSpec> argQ argD
  17 state <bool> ffholdpol ffrstpol
  18 state <int> ffoffset
  19 udata <SigSpec> dffD dffQ
  20 udata <SigBit> dffclock
  21 udata <Cell*> dff dffholdmux dffrstmux
  22 udata <bool> dffholdpol dffrstpol dffclock_pol
  23
  24 match mul
  25         select mul->type.in($mul, \SB_MAC16)
  26         select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
  27 endmatch
  28
  29 code sigA sigB sigH
  30         auto unextend = [](const SigSpec &sig) {
  31                 int i;
  32                 for (i = GetSize(sig)-1; i > 0; i--)
  33                         if (sig[i] != sig[i-1])
  34                                 break;
  35                 // Do not remove non-const sign bit
  36                 if (sig[i].wire)
  37                         ++i;
  38                 return sig.extract(0, i);
  39         };
  40         sigA = unextend(port(mul, \A));
  41         sigB = unextend(port(mul, \B));
  42
  43         SigSpec O;
  44         if (mul->type == $mul)
  45                 O = mul->getPort(\Y);
  46         else if (mul->type == \SB_MAC16)
  47                 O = mul->getPort(\O);
  48         else log_abort();
  49         if (GetSize(O) <= 10)
  50                 reject;
  51
  52         // Only care about those bits that are used
  53         int i;
  54         for (i = 0; i < GetSize(O); i++) {
  55                 if (nusers(O[i]) <= 1)
  56                         break;
  57                 sigH.append(O[i]);
  58         }
  59         log_assert(nusers(O.extract_end(i)) <= 1);
  60 endcode
  61
  62 code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
  63         if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
  64                 argQ = sigA;
  65                 subpattern(in_dffe);
  66                 if (dff) {
  67                         ffA = dff;
  68                         clock = dffclock;
  69                         clock_pol = dffclock_pol;
  70                         if (dffrstmux) {
  71                                 ffArstmux = dffrstmux;
  72                                 ffArstpol = dffrstpol;
  73                         }
  74                         if (dffholdmux) {
  75                                 ffAholdmux = dffholdmux;
  76                                 ffAholdpol = dffholdpol;
  77                         }
  78                         sigA = dffD;
  79                 }
  80         }
  81 endcode
  82
  83 code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
  84         if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
  85                 argQ = sigB;
  86                 subpattern(in_dffe);
  87                 if (dff) {
  88                         ffB = dff;
  89                         clock = dffclock;
  90                         clock_pol = dffclock_pol;
  91                         if (dffrstmux) {
  92                                 ffBrstmux = dffrstmux;
  93                                 ffBrstpol = dffrstpol;
  94                         }
  95                         if (dffholdmux) {
  96                                 ffBholdmux = dffholdmux;
  97                                 ffBholdpol = dffholdpol;
  98                         }
  99                         sigB = dffD;
 100                 }
 101         }
 102 endcode
 103
 104 code argD ffFJKG sigH clock clock_pol
 105         if (nusers(sigH) == 2 &&
 106                         (mul->type != \SB_MAC16 ||
 107                          (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
 108                 argD = sigH;
 109                 subpattern(out_dffe);
 110                 if (dff) {
 111                         // F/J/K/G do not have a CE-like (hold) input
 112                         if (dffholdmux)
 113                                 goto reject_ffFJKG;
 114
 115                         // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
 116                         //   shared with A and B
 117                         if ((ffArstmux != NULL) != (dffrstmux != NULL))
 118                                 goto reject_ffFJKG;
 119                         if ((ffBrstmux != NULL) != (dffrstmux != NULL))
 120                                 goto reject_ffFJKG;
 121                         if (ffArstmux) {
 122                                 if (port(ffArstmux, \S) != port(dffrstmux, \S))
 123                                         goto reject_ffFJKG;
 124                                 if (ffArstpol != dffrstpol)
 125                                         goto reject_ffFJKG;
 126                         }
 127                         if (ffBrstmux) {
 128                                 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
 129                                         goto reject_ffFJKG;
 130                                 if (ffBrstpol != dffrstpol)
 131                                         goto reject_ffFJKG;
 132                         }
 133
 134                         ffFJKG = dff;
 135                         clock = dffclock;
 136                         clock_pol = dffclock_pol;
 137                         sigH = dffQ;
 138
 139 reject_ffFJKG:          ;
 140                 }
 141         }
 142 endcode
 143
 144 code argD ffH sigH sigO clock clock_pol
 145         if (ffFJKG && nusers(sigH) == 2 &&
 146                         (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
 147                 argD = sigH;
 148                 subpattern(out_dffe);
 149                 if (dff) {
 150                         // H does not have a CE-like (hold) input
 151                         if (dffholdmux)
 152                                 goto reject_ffH;
 153
 154                         // Reset signal of H (IRSTBOT) shared with B
 155                         if ((ffBrstmux != NULL) != (dffrstmux != NULL))
 156                                 goto reject_ffH;
 157                         if (ffBrstmux) {
 158                                 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
 159                                         goto reject_ffH;
 160                                 if (ffBrstpol != dffrstpol)
 161                                         goto reject_ffH;
 162                         }
 163
 164                         ffH = dff;
 165                         clock = dffclock;
 166                         clock_pol = dffclock_pol;
 167                         sigH = dffQ;
 168
 169 reject_ffH:             ;
 170                 }
 171         }
 172
 173         sigO = sigH;
 174 endcode
 175
 176 match add
 177         if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
 178
 179         select add->type.in($add)
 180         choice <IdString> AB {\A, \B}
 181         select nusers(port(add, AB)) == 2
 182
 183         index <SigBit> port(add, AB)[0] === sigH[0]
 184         filter GetSize(port(add, AB)) <= GetSize(sigH)
 185         filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
 186         filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
 187         set addAB AB
 188         optional
 189 endmatch
 190
 191 code sigCD sigO cd_signed
 192         if (add) {
 193                 sigCD = port(add, addAB == \A ? \B : \A);
 194                 cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
 195
 196                 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
 197                 int actual_mul_width = GetSize(sigH);
 198                 int actual_acc_width = GetSize(sigCD);
 199
 200                 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
 201                         reject;
 202                 // If accumulator, check adder width and signedness
 203                 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
 204                         reject;
 205
 206                 sigO = port(add, \Y);
 207         }
 208 endcode
 209
 210 match mux
 211         select mux->type == $mux
 212         choice <IdString> AB {\A, \B}
 213         select nusers(port(mux, AB)) == 2
 214         index <SigSpec> port(mux, AB) === sigO
 215         set muxAB AB
 216         optional
 217 endmatch
 218
 219 code sigO
 220         if (mux)
 221                 sigO = port(mux, \Y);
 222 endcode
 223
 224 code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
 225         if (mul->type != \SB_MAC16 ||
 226                         // Ensure that register is not already used
 227                         ((param(mul, \TOPOUTPUT_SELECT, 0).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT, 0).as_int() != 1) &&
 228                          // Ensure that OLOADTOP/OLOADBOT is unused or zero
 229                          (port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
 230
 231                 dff = nullptr;
 232
 233                 // First try entire sigO
 234                 if (nusers(sigO) == 2) {
 235                         argD = sigO;
 236                         subpattern(out_dffe);
 237                 }
 238
 239                 // Otherwise try just its least significant 16 bits
 240                 if (!dff && GetSize(sigO) > 16) {
 241                         argD = sigO.extract(0, 16);
 242                         if (nusers(argD) == 2) {
 243                                 subpattern(out_dffe);
 244                                 o_lo = dff;
 245                         }
 246                 }
 247
 248                 if (dff) {
 249                         ffO = dff;
 250                         clock = dffclock;
 251                         clock_pol = dffclock_pol;
 252                         if (dffrstmux) {
 253                                 ffOrstmux = dffrstmux;
 254                                 ffOrstpol = dffrstpol;
 255                         }
 256                         if (dffholdmux) {
 257                                 ffOholdmux = dffholdmux;
 258                                 ffOholdpol = dffholdpol;
 259                         }
 260
 261                         sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
 262                 }
 263
 264                 // Loading value into output register is not
 265                 //   supported unless using accumulator
 266                 if (mux) {
 267                         if (sigCD != sigO)
 268                                 reject;
 269                         sigCD = port(mux, muxAB == \B ? \A : \B);
 270
 271                         cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
 272                 }
 273         }
 274 endcode
 275
 276 code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
 277         if (!sigCD.empty() && sigCD != sigO &&
 278                         (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
 279                 argQ = sigCD;
 280                 subpattern(in_dffe);
 281                 if (dff) {
 282                         if (dffholdmux) {
 283                                 ffCDholdmux = dffholdmux;
 284                                 ffCDholdpol = dffholdpol;
 285                         }
 286
 287                         // Reset signal of C (IRSTTOP) and D (IRSTBOT)
 288                         //   shared with A and B
 289                         if ((ffArstmux != NULL) != (dffrstmux != NULL))
 290                                 goto reject_ffCD;
 291                         if ((ffBrstmux != NULL) != (dffrstmux != NULL))
 292                                 goto reject_ffCD;
 293                         if (ffArstmux) {
 294                                 if (port(ffArstmux, \S) != port(dffrstmux, \S))
 295                                         goto reject_ffCD;
 296                                 if (ffArstpol != dffrstpol)
 297                                         goto reject_ffCD;
 298                         }
 299                         if (ffBrstmux) {
 300                                 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
 301                                         goto reject_ffCD;
 302                                 if (ffBrstpol != dffrstpol)
 303                                         goto reject_ffCD;
 304                         }
 305
 306                         ffCD = dff;
 307                         clock = dffclock;
 308                         clock_pol = dffclock_pol;
 309                         sigCD = dffD;
 310
 311 reject_ffCD:            ;
 312                 }
 313         }
 314 endcode
 315
 316 code sigCD
 317         sigCD.extend_u0(32, cd_signed);
 318 endcode
 319
 320 code
 321         accept;
 322 endcode
 323
 324 // #######################
 325
 326 subpattern in_dffe
 327 arg argD argQ clock clock_pol
 328
 329 code
 330         dff = nullptr;
 331         for (auto c : argQ.chunks()) {
 332                 if (!c.wire)
 333                         reject;
 334                 if (c.wire->get_bool_attribute(\keep))
 335                         reject;
 336                 Const init = c.wire->attributes.at(\init, State::Sx);
 337                 if (!init.is_fully_undef() && !init.is_fully_zero())
 338                         reject;
 339         }
 340 endcode
 341
 342 match ff
 343         select ff->type.in($dff)
 344         // DSP48E1 does not support clock inversion
 345         select param(ff, \CLK_POLARITY).as_bool()
 346
 347         slice offset GetSize(port(ff, \D))
 348         index <SigBit> port(ff, \Q)[offset] === argQ[0]
 349
 350         // Check that the rest of argQ is present
 351         filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 352         filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 353
 354         set ffoffset offset
 355 endmatch
 356
 357 code argQ argD
 358 {
 359         if (clock != SigBit()) {
 360                 if (port(ff, \CLK) != clock)
 361                         reject;
 362                 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
 363                         reject;
 364         }
 365
 366         SigSpec Q = port(ff, \Q);
 367         dff = ff;
 368         dffclock = port(ff, \CLK);
 369         dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
 370         dffD = argQ;
 371         argD = port(ff, \D);
 372         argQ = Q;
 373         dffD.replace(argQ, argD);
 374         // Only search for ffrstmux if dffD only
 375         //   has two (ff, ffrstmux) users
 376         if (nusers(dffD) > 2)
 377                 argD = SigSpec();
 378 }
 379 endcode
 380
 381 match ffrstmux
 382         if false /* TODO: ice40 resets are actually async */
 383
 384         if !argD.empty()
 385         select ffrstmux->type.in($mux)
 386         index <SigSpec> port(ffrstmux, \Y) === argD
 387
 388         choice <IdString> BA {\B, \A}
 389         // DSP48E1 only supports reset to zero
 390         select port(ffrstmux, BA).is_fully_zero()
 391
 392         define <bool> pol (BA == \B)
 393         set ffrstpol pol
 394         semioptional
 395 endmatch
 396
 397 code argD
 398         if (ffrstmux) {
 399                 dffrstmux = ffrstmux;
 400                 dffrstpol = ffrstpol;
 401                 argD = port(ffrstmux, ffrstpol ? \A : \B);
 402                 dffD.replace(port(ffrstmux, \Y), argD);
 403
 404                 // Only search for ffholdmux if argQ has at
 405                 //   least 3 users (ff, <upstream>, ffrstmux) and
 406                 //   dffD only has two (ff, ffrstmux)
 407                 if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
 408                         argD = SigSpec();
 409         }
 410         else
 411                 dffrstmux = nullptr;
 412 endcode
 413
 414 match ffholdmux
 415         if !argD.empty()
 416         select ffholdmux->type.in($mux)
 417         index <SigSpec> port(ffholdmux, \Y) === argD
 418         choice <IdString> BA {\B, \A}
 419         index <SigSpec> port(ffholdmux, BA) === argQ
 420         define <bool> pol (BA == \B)
 421         set ffholdpol pol
 422         semioptional
 423 endmatch
 424
 425 code argD
 426         if (ffholdmux) {
 427                 dffholdmux = ffholdmux;
 428                 dffholdpol = ffholdpol;
 429                 argD = port(ffholdmux, ffholdpol ? \A : \B);
 430                 dffD.replace(port(ffholdmux, \Y), argD);
 431         }
 432         else
 433                 dffholdmux = nullptr;
 434 endcode
 435
 436 // #######################
 437
 438 subpattern out_dffe
 439 arg argD argQ clock clock_pol
 440
 441 code
 442         dff = nullptr;
 443         for (auto c : argD.chunks())
 444                 if (c.wire->get_bool_attribute(\keep))
 445                         reject;
 446 endcode
 447
 448 match ffholdmux
 449         select ffholdmux->type.in($mux)
 450         // ffholdmux output must have two users: ffholdmux and ff.D
 451         select nusers(port(ffholdmux, \Y)) == 2
 452
 453         choice <IdString> BA {\B, \A}
 454         // keep-last-value net must have at least three users: ffholdmux, ff, downstream sink(s)
 455         select nusers(port(ffholdmux, BA)) >= 3
 456
 457         slice offset GetSize(port(ffholdmux, \Y))
 458         define <IdString> AB (BA == \B ? \A : \B)
 459         index <SigBit> port(ffholdmux, AB)[offset] === argD[0]
 460
 461         // Check that the rest of argD is present
 462         filter GetSize(port(ffholdmux, AB)) >= offset + GetSize(argD)
 463         filter port(ffholdmux, AB).extract(offset, GetSize(argD)) == argD
 464
 465         set ffoffset offset
 466         define <bool> pol (BA == \B)
 467         set ffholdpol pol
 468
 469         semioptional
 470 endmatch
 471
 472 code argD argQ
 473         dffholdmux = ffholdmux;
 474         if (ffholdmux) {
 475                 SigSpec AB = port(ffholdmux, ffholdpol ? \A : \B);
 476                 SigSpec Y = port(ffholdmux, \Y);
 477                 argQ = argD;
 478                 argD.replace(AB, Y);
 479                 argQ.replace(AB, port(ffholdmux, ffholdpol ? \B : \A));
 480
 481                 dffholdmux = ffholdmux;
 482                 dffholdpol = ffholdpol;
 483         }
 484 endcode
 485
 486 match ffrstmux
 487         if false /* TODO: ice40 resets are actually async */
 488
 489         select ffrstmux->type.in($mux)
 490         // ffrstmux output must have two users: ffrstmux and ff.D
 491         select nusers(port(ffrstmux, \Y)) == 2
 492
 493         choice <IdString> BA {\B, \A}
 494         // DSP48E1 only supports reset to zero
 495         select port(ffrstmux, BA).is_fully_zero()
 496
 497         slice offset GetSize(port(ffrstmux, \Y))
 498         define <IdString> AB (BA == \B ? \A : \B)
 499         index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
 500
 501         // Check that offset is consistent
 502         filter !ffholdmux || ffoffset == offset
 503         // Check that the rest of argD is present
 504         filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
 505         filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
 506
 507         set ffoffset offset
 508         define <bool> pol (AB == \A)
 509         set ffrstpol pol
 510
 511         semioptional
 512 endmatch
 513
 514 code argD argQ
 515         dffrstmux = ffrstmux;
 516         if (ffrstmux) {
 517                 SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
 518                 SigSpec Y = port(ffrstmux, \Y);
 519                 argD.replace(AB, Y);
 520
 521                 dffrstmux = ffrstmux;
 522                 dffrstpol = ffrstpol;
 523         }
 524 endcode
 525
 526 match ff
 527         select ff->type.in($dff)
 528         // DSP48E1 does not support clock inversion
 529         select param(ff, \CLK_POLARITY).as_bool()
 530
 531         slice offset GetSize(port(ff, \D))
 532         index <SigBit> port(ff, \D)[offset] === argD[0]
 533
 534         // Check that offset is consistent
 535         filter (!ffholdmux && !ffrstmux) || ffoffset == offset
 536         // Check that the rest of argD is present
 537         filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
 538         filter port(ff, \D).extract(offset, GetSize(argD)) == argD
 539         // Check that FF.Q is connected to CE-mux
 540         filter !ffholdmux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 541
 542         set ffoffset offset
 543 endmatch
 544
 545 code argQ
 546         if (ff) {
 547                 if (clock != SigBit()) {
 548                         if (port(ff, \CLK) != clock)
 549                                 reject;
 550                         if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
 551                                 reject;
 552                 }
 553                 SigSpec D = port(ff, \D);
 554                 SigSpec Q = port(ff, \Q);
 555                 if (!ffholdmux) {
 556                         argQ = argD;
 557                         argQ.replace(D, Q);
 558                 }
 559
 560                 for (auto c : argQ.chunks()) {
 561                         Const init = c.wire->attributes.at(\init, State::Sx);
 562                         if (!init.is_fully_undef() && !init.is_fully_zero())
 563                                 reject;
 564                 }
 565
 566                 dff = ff;
 567                 dffQ = argQ;
 568                 dffclock = port(ff, \CLK);
 569                 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
 570         }
 571         // No enable/reset mux possible without flop
 572         else if (dffholdmux || dffrstmux)
 573                 reject;
 574 endcode