4 state <bool> clock_pol cd_signed o_lo
5 state <SigSpec> sigA sigB sigCD sigH sigO
7 state <IdString> addAB muxAB
9 state <Cell*> ffA ffB ffCD
10 state <Cell*> ffFJKG ffH ffO
14 state <SigSpec> argQ argD
15 udata <SigSpec> dffD dffQ
16 udata <SigBit> dffclock
18 udata <bool> dffclock_pol
21 select mul->type.in($mul, \SB_MAC16)
22 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
26 auto unextend = [](const SigSpec &sig) {
28 for (i = GetSize(sig)-1; i > 0; i--)
29 if (sig[i] != sig[i-1])
31 // Do not remove non-const sign bit
33 return sig.extract(0, i);
35 sigA = unextend(port(mul, \A));
36 sigB = unextend(port(mul, \B));
39 if (mul->type == $mul)
41 else if (mul->type == \SB_MAC16)
47 // Only care about those bits that are used
49 for (i = 0; i < GetSize(O); i++) {
50 if (nusers(O[i]) <= 1)
54 // This sigM could have no users if downstream sinks (e.g. $add) is
55 // narrower than $mul result, for example
59 log_assert(nusers(O.extract_end(i)) <= 1);
62 code argQ ffA sigA clock clock_pol
63 if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
69 clock_pol = dffclock_pol;
75 code argQ ffB sigB clock clock_pol
76 if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
82 clock_pol = dffclock_pol;
88 code argD argSdff ffFJKG sigH clock clock_pol
89 if (nusers(sigH) == 2 &&
90 (mul->type != \SB_MAC16 ||
91 (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
96 // F/J/K/G do not have a CE-like (hold) input
97 if (dff->hasPort(\EN))
100 // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
101 // shared with A and B
103 if (ffA->hasPort(\ARST) != dff->hasPort(\ARST))
105 if (ffA->hasPort(\ARST)) {
106 if (port(ffA, \ARST) != port(dff, \ARST))
108 if (param(ffA, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
113 if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
115 if (ffB->hasPort(\ARST)) {
116 if (port(ffB, \ARST) != port(dff, \ARST))
118 if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
125 clock_pol = dffclock_pol;
133 code argD argSdff ffH sigH sigO clock clock_pol
134 if (ffFJKG && nusers(sigH) == 2 &&
135 (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
138 subpattern(out_dffe);
140 // H does not have a CE-like (hold) input
141 if (dff->hasPort(\EN))
144 // Reset signal of H (IRSTBOT) shared with B
145 if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
147 if (ffB->hasPort(\ARST)) {
148 if (port(ffB, \ARST) != port(dff, \ARST))
150 if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
156 clock_pol = dffclock_pol;
167 if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
169 select add->type.in($add)
170 choice <IdString> AB {\A, \B}
171 select nusers(port(add, AB)) == 2
173 index <SigBit> port(add, AB)[0] === sigH[0]
174 filter GetSize(port(add, AB)) <= GetSize(sigH)
175 filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
176 filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
181 code sigCD sigO cd_signed
183 sigCD = port(add, addAB == \A ? \B : \A);
184 cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
186 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
187 int actual_mul_width = GetSize(sigH);
188 int actual_acc_width = GetSize(sigCD);
190 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
192 // If accumulator, check adder width and signedness
193 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
196 sigO = port(add, \Y);
201 select mux->type == $mux
202 choice <IdString> AB {\A, \B}
203 select nusers(port(mux, AB)) == 2
204 index <SigSpec> port(mux, AB) === sigO
211 sigO = port(mux, \Y);
214 code argD argSdff ffO sigO sigCD clock clock_pol cd_signed o_lo
215 if (mul->type != \SB_MAC16 ||
216 // Ensure that register is not already used
217 ((param(mul, \TOPOUTPUT_SELECT).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT).as_int() != 1) &&
218 // Ensure that OLOADTOP/OLOADBOT is unused or zero
219 (port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
223 // First try entire sigO
224 if (nusers(sigO) == 2) {
227 subpattern(out_dffe);
230 // Otherwise try just its least significant 16 bits
231 if (!dff && GetSize(sigO) > 16) {
232 argD = sigO.extract(0, 16);
233 if (nusers(argD) == 2) {
235 subpattern(out_dffe);
243 clock_pol = dffclock_pol;
245 sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
248 // Loading value into output register is not
249 // supported unless using accumulator
253 sigCD = port(mux, muxAB == \B ? \A : \B);
255 cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
256 } else if (dff && dff->hasPort(\SRST)) {
259 sigCD = param(dff, \SRST_VALUE);
261 cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
266 code argQ ffCD sigCD clock clock_pol
267 if (!sigCD.empty() && sigCD != sigO &&
268 (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
272 // Reset signal of C (IRSTTOP) and D (IRSTBOT)
273 // shared with A and B
275 if (ffA->hasPort(\ARST) != dff->hasPort(\ARST))
277 if (ffA->hasPort(\ARST)) {
278 if (port(ffA, \ARST) != port(dff, \ARST))
280 if (param(ffA, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
285 if (ffB->hasPort(\ARST) != dff->hasPort(\ARST))
287 if (ffB->hasPort(\ARST)) {
288 if (port(ffB, \ARST) != port(dff, \ARST))
290 if (param(ffB, \ARST_POLARITY) != param(dff, \ARST_POLARITY))
297 clock_pol = dffclock_pol;
306 sigCD.extend_u0(32, cd_signed);
313 // #######################
316 arg argD argQ clock clock_pol
322 for (auto c : argQ.chunks()) {
325 if (c.wire->get_bool_attribute(\keep))
327 Const init = c.wire->attributes.at(\init, State::Sx);
328 if (!init.is_fully_undef() && !init.is_fully_zero())
334 select ff->type.in($dff, $dffe)
335 // DSP48E1 does not support clock inversion
336 select param(ff, \CLK_POLARITY).as_bool()
338 slice offset GetSize(port(ff, \D))
339 index <SigBit> port(ff, \Q)[offset] === argQ[0]
341 // Check that the rest of argQ is present
342 filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
343 filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
348 if (clock != SigBit()) {
349 if (port(ff, \CLK) != clock)
351 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
355 SigSpec Q = port(ff, \Q);
357 dffclock = port(ff, \CLK);
358 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
362 dffD.replace(argQ, argD);
366 // #######################
369 arg argD argSdff argQ clock clock_pol
373 for (auto c : argD.chunks())
374 if (c.wire->get_bool_attribute(\keep))
379 select ff->type.in($dff, $dffe, $sdff, $sdffce)
380 // SB_MAC16 does not support clock inversion
381 select param(ff, \CLK_POLARITY).as_bool()
383 slice offset GetSize(port(ff, \D))
384 index <SigBit> port(ff, \D)[offset] === argD[0]
386 // Only allow sync reset if requested.
387 filter argSdff || ff->type.in($dff, $dffe)
388 // Check that the rest of argD is present
389 filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
390 filter port(ff, \D).extract(offset, GetSize(argD)) == argD
395 if (clock != SigBit()) {
396 if (port(ff, \CLK) != clock)
398 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
401 SigSpec D = port(ff, \D);
402 SigSpec Q = port(ff, \Q);
406 for (auto c : argQ.chunks()) {
407 Const init = c.wire->attributes.at(\init, State::Sx);
408 if (!init.is_fully_undef() && !init.is_fully_zero())
414 dffclock = port(ff, \CLK);
415 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();