Merge remote-tracking branch 'origin/master' into xc7dsp
[yosys.git] / passes / pmgen / ice40_dsp.pmg
1 pattern ice40_dsp
2
3 state <SigBit> clock
4 state <bool> clock_pol
5 state <SigSpec> sigA sigB sigCD sigH sigO
6 state <Cell*> addAB muxAB
7
8 match mul
9 select mul->type.in($mul, $__MUL16X16)
10 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
11 select GetSize(mul->getPort(\Y)) > 10
12 endmatch
13
14 match ffA
15 // TODO: Support $dffe too by checking if all enable signals are identical
16 select ffA->type.in($dff)
17 filter !port(mul, \A).remove_const().empty()
18 filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
19 optional
20 endmatch
21
22 code sigA clock clock_pol
23 sigA = port(mul, \A);
24
25 if (ffA) {
26 for (auto b : port(ffA, \Q))
27 if (b.wire->get_bool_attribute(\keep))
28 reject;
29
30 clock = port(ffA, \CLK).as_bit();
31 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
32
33 sigA.replace(port(ffA, \Q), port(ffA, \D));
34 }
35 endcode
36
37 match ffB
38 select ffB->type.in($dff)
39 filter !port(mul, \B).remove_const().empty()
40 filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
41 optional
42 endmatch
43
44 code sigB clock clock_pol
45 sigB = port(mul, \B);
46
47 if (ffB) {
48 for (auto b : port(ffB, \Q))
49 if (b.wire->get_bool_attribute(\keep))
50 reject;
51
52 SigBit c = port(ffB, \CLK).as_bit();
53 bool cp = param(ffB, \CLK_POLARITY).as_bool();
54
55 if (clock != SigBit() && (c != clock || cp != clock_pol))
56 reject;
57
58 clock = c;
59 clock_pol = cp;
60
61 sigB.replace(port(ffB, \Q), port(ffB, \D));
62 }
63 endcode
64
65 match ffH
66 select ffH->type.in($dff)
67 select nusers(port(ffH, \D)) == 2
68 index <SigSpec> port(ffH, \D) === port(mul, \Y)
69 optional
70 endmatch
71
72 code sigH sigO clock clock_pol
73 sigH = port(mul, \Y);
74 sigO = sigH;
75
76 if (ffH) {
77 sigH = port(ffH, \Q);
78 for (auto b : sigH)
79 if (b.wire->get_bool_attribute(\keep))
80 reject;
81
82 sigO = sigH;
83
84 SigBit c = port(ffH, \CLK).as_bit();
85 bool cp = param(ffH, \CLK_POLARITY).as_bool();
86
87 if (clock != SigBit() && (c != clock || cp != clock_pol))
88 reject;
89
90 clock = c;
91 clock_pol = cp;
92 }
93 endcode
94
95 match addA
96 select addA->type.in($add)
97 select nusers(port(addA, \A)) == 2
98 index <SigSpec> port(addA, \A) === sigH
99 optional
100 endmatch
101
102 match addB
103 if !addA
104 select addB->type.in($add, $sub)
105 select nusers(port(addB, \B)) == 2
106 index <SigSpec> port(addB, \B) === sigH
107 optional
108 endmatch
109
110 code addAB sigCD sigO
111 if (addA) {
112 addAB = addA;
113 sigCD = port(addAB, \B);
114 sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool());
115 }
116 if (addB) {
117 addAB = addB;
118 sigCD = port(addAB, \A);
119 sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
120 }
121 if (addAB) {
122 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
123 int actual_mul_width = GetSize(sigH);
124 int actual_acc_width = GetSize(sigO);
125
126 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
127 reject;
128 if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \B_SIGNED).as_bool()))
129 reject;
130
131 sigO = port(addAB, \Y);
132 }
133 endcode
134
135 match muxA
136 select muxA->type.in($mux)
137 select nusers(port(muxA, \A)) == 2
138 index <SigSpec> port(muxA, \A) === sigO
139 optional
140 endmatch
141
142 match muxB
143 if !muxA
144 select muxB->type.in($mux)
145 select nusers(port(muxB, \B)) == 2
146 index <SigSpec> port(muxB, \B) === sigO
147 optional
148 endmatch
149
150 code muxAB
151 if (muxA)
152 muxAB = muxA;
153 else if (muxB)
154 muxAB = muxB;
155 endcode
156
157 match ffO_lo
158 select ffO_lo->type.in($dff)
159 filter nusers(sigO.extract(0,16)) == 2
160 filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set())
161 optional
162 endmatch
163
164 match ffO_hi
165 select ffO_hi->type.in($dff)
166 filter nusers(sigO.extract(16,16)) == 2
167 filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set())
168 optional
169 endmatch
170
171 code clock clock_pol sigO sigCD
172 if (ffO_lo || ffO_hi) {
173 if (ffO_lo) {
174 for (auto b : port(ffO_lo, \Q))
175 if (b.wire->get_bool_attribute(\keep))
176 reject;
177
178 SigBit c = port(ffO_lo, \CLK).as_bit();
179 bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
180
181 if (clock != SigBit() && (c != clock || cp != clock_pol))
182 reject;
183
184 clock = c;
185 clock_pol = cp;
186
187 if (port(ffO_lo, \Q) != sigO.extract(0,16))
188 sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
189 }
190
191 if (ffO_hi) {
192 for (auto b : port(ffO_hi, \Q))
193 if (b.wire->get_bool_attribute(\keep))
194 reject;
195
196 SigBit c = port(ffO_hi, \CLK).as_bit();
197 bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
198
199 if (clock != SigBit() && (c != clock || cp != clock_pol))
200 reject;
201
202 clock = c;
203 clock_pol = cp;
204
205 if (port(ffO_hi, \Q) != sigO.extract(16,16))
206 sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
207 }
208
209 // Loading value into output register is not
210 // supported unless using accumulator
211 if (muxAB) {
212 if (sigCD != sigO)
213 reject;
214 if (muxA)
215 sigCD = port(muxAB, \B);
216 else if (muxB)
217 sigCD = port(muxAB, \A);
218 else log_abort();
219 sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());
220 }
221 }
222 endcode