5 state <SigSpec> sigA sigB sigCD sigH sigO
6 state <Cell*> addAB muxAB
9 select mul->type.in($mul, $__MUL16X16)
10 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
11 select GetSize(mul->getPort(\Y)) > 10
15 // TODO: Support $dffe too by checking if all enable signals are identical
16 select ffA->type.in($dff)
17 filter !port(mul, \A).remove_const().empty()
18 filter includes(port(ffA, \Q).to_sigbit_set(), port(mul, \A).remove_const().to_sigbit_set())
22 code sigA clock clock_pol
26 for (auto b : port(ffA, \Q))
27 if (b.wire->get_bool_attribute(\keep))
30 clock = port(ffA, \CLK).as_bit();
31 clock_pol = param(ffA, \CLK_POLARITY).as_bool();
33 sigA.replace(port(ffA, \Q), port(ffA, \D));
38 select ffB->type.in($dff)
39 filter !port(mul, \B).remove_const().empty()
40 filter includes(port(ffB, \Q).to_sigbit_set(), port(mul, \B).remove_const().to_sigbit_set())
44 code sigB clock clock_pol
48 for (auto b : port(ffB, \Q))
49 if (b.wire->get_bool_attribute(\keep))
52 SigBit c = port(ffB, \CLK).as_bit();
53 bool cp = param(ffB, \CLK_POLARITY).as_bool();
55 if (clock != SigBit() && (c != clock || cp != clock_pol))
61 sigB.replace(port(ffB, \Q), port(ffB, \D));
66 select ffH->type.in($dff)
67 select nusers(port(ffH, \D)) == 2
68 index <SigSpec> port(ffH, \D) === port(mul, \Y)
72 code sigH sigO clock clock_pol
79 if (b.wire->get_bool_attribute(\keep))
84 SigBit c = port(ffH, \CLK).as_bit();
85 bool cp = param(ffH, \CLK_POLARITY).as_bool();
87 if (clock != SigBit() && (c != clock || cp != clock_pol))
96 select addA->type.in($add)
97 select nusers(port(addA, \A)) == 2
98 index <SigSpec> port(addA, \A) === sigH
104 select addB->type.in($add, $sub)
105 select nusers(port(addB, \B)) == 2
106 index <SigSpec> port(addB, \B) === sigH
110 code addAB sigCD sigO
113 sigCD = port(addAB, \B);
114 sigCD.extend_u0(32, param(addAB, \B_SIGNED).as_bool());
118 sigCD = port(addAB, \A);
119 sigCD.extend_u0(32, param(addAB, \A_SIGNED).as_bool());
122 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
123 int actual_mul_width = GetSize(sigH);
124 int actual_acc_width = GetSize(sigO);
126 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
128 if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \B_SIGNED).as_bool()))
131 sigO = port(addAB, \Y);
136 select muxA->type.in($mux)
137 select nusers(port(muxA, \A)) == 2
138 index <SigSpec> port(muxA, \A) === sigO
144 select muxB->type.in($mux)
145 select nusers(port(muxB, \B)) == 2
146 index <SigSpec> port(muxB, \B) === sigO
158 select ffO_lo->type.in($dff)
159 filter nusers(sigO.extract(0,16)) == 2
160 filter includes(port(ffO_lo, \D).to_sigbit_set(), sigO.extract(0,16).to_sigbit_set())
165 select ffO_hi->type.in($dff)
166 filter nusers(sigO.extract(16,16)) == 2
167 filter includes(port(ffO_hi, \D).to_sigbit_set(), sigO.extract(16,16).to_sigbit_set())
171 code clock clock_pol sigO sigCD
172 if (ffO_lo || ffO_hi) {
174 for (auto b : port(ffO_lo, \Q))
175 if (b.wire->get_bool_attribute(\keep))
178 SigBit c = port(ffO_lo, \CLK).as_bit();
179 bool cp = param(ffO_lo, \CLK_POLARITY).as_bool();
181 if (clock != SigBit() && (c != clock || cp != clock_pol))
187 if (port(ffO_lo, \Q) != sigO.extract(0,16))
188 sigO.replace(port(ffO_lo, \D), port(ffO_lo, \Q));
192 for (auto b : port(ffO_hi, \Q))
193 if (b.wire->get_bool_attribute(\keep))
196 SigBit c = port(ffO_hi, \CLK).as_bit();
197 bool cp = param(ffO_hi, \CLK_POLARITY).as_bool();
199 if (clock != SigBit() && (c != clock || cp != clock_pol))
205 if (port(ffO_hi, \Q) != sigO.extract(16,16))
206 sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
209 // Loading value into output register is not
210 // supported unless using accumulator
215 sigCD = port(muxAB, \B);
217 sigCD = port(muxAB, \A);
219 sigCD.extend_u0(32, addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool());