4 state <bool> clock_pol cd_signed o_lo
5 state <SigSpec> sigA sigB sigCD sigH sigO
7 state <IdString> addAB muxAB
9 state <bool> ffAholdpol ffBholdpol ffCDholdpol ffOholdpol
10 state <bool> ffArstpol ffBrstpol ffCDrstpol ffOrstpol
12 state <Cell*> ffA ffAholdmux ffArstmux ffB ffBholdmux ffBrstmux ffCD ffCDholdmux
13 state <Cell*> ffFJKG ffH ffO ffOholdmux ffOrstmux
16 state <SigSpec> argQ argD
17 state <bool> ffholdpol ffrstpol
19 udata <SigSpec> dffD dffQ
20 udata <SigBit> dffclock
21 udata <Cell*> dff dffholdmux dffrstmux
22 udata <bool> dffholdpol dffrstpol dffclock_pol
25 select mul->type.in($mul, \SB_MAC16)
26 select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
30 auto unextend = [](const SigSpec &sig) {
32 for (i = GetSize(sig)-1; i > 0; i--)
33 if (sig[i] != sig[i-1])
35 // Do not remove non-const sign bit
38 return sig.extract(0, i);
40 sigA = unextend(port(mul, \A));
41 sigB = unextend(port(mul, \B));
44 if (mul->type == $mul)
46 else if (mul->type == \SB_MAC16)
52 // Only care about those bits that are used
54 for (i = 0; i < GetSize(O); i++) {
55 if (nusers(O[i]) <= 1)
59 // This sigM could have no users if downstream sinks (e.g. $add) is
60 // narrower than $mul result, for example
64 log_assert(nusers(O.extract_end(i)) <= 1);
67 code argQ ffA ffAholdmux ffArstmux ffAholdpol ffArstpol sigA clock clock_pol
68 if (mul->type != \SB_MAC16 || !param(mul, \A_REG).as_bool()) {
74 clock_pol = dffclock_pol;
76 ffArstmux = dffrstmux;
77 ffArstpol = dffrstpol;
80 ffAholdmux = dffholdmux;
81 ffAholdpol = dffholdpol;
88 code argQ ffB ffBholdmux ffBrstmux ffBholdpol ffBrstpol sigB clock clock_pol
89 if (mul->type != \SB_MAC16 || !param(mul, \B_REG).as_bool()) {
95 clock_pol = dffclock_pol;
97 ffBrstmux = dffrstmux;
98 ffBrstpol = dffrstpol;
101 ffBholdmux = dffholdmux;
102 ffBholdpol = dffholdpol;
109 code argD ffFJKG sigH clock clock_pol
110 if (nusers(sigH) == 2 &&
111 (mul->type != \SB_MAC16 ||
112 (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool()))) {
114 subpattern(out_dffe);
116 // F/J/K/G do not have a CE-like (hold) input
120 // Reset signal of F/J (IRSTTOP) and K/G (IRSTBOT)
121 // shared with A and B
122 if ((ffArstmux != NULL) != (dffrstmux != NULL))
124 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
127 if (port(ffArstmux, \S) != port(dffrstmux, \S))
129 if (ffArstpol != dffrstpol)
133 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
135 if (ffBrstpol != dffrstpol)
141 clock_pol = dffclock_pol;
149 code argD ffH sigH sigO clock clock_pol
150 if (ffFJKG && nusers(sigH) == 2 &&
151 (mul->type != \SB_MAC16 || !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())) {
153 subpattern(out_dffe);
155 // H does not have a CE-like (hold) input
159 // Reset signal of H (IRSTBOT) shared with B
160 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
163 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
165 if (ffBrstpol != dffrstpol)
171 clock_pol = dffclock_pol;
182 if mul->type != \SB_MAC16 || (param(mul, \TOPOUTPUT_SELECT).as_int() == 3 && param(mul, \BOTOUTPUT_SELECT).as_int() == 3)
184 select add->type.in($add)
185 choice <IdString> AB {\A, \B}
186 select nusers(port(add, AB)) == 2
188 index <SigBit> port(add, AB)[0] === sigH[0]
189 filter GetSize(port(add, AB)) <= GetSize(sigH)
190 filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
191 filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
196 code sigCD sigO cd_signed
198 sigCD = port(add, addAB == \A ? \B : \A);
199 cd_signed = param(add, addAB == \A ? \B_SIGNED : \A_SIGNED).as_bool();
201 int natural_mul_width = GetSize(sigA) + GetSize(sigB);
202 int actual_mul_width = GetSize(sigH);
203 int actual_acc_width = GetSize(sigCD);
205 if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
207 // If accumulator, check adder width and signedness
208 if (sigCD == sigH && (actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(add, \A_SIGNED).as_bool()))
211 sigO = port(add, \Y);
216 select mux->type == $mux
217 choice <IdString> AB {\A, \B}
218 select nusers(port(mux, AB)) == 2
219 index <SigSpec> port(mux, AB) === sigO
226 sigO = port(mux, \Y);
229 code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
230 if (mul->type != \SB_MAC16 ||
231 // Ensure that register is not already used
232 ((param(mul, \TOPOUTPUT_SELECT).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT).as_int() != 1) &&
233 // Ensure that OLOADTOP/OLOADBOT is unused or zero
234 (port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
238 // First try entire sigO
239 if (nusers(sigO) == 2) {
241 subpattern(out_dffe);
244 // Otherwise try just its least significant 16 bits
245 if (!dff && GetSize(sigO) > 16) {
246 argD = sigO.extract(0, 16);
247 if (nusers(argD) == 2) {
248 subpattern(out_dffe);
256 clock_pol = dffclock_pol;
258 ffOrstmux = dffrstmux;
259 ffOrstpol = dffrstpol;
262 ffOholdmux = dffholdmux;
263 ffOholdpol = dffholdpol;
266 sigO.replace(sigO.extract(0, GetSize(dffQ)), dffQ);
269 // Loading value into output register is not
270 // supported unless using accumulator
274 sigCD = port(mux, muxAB == \B ? \A : \B);
276 cd_signed = add && param(add, \A_SIGNED).as_bool() && param(add, \B_SIGNED).as_bool();
281 code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
282 if (!sigCD.empty() && sigCD != sigO &&
283 (mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
288 ffCDholdmux = dffholdmux;
289 ffCDholdpol = dffholdpol;
292 // Reset signal of C (IRSTTOP) and D (IRSTBOT)
293 // shared with A and B
294 if ((ffArstmux != NULL) != (dffrstmux != NULL))
296 if ((ffBrstmux != NULL) != (dffrstmux != NULL))
299 if (port(ffArstmux, \S) != port(dffrstmux, \S))
301 if (ffArstpol != dffrstpol)
305 if (port(ffBrstmux, \S) != port(dffrstmux, \S))
307 if (ffBrstpol != dffrstpol)
313 clock_pol = dffclock_pol;
322 sigCD.extend_u0(32, cd_signed);
329 // #######################
332 arg argD argQ clock clock_pol
338 for (auto c : argQ.chunks()) {
341 if (c.wire->get_bool_attribute(\keep))
343 Const init = c.wire->attributes.at(\init, State::Sx);
344 if (!init.is_fully_undef() && !init.is_fully_zero())
350 select ff->type.in($dff)
351 // DSP48E1 does not support clock inversion
352 select param(ff, \CLK_POLARITY).as_bool()
354 slice offset GetSize(port(ff, \D))
355 index <SigBit> port(ff, \Q)[offset] === argQ[0]
357 // Check that the rest of argQ is present
358 filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
359 filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
366 if (clock != SigBit()) {
367 if (port(ff, \CLK) != clock)
369 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
373 SigSpec Q = port(ff, \Q);
375 dffclock = port(ff, \CLK);
376 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
380 dffD.replace(argQ, argD);
381 // Only search for ffrstmux if dffD only
382 // has two (ff, ffrstmux) users
383 if (nusers(dffD) > 2)
389 if false /* TODO: ice40 resets are actually async */
392 select ffrstmux->type.in($mux)
393 index <SigSpec> port(ffrstmux, \Y) === argD
395 choice <IdString> BA {\B, \A}
396 // DSP48E1 only supports reset to zero
397 select port(ffrstmux, BA).is_fully_zero()
399 define <bool> pol (BA == \B)
406 dffrstmux = ffrstmux;
407 dffrstpol = ffrstpol;
408 argD = port(ffrstmux, ffrstpol ? \A : \B);
409 dffD.replace(port(ffrstmux, \Y), argD);
411 // Only search for ffholdmux if argQ has at
412 // least 3 users (ff, <upstream>, ffrstmux) and
413 // dffD only has two (ff, ffrstmux)
414 if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
423 select ffholdmux->type.in($mux)
424 index <SigSpec> port(ffholdmux, \Y) === argD
425 choice <IdString> BA {\B, \A}
426 index <SigSpec> port(ffholdmux, BA) === argQ
427 define <bool> pol (BA == \B)
434 dffholdmux = ffholdmux;
435 dffholdpol = ffholdpol;
436 argD = port(ffholdmux, ffholdpol ? \A : \B);
437 dffD.replace(port(ffholdmux, \Y), argD);
440 dffholdmux = nullptr;
443 // #######################
446 arg argD argQ clock clock_pol
450 for (auto c : argD.chunks())
451 if (c.wire->get_bool_attribute(\keep))
456 select ffholdmux->type.in($mux)
457 // ffholdmux output must have two users: ffholdmux and ff.D
458 select nusers(port(ffholdmux, \Y)) == 2
460 choice <IdString> BA {\B, \A}
461 // keep-last-value net must have at least three users: ffholdmux, ff, downstream sink(s)
462 select nusers(port(ffholdmux, BA)) >= 3
464 slice offset GetSize(port(ffholdmux, \Y))
465 define <IdString> AB (BA == \B ? \A : \B)
466 index <SigBit> port(ffholdmux, AB)[offset] === argD[0]
468 // Check that the rest of argD is present
469 filter GetSize(port(ffholdmux, AB)) >= offset + GetSize(argD)
470 filter port(ffholdmux, AB).extract(offset, GetSize(argD)) == argD
473 define <bool> pol (BA == \B)
480 dffholdmux = ffholdmux;
482 SigSpec AB = port(ffholdmux, ffholdpol ? \A : \B);
483 SigSpec Y = port(ffholdmux, \Y);
486 argQ.replace(AB, port(ffholdmux, ffholdpol ? \B : \A));
488 dffholdmux = ffholdmux;
489 dffholdpol = ffholdpol;
494 if false /* TODO: ice40 resets are actually async */
496 select ffrstmux->type.in($mux)
497 // ffrstmux output must have two users: ffrstmux and ff.D
498 select nusers(port(ffrstmux, \Y)) == 2
500 choice <IdString> BA {\B, \A}
501 // DSP48E1 only supports reset to zero
502 select port(ffrstmux, BA).is_fully_zero()
504 slice offset GetSize(port(ffrstmux, \Y))
505 define <IdString> AB (BA == \B ? \A : \B)
506 index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
508 // Check that offset is consistent
509 filter !ffholdmux || ffoffset == offset
510 // Check that the rest of argD is present
511 filter GetSize(port(ffrstmux, AB)) >= offset + GetSize(argD)
512 filter port(ffrstmux, AB).extract(offset, GetSize(argD)) == argD
515 define <bool> pol (AB == \A)
522 dffrstmux = ffrstmux;
524 SigSpec AB = port(ffrstmux, ffrstpol ? \A : \B);
525 SigSpec Y = port(ffrstmux, \Y);
528 dffrstmux = ffrstmux;
529 dffrstpol = ffrstpol;
534 select ff->type.in($dff)
535 // SB_MAC16 does not support clock inversion
536 select param(ff, \CLK_POLARITY).as_bool()
538 slice offset GetSize(port(ff, \D))
539 index <SigBit> port(ff, \D)[offset] === argD[0]
541 // Check that offset is consistent
542 filter (!ffholdmux && !ffrstmux) || ffoffset == offset
543 // Check that the rest of argD is present
544 filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
545 filter port(ff, \D).extract(offset, GetSize(argD)) == argD
546 // Check that FF.Q is connected to CE-mux
547 filter !ffholdmux || port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
554 if (clock != SigBit()) {
555 if (port(ff, \CLK) != clock)
557 if (param(ff, \CLK_POLARITY).as_bool() != clock_pol)
560 SigSpec D = port(ff, \D);
561 SigSpec Q = port(ff, \Q);
567 for (auto c : argQ.chunks()) {
568 Const init = c.wire->attributes.at(\init, State::Sx);
569 if (!init.is_fully_undef() && !init.is_fully_zero())
575 dffclock = port(ff, \CLK);
576 dffclock_pol = param(ff, \CLK_POLARITY).as_bool();
578 // No enable/reset mux possible without flop
579 else if (dffholdmux || dffrstmux)