3 state <IdString> cemuxAB
6 select dff->type == $dff
7 select GetSize(port(dff, \D)) > 1
11 select cemux->type == $mux
12 select GetSize(port(cemux, \Y)) > 1
13 index <SigSpec> port(cemux, \Y) === port(dff, \D)
14 choice <IdString> AB {\A, \B}
15 index <SigSpec> port(cemux, AB) === port(dff, \Q)
20 SigSpec &D = cemux->connections_.at(cemuxAB == \A ? \B : \A);
21 SigSpec &Q = dff->connections_.at(\Q);
22 int width = GetSize(D);
24 if (D[width-1] == D[width-2]) {
27 SigBit sign = D[width-1];
28 bool is_signed = sign.wire;
30 for (i = width-1; i >= 2; i--) {
32 module->connect(Q[i], sign);
37 module->connect(Q[i], Q[i-1]);
43 cemux->connections_.at(\A).remove(i, width-i);
44 cemux->connections_.at(\B).remove(i, width-i);
45 cemux->connections_.at(\Y).remove(i, width-i);
46 cemux->fixup_parameters();
47 dff->connections_.at(\D).remove(i, width-i);
48 dff->connections_.at(\Q).remove(i, width-i);
49 dff->fixup_parameters();
51 log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
56 for (int i = width-1; i >= 0; i--) {
60 auto it = w->attributes.find(\init);
62 if (it != w->attributes.end())
63 init = it->second[Q[i].offset];
67 if (init == State::Sx || init == D[i].data) {
69 module->connect(Q[i], D[i]);
70 cemux->connections_.at(\A).remove(i);
71 cemux->connections_.at(\B).remove(i);
72 cemux->connections_.at(\Y).remove(i);
73 dff->connections_.at(\D).remove(i);
74 dff->connections_.at(\Q).remove(i);
79 cemux->fixup_parameters();
80 dff->fixup_parameters();
81 log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);