3 state <IdString> cemuxAB rstmuxBA
7 select dff->type == $dff
8 select GetSize(port(dff, \D)) > 1
12 select rstmux->type == $mux
13 select GetSize(port(rstmux, \Y)) > 1
14 index <SigSpec> port(rstmux, \Y) === port(dff, \D)
15 choice <IdString> BA {\B, \A}
16 select port(rstmux, BA).is_fully_const()
23 sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
29 select cemux->type == $mux
30 select GetSize(port(cemux, \Y)) > 1
31 index <SigSpec> port(cemux, \Y) === sigD
32 choice <IdString> AB {\A, \B}
33 index <SigSpec> port(cemux, AB) === port(dff, \Q)
38 SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
39 SigSpec Q = port(dff, \Q);
42 rst = port(rstmux, rstmuxBA).as_const();
43 int width = GetSize(D);
45 SigSpec &ceA = cemux->connections_.at(\A);
46 SigSpec &ceB = cemux->connections_.at(\B);
47 SigSpec &ceY = cemux->connections_.at(\Y);
48 SigSpec &dffD = dff->connections_.at(\D);
49 SigSpec &dffQ = dff->connections_.at(\Q);
51 if (D[width-1] == D[width-2]) {
54 SigBit sign = D[width-1];
55 bool is_signed = sign.wire;
57 for (i = width-1; i >= 2; i--) {
59 module->connect(Q[i], sign);
60 if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
64 module->connect(Q[i], Q[i-1]);
65 if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
70 ceA.remove(i, width-i);
71 ceB.remove(i, width-i);
72 ceY.remove(i, width-i);
73 cemux->fixup_parameters();
74 dffD.remove(i, width-i);
75 dffQ.remove(i, width-i);
76 dff->fixup_parameters();
78 log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
83 for (int i = width-1; i >= 0; i--) {
87 auto it = w->attributes.find(\init);
89 if (it != w->attributes.end())
90 init = it->second[Q[i].offset];
94 if (init == State::Sx || init == D[i].data) {
96 module->connect(Q[i], D[i]);
105 did_something = true;
106 cemux->fixup_parameters();
107 dff->fixup_parameters();
108 log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);