passes/pmgen/peepopt_dffmux.pmg

   1 pattern dffmux
   2
   3 state <IdString> cemuxAB rstmuxBA
   4 state <SigSpec> sigD
   5
   6 match dff
   7         select dff->type == $dff
   8         select GetSize(port(dff, \D)) > 1
   9 endmatch
  10
  11 match rstmux
  12         select rstmux->type == $mux
  13         select GetSize(port(rstmux, \Y)) > 1
  14         index <SigSpec> port(rstmux, \Y) === port(dff, \D)
  15         choice <IdString> BA {\B, \A}
  16         select port(rstmux, BA).is_fully_const()
  17         set rstmuxBA BA
  18         optional
  19 endmatch
  20
  21 code sigD
  22         if (rstmux)
  23                 sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
  24         else
  25                 sigD = port(dff, \D);
  26 endcode
  27
  28 match cemux
  29         select cemux->type == $mux
  30         select GetSize(port(cemux, \Y)) > 1
  31         index <SigSpec> port(cemux, \Y) === sigD
  32         choice <IdString> AB {\A, \B}
  33         index <SigSpec> port(cemux, AB) === port(dff, \Q)
  34         set cemuxAB AB
  35 endmatch
  36
  37 code
  38         SigSpec D = port(cemux, cemuxAB == \A ? \B : \A);
  39         SigSpec Q = port(dff, \Q);
  40         Const rst;
  41         if (rstmux)
  42                 rst = port(rstmux, rstmuxBA).as_const();
  43         int width = GetSize(D);
  44
  45         SigSpec &ceA = cemux->connections_.at(\A);
  46         SigSpec &ceB = cemux->connections_.at(\B);
  47         SigSpec &ceY = cemux->connections_.at(\Y);
  48         SigSpec &dffD = dff->connections_.at(\D);
  49         SigSpec &dffQ = dff->connections_.at(\Q);
  50
  51         if (D[width-1] == D[width-2]) {
  52                 did_something = true;
  53
  54                 SigBit sign = D[width-1];
  55                 bool is_signed = sign.wire;
  56                 int i;
  57                 for (i = width-1; i >= 2; i--) {
  58                         if (!is_signed) {
  59                                 module->connect(Q[i], sign);
  60                                 if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
  61                                         break;
  62                         }
  63                         else {
  64                                 module->connect(Q[i], Q[i-1]);
  65                                 if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
  66                                         break;
  67                         }
  68                 }
  69
  70                 ceA.remove(i, width-i);
  71                 ceB.remove(i, width-i);
  72                 ceY.remove(i, width-i);
  73                 cemux->fixup_parameters();
  74                 dffD.remove(i, width-i);
  75                 dffQ.remove(i, width-i);
  76                 dff->fixup_parameters();
  77
  78                 log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
  79                 accept;
  80         }
  81         else {
  82                 int count = 0;
  83                 for (int i = width-1; i >= 0; i--) {
  84                         if (D[i].wire)
  85                                 continue;
  86                         Wire *w = Q[i].wire;
  87                         auto it = w->attributes.find(\init);
  88                         State init;
  89                         if (it != w->attributes.end())
  90                                 init = it->second[Q[i].offset];
  91                         else
  92                                 init = State::Sx;
  93
  94                         if (init == State::Sx || init == D[i].data) {
  95                                 count++;
  96                                 module->connect(Q[i], D[i]);
  97                                 ceA.remove(i);
  98                                 ceB.remove(i);
  99                                 ceY.remove(i);
 100                                 dffD.remove(i);
 101                                 dffQ.remove(i);
 102                         }
 103                 }
 104                 if (count > 0) {
 105                         did_something = true;
 106                         cemux->fixup_parameters();
 107                         dff->fixup_parameters();
 108                         log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
 109                 }
 110
 111                 accept;
 112         }
 113 endcode