passes/pmgen/peepopt_dffmux.pmg

   1 pattern dffmux
   2
   3 state <IdString> cemuxAB rstmuxBA
   4 state <SigSpec> sigD
   5
   6 match dff
   7         select dff->type == $dff
   8         select GetSize(port(dff, \D)) > 1
   9 endmatch
  10
  11 match rstmux
  12         select rstmux->type == $mux
  13         select GetSize(port(rstmux, \Y)) > 1
  14         index <SigSpec> port(rstmux, \Y) === port(dff, \D)
  15         choice <IdString> BA {\B, \A}
  16         select port(rstmux, BA).is_fully_const()
  17         set rstmuxBA BA
  18         optional
  19 endmatch
  20
  21 code sigD
  22         if (rstmux)
  23                 sigD = port(rstmux, rstmuxBA == \B ? \A : \B);
  24         else
  25                 sigD = port(dff, \D);
  26 endcode
  27
  28 match cemux
  29         select cemux->type == $mux
  30         select GetSize(port(cemux, \Y)) > 1
  31         index <SigSpec> port(cemux, \Y) === sigD
  32         choice <IdString> AB {\A, \B}
  33         index <SigSpec> port(cemux, AB) === port(dff, \Q)
  34         set cemuxAB AB
  35 endmatch
  36
  37 code
  38         SigSpec &D = cemux->connections_.at(cemuxAB == \A ? \B : \A);
  39         SigSpec &Q = dff->connections_.at(\Q);
  40         Const rst;
  41         if (rstmux)
  42                 rst = port(rstmux, rstmuxBA).as_const();
  43         int width = GetSize(D);
  44
  45         if (D[width-1] == D[width-2]) {
  46                 did_something = true;
  47
  48                 SigBit sign = D[width-1];
  49                 bool is_signed = sign.wire;
  50                 int i;
  51                 for (i = width-1; i >= 2; i--) {
  52                         if (!is_signed) {
  53                                 module->connect(Q[i], sign);
  54                                 if (D[i-1] != sign || (rst.size() && rst[i-1] != rst[width-1]))
  55                                         break;
  56                         }
  57                         else {
  58                                 module->connect(Q[i], Q[i-1]);
  59                                 if (D[i-2] != sign || (rst.size() && rst[i-1] != rst[width-1]))
  60                                         break;
  61                         }
  62                 }
  63
  64                 cemux->connections_.at(\A).remove(i, width-i);
  65                 cemux->connections_.at(\B).remove(i, width-i);
  66                 cemux->connections_.at(\Y).remove(i, width-i);
  67                 cemux->fixup_parameters();
  68                 dff->connections_.at(\D).remove(i, width-i);
  69                 dff->connections_.at(\Q).remove(i, width-i);
  70                 dff->fixup_parameters();
  71
  72                 log("dffcemux pattern in %s: dff=%s, cemux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux), width-i);
  73                 accept;
  74         }
  75         else {
  76                 int count = 0;
  77                 for (int i = width-1; i >= 0; i--) {
  78                         if (D[i].wire)
  79                                 continue;
  80                         Wire *w = Q[i].wire;
  81                         auto it = w->attributes.find(\init);
  82                         State init;
  83                         if (it != w->attributes.end())
  84                                 init = it->second[Q[i].offset];
  85                         else
  86                                 init = State::Sx;
  87
  88                         if (init == State::Sx || init == D[i].data) {
  89                                 count++;
  90                                 module->connect(Q[i], D[i]);
  91                                 cemux->connections_.at(\A).remove(i);
  92                                 cemux->connections_.at(\B).remove(i);
  93                                 cemux->connections_.at(\Y).remove(i);
  94                                 dff->connections_.at(\D).remove(i);
  95                                 dff->connections_.at(\Q).remove(i);
  96                         }
  97                 }
  98                 if (count > 0) {
  99                         did_something = true;
 100                         cemux->fixup_parameters();
 101                         dff->fixup_parameters();
 102                         log("dffcemux pattern in %s: dff=%s, cemux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), count);
 103                 }
 104
 105                 accept;
 106         }
 107 endcode