passes/pmgen/peepopt_muldiv.pmg

   1 pattern muldiv
   2
   3 state <SigSpec> t x y
   4
   5 match mul
   6         select mul->type == $mul
   7         select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y))
   8 endmatch
   9
  10 code t x y
  11         t = port(mul, \Y);
  12         x = port(mul, \A);
  13         y = port(mul, \B);
  14         branch;
  15         std::swap(x, y);
  16 endcode
  17
  18 match div
  19         select div->type.in($div)
  20         index <SigSpec> port(div, \A) === t
  21         index <SigSpec> port(div, \B) === x
  22 endmatch
  23
  24 code
  25         SigSpec div_y = port(div, \Y);
  26         SigSpec val_y = y;
  27
  28         if (GetSize(div_y) != GetSize(val_y))
  29                 val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
  30
  31         did_something = true;
  32         log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
  33         module->connect(div_y, val_y);
  34         autoremove(div);
  35         reject;
  36 endcode