passes/pmgen/peepopt_shiftmul.pmg

   1 pattern shiftmul
   2 //
   3 // Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
   4 //
   5
   6 state <SigSpec> shamt
   7
   8 match shift
   9         select shift->type.in($shift, $shiftx, $shr)
  10 endmatch
  11
  12 code shamt
  13         shamt = port(shift, \B);
  14         if (shamt.empty())
  15                 reject;
  16         if (shamt[GetSize(shamt)-1] == State::S0) {
  17                 do {
  18                         shamt.remove(GetSize(shamt)-1);
  19                         if (shamt.empty())
  20                                 reject;
  21                 } while (shamt[GetSize(shamt)-1] == State::S0);
  22         } else
  23         if (shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool()) {
  24                 reject;
  25         }
  26         if (GetSize(shamt) > 20)
  27                 reject;
  28 endcode
  29
  30 match mul
  31         select mul->type.in($mul)
  32         select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const()
  33         index <SigSpec> port(mul, \Y) === shamt
  34         filter !param(mul, \A_SIGNED).as_bool()
  35 endmatch
  36
  37 code
  38 {
  39         IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B;
  40         Const const_factor_cnst = port(mul, const_factor_port).as_const();
  41         int const_factor = const_factor_cnst.as_int();
  42
  43         if (GetSize(const_factor_cnst) == 0)
  44                 reject;
  45
  46         if (GetSize(const_factor_cnst) > 20)
  47                 reject;
  48
  49         if (GetSize(port(shift, \Y)) > const_factor)
  50                 reject;
  51
  52         int factor_bits = ceil_log2(const_factor);
  53         SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
  54
  55         if (GetSize(shamt) < factor_bits+GetSize(mul_din))
  56                 reject;
  57
  58         did_something = true;
  59         log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
  60
  61         int new_const_factor = 1 << factor_bits;
  62         SigSpec padding(State::Sx, new_const_factor-const_factor);
  63         SigSpec old_a = port(shift, \A), new_a;
  64         int trunc = 0;
  65
  66         if (GetSize(old_a) % const_factor != 0) {
  67                 trunc = const_factor - GetSize(old_a) % const_factor;
  68                 old_a.append(SigSpec(State::Sx, trunc));
  69         }
  70
  71         for (int i = 0; i*const_factor < GetSize(old_a); i++) {
  72                 SigSpec slice = old_a.extract(i*const_factor, const_factor);
  73                 new_a.append(slice);
  74                 new_a.append(padding);
  75         }
  76
  77         if (trunc > 0)
  78                 new_a.remove(GetSize(new_a)-trunc, trunc);
  79
  80         SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
  81         if (param(shift, \B_SIGNED).as_bool())
  82                 new_b.append(State::S0);
  83
  84         shift->setPort(\A, new_a);
  85         shift->setParam(\A_WIDTH, GetSize(new_a));
  86         shift->setPort(\B, new_b);
  87         shift->setParam(\B_WIDTH, GetSize(new_b));
  88
  89         blacklist(shift);
  90         accept;
  91 }
  92 endcode