3 // Optimize mul+shift pairs that result from expressions such as foo[s*W+:W]
9 select shift->type.in($shift, $shiftx, $shr)
13 shamt = port(shift, \B);
16 if (shamt[GetSize(shamt)-1] == State::S0) {
18 shamt.remove(GetSize(shamt)-1);
21 } while (shamt[GetSize(shamt)-1] == State::S0);
23 if (shift->type.in($shift, $shiftx) && param(shift, \B_SIGNED).as_bool()) {
26 if (GetSize(shamt) > 20)
31 select mul->type.in($mul)
32 select port(mul, \A).is_fully_const() || port(mul, \B).is_fully_const()
33 index <SigSpec> port(mul, \Y) === shamt
34 filter !param(mul, \A_SIGNED).as_bool()
39 IdString const_factor_port = port(mul, \A).is_fully_const() ? \A : \B;
40 Const const_factor_cnst = port(mul, const_factor_port).as_const();
41 int const_factor = const_factor_cnst.as_int();
43 if (GetSize(const_factor_cnst) == 0)
46 if (GetSize(const_factor_cnst) > 20)
49 if (GetSize(port(shift, \Y)) > const_factor)
52 int factor_bits = ceil_log2(const_factor);
53 SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
55 if (GetSize(shamt) < factor_bits+GetSize(mul_din))
59 log("shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
61 int new_const_factor = 1 << factor_bits;
62 SigSpec padding(State::Sx, new_const_factor-const_factor);
63 SigSpec old_a = port(shift, \A), new_a;
66 if (GetSize(old_a) % const_factor != 0) {
67 trunc = const_factor - GetSize(old_a) % const_factor;
68 old_a.append(SigSpec(State::Sx, trunc));
71 for (int i = 0; i*const_factor < GetSize(old_a); i++) {
72 SigSpec slice = old_a.extract(i*const_factor, const_factor);
74 new_a.append(padding);
78 new_a.remove(GetSize(new_a)-trunc, trunc);
80 SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
81 if (param(shift, \B_SIGNED).as_bool())
82 new_b.append(State::S0);
84 shift->setPort(\A, new_a);
85 shift->setParam(\A_WIDTH, GetSize(new_a));
86 shift->setPort(\B, new_b);
87 shift->setParam(\B_WIDTH, GetSize(new_b));