3 state <IdString> portname
4 udata <vector<pair<Cell*, IdString>>> chain longest_chain
5 udata <pool<Cell*>> non_first_cells
9 non_first_cells.clear();
14 select first->type.in($_AND_, $_OR_, $_XOR_)
15 filter !non_first_cells.count(first)
17 SigSpec A = module->addWire(NEW_ID);
18 SigSpec B = module->addWire(NEW_ID);
19 SigSpec Y = module->addWire(NEW_ID);
23 module->addAndGate(NEW_ID, A, B, Y);
26 module->addOrGate(NEW_ID, A, B, Y);
29 module->addXorGate(NEW_ID, A, B, Y);
36 longest_chain.clear();
37 chain.push_back(make_pair(first, \A));
39 chain.back().second = \B;
43 log_assert(chain.empty());
44 if (GetSize(longest_chain) > 1)
48 // ------------------------------------------------------------------
53 select first->type.in($_AND_, $_OR_, $_XOR_)
63 select next->type.in($_AND_, $_OR_, $_XOR_)
64 select nusers(port(next, \Y)) == 2
65 index <IdString> next->type === first->type
66 index <SigSpec> port(next, \Y) === port(first, portname)
70 non_first_cells.insert(next);
73 // ------------------------------------------------------------------
80 select next->type.in($_AND_, $_OR_, $_XOR_)
81 select nusers(port(next, \Y)) == 2
82 index <IdString> next->type === chain.back().first->type
83 index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
85 SigSpec A = module->addWire(NEW_ID);
86 SigSpec B = module->addWire(NEW_ID);
87 SigSpec Y = port(chain.back().first, chain.back().second);
88 Cell *c = module->addAndGate(NEW_ID, A, B, Y);
89 c->type = chain.back().first->type;
94 chain.push_back(make_pair(next, \A));
96 chain.back().second = \B;
99 if (GetSize(chain) > GetSize(longest_chain))
100 longest_chain = chain;
101 leaves.append(port(chain.back().first, chain.back().second));
108 // ==================================================================
112 state <bool> eq_ne_signed
113 state <SigSpec> eq_inA eq_inB
114 state <int> pmux_slice_eq pmux_slice_ne
117 select eq->type == $eq
118 choice <IdString> AB {\A, \B}
119 define <IdString> BA AB == \A ? \B : \A
120 set eq_inA port(eq, \A)
121 set eq_inB port(eq, \B)
122 set eq_ne_signed param(eq, \A_SIGNED).as_bool()
124 SigSpec A = module->addWire(NEW_ID, rng(7)+1);
125 SigSpec B = module->addWire(NEW_ID, rng(7)+1);
126 SigSpec Y = module->addWire(NEW_ID);
127 module->addEq(NEW_ID, A, B, Y, rng(2));
131 select pmux->type == $pmux
132 slice idx GetSize(port(pmux, \S))
133 index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
134 set pmux_slice_eq idx
136 int width = rng(7) + 1;
137 int numsel = rng(4) + 1;
138 int idx = rng(numsel);
140 SigSpec A = module->addWire(NEW_ID, width);
141 SigSpec Y = module->addWire(NEW_ID, width);
144 for (int i = 0; i < numsel; i++) {
145 B.append(module->addWire(NEW_ID, width));
146 S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
149 module->addPmux(NEW_ID, A, B, S, Y);
153 select ne->type == $ne
154 choice <IdString> AB {\A, \B}
155 define <IdString> BA (AB == \A ? \B : \A)
156 index <SigSpec> port(ne, AB) === eq_inA
157 index <SigSpec> port(ne, BA) === eq_inB
158 index <int> param(ne, \A_SIGNED).as_bool() === eq_ne_signed
160 SigSpec A = eq_inA, B = eq_inB, Y;
165 for (auto bit : port(pmux, \S)) {
170 Y = Y[rng(GetSize(Y))];
172 Y = module->addWire(NEW_ID);
174 Y = module->addWire(NEW_ID);
176 module->addNe(NEW_ID, A, B, Y, rng(2));
180 select pmux2->type == $pmux
181 slice idx GetSize(port(pmux2, \S))
182 index <Cell*> pmux2 === pmux
183 index <SigBit> port(pmux2, \S)[idx] === port(ne, \Y)
184 set pmux_slice_ne idx