passes/pmgen/test_pmgen.pmg

   1 pattern reduce
   2
   3 state <IdString> portname
   4 udata <vector<pair<Cell*, IdString>>> chain longest_chain
   5 udata <pool<Cell*>> non_first_cells
   6 udata <SigSpec> leaves
   7
   8 code
   9         non_first_cells.clear();
  10         subpattern(setup);
  11 endcode
  12
  13 match first
  14         select first->type.in($_AND_, $_OR_, $_XOR_)
  15         filter !non_first_cells.count(first)
  16 generate
  17         SigSpec A = module->addWire(NEW_ID);
  18         SigSpec B = module->addWire(NEW_ID);
  19         SigSpec Y = module->addWire(NEW_ID);
  20         switch (rng(3))
  21         {
  22         case 0:
  23                 module->addAndGate(NEW_ID, A, B, Y);
  24                 break;
  25         case 1:
  26                 module->addOrGate(NEW_ID, A, B, Y);
  27                 break;
  28         case 2:
  29                 module->addXorGate(NEW_ID, A, B, Y);
  30                 break;
  31         }
  32 endmatch
  33
  34 code
  35         leaves = SigSpec();
  36         longest_chain.clear();
  37         chain.push_back(make_pair(first, \A));
  38         subpattern(tail);
  39         chain.back().second = \B;
  40         subpattern(tail);
  41 finally
  42         chain.pop_back();
  43         log_assert(chain.empty());
  44         if (GetSize(longest_chain) > 1)
  45                 accept;
  46 endcode
  47
  48 // ------------------------------------------------------------------
  49
  50 subpattern setup
  51
  52 match first
  53         select first->type.in($_AND_, $_OR_, $_XOR_)
  54 endmatch
  55
  56 code portname
  57         portname = \A;
  58         branch;
  59         portname = \B;
  60 endcode
  61
  62 match next
  63         select next->type.in($_AND_, $_OR_, $_XOR_)
  64         select nusers(port(next, \Y)) == 2
  65         index <IdString> next->type === first->type
  66         index <SigSpec> port(next, \Y) === port(first, portname)
  67 endmatch
  68
  69 code
  70         non_first_cells.insert(next);
  71 endcode
  72
  73 // ------------------------------------------------------------------
  74
  75 subpattern tail
  76 arg first
  77
  78 match next
  79         semioptional
  80         select next->type.in($_AND_, $_OR_, $_XOR_)
  81         select nusers(port(next, \Y)) == 2
  82         index <IdString> next->type === chain.back().first->type
  83         index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
  84 generate 10
  85         SigSpec A = module->addWire(NEW_ID);
  86         SigSpec B = module->addWire(NEW_ID);
  87         SigSpec Y = port(chain.back().first, chain.back().second);
  88         Cell *c = module->addAndGate(NEW_ID, A, B, Y);
  89         c->type = chain.back().first->type;
  90 endmatch
  91
  92 code
  93         if (next) {
  94                 chain.push_back(make_pair(next, \A));
  95                 subpattern(tail);
  96                 chain.back().second = \B;
  97                 subpattern(tail);
  98         } else {
  99                 if (GetSize(chain) > GetSize(longest_chain))
 100                         longest_chain = chain;
 101                 leaves.append(port(chain.back().first, chain.back().second));
 102         }
 103 finally
 104         if (next)
 105                 chain.pop_back();
 106 endcode
 107
 108 // ==================================================================
 109
 110 pattern eqpmux
 111
 112 state <bool> eq_ne_signed
 113 state <SigSpec> eq_inA eq_inB
 114 state <int> pmux_slice_eq pmux_slice_ne
 115
 116 match eq
 117         select eq->type == $eq
 118         choice <IdString> AB {\A, \B}
 119         define <IdString> BA AB == \A ? \B : \A
 120         set eq_inA port(eq, \A)
 121         set eq_inB port(eq, \B)
 122         set eq_ne_signed param(eq, \A_SIGNED).as_bool()
 123 generate 100 10
 124         SigSpec A = module->addWire(NEW_ID, rng(7)+1);
 125         SigSpec B = module->addWire(NEW_ID, rng(7)+1);
 126         SigSpec Y = module->addWire(NEW_ID);
 127         module->addEq(NEW_ID, A, B, Y, rng(2));
 128 endmatch
 129
 130 match pmux
 131         select pmux->type == $pmux
 132         slice idx GetSize(port(pmux, \S))
 133         index <SigBit> port(pmux, \S)[idx] === port(eq, \Y)
 134         set pmux_slice_eq idx
 135 generate 100 10
 136         int width = rng(7) + 1;
 137         int numsel = rng(4) + 1;
 138         int idx = rng(numsel);
 139
 140         SigSpec A = module->addWire(NEW_ID, width);
 141         SigSpec Y = module->addWire(NEW_ID, width);
 142
 143         SigSpec B, S;
 144         for (int i = 0; i < numsel; i++) {
 145                 B.append(module->addWire(NEW_ID, width));
 146                 S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
 147         }
 148
 149         module->addPmux(NEW_ID, A, B, S, Y);
 150 endmatch
 151
 152 match ne
 153         select ne->type == $ne
 154         choice <IdString> AB {\A, \B}
 155         define <IdString> BA (AB == \A ? \B : \A)
 156         index <SigSpec> port(ne, AB) === eq_inA
 157         index <SigSpec> port(ne, BA) === eq_inB
 158         index <int> param(ne, \A_SIGNED).as_bool() === eq_ne_signed
 159 generate 100 10
 160         SigSpec A = eq_inA, B = eq_inB, Y;
 161         if (rng(2)) {
 162                 std::swap(A, B);
 163         }
 164         if (rng(2)) {
 165                 for (auto bit : port(pmux, \S)) {
 166                         if (nusers(bit) < 2)
 167                                 Y.append(bit);
 168                 }
 169                 if (GetSize(Y))
 170                         Y = Y[rng(GetSize(Y))];
 171                 else
 172                         Y = module->addWire(NEW_ID);
 173         } else {
 174                 Y = module->addWire(NEW_ID);
 175         }
 176         module->addNe(NEW_ID, A, B, Y, rng(2));
 177 endmatch
 178
 179 match pmux2
 180         select pmux2->type == $pmux
 181         slice idx GetSize(port(pmux2, \S))
 182         index <Cell*> pmux2 === pmux
 183         index <SigBit> port(pmux2, \S)[idx] === port(ne, \Y)
 184         set pmux_slice_ne idx
 185 endmatch
 186
 187 code
 188         accept;
 189 endcode