passes/pmgen/xilinx_dsp_CREG.pmg

   1 // This file describes the second of three pattern matcher setups that
   2 //   forms the `xilinx_dsp` pass described in xilinx_dsp.cc
   3 // At a high level, it works as follows:
   4 //   (1) Starting from a DSP48E1 cell that (a) doesn't have a CREG already,
   5 //       and (b) uses the 'C' port
   6 //   (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
   7 //       (attached to at most two $mux cells that implement clock-enable or
   8 //        reset functionality, using a subpattern discussed below)
   9 // Notes:
  10 //   - Running CREG packing after xilinx_dsp_pack is necessary since there is no
  11 //     guarantee that the cell ordering corresponds to the "expected" case (i.e.
  12 //     the order in which they appear in the source) thus the possiblity existed
  13 //     that a register got packed as a CREG into a downstream DSP that should
  14 //     have otherwise been a PREG of an upstream DSP that had not been visited
  15 //     yet
  16 //   - The reason this is separated out from the xilinx_dsp.pmg file is
  17 //     for efficiency --- each *.pmg file creates a class of the same basename,
  18 //     which when constructed, creates a custom database tailored to the
  19 //     pattern(s) contained within. Since the pattern in this file must be
  20 //     executed after the pattern contained in xilinx_dsp.pmg, it is necessary
  21 //     to reconstruct this database. Separating the two patterns into
  22 //     independent files causes two smaller, more specific, databases.
  23
  24 pattern xilinx_dsp_packC
  25
  26 udata <std::function<SigSpec(const SigSpec&)>> unextend
  27 state <SigBit> clock
  28 state <SigSpec> sigC sigP
  29 state <bool> ffCcepol ffCrstpol
  30 state <Cell*> ffC ffCcemux ffCrstmux
  31
  32 // Variables used for subpatterns
  33 state <SigSpec> argQ argD
  34 state <bool> ffcepol ffrstpol
  35 state <int> ffoffset
  36 udata <SigSpec> dffD dffQ
  37 udata <SigBit> dffclock
  38 udata <Cell*> dff dffcemux dffrstmux
  39 udata <bool> dffcepol dffrstpol
  40
  41 // (1) Starting from a DSP48E1 cell that (a) doesn't have a CREG already,
  42 //     and (b) uses the 'C' port
  43 match dsp
  44         select dsp->type.in(\DSP48E1)
  45         select param(dsp, \CREG, 1).as_int() == 0
  46         select nusers(port(dsp, \C, SigSpec())) > 1
  47 endmatch
  48
  49 code sigC sigP clock
  50         unextend = [](const SigSpec &sig) {
  51                 int i;
  52                 for (i = GetSize(sig)-1; i > 0; i--)
  53                         if (sig[i] != sig[i-1])
  54                                 break;
  55                 // Do not remove non-const sign bit
  56                 if (sig[i].wire)
  57                         ++i;
  58                 return sig.extract(0, i);
  59         };
  60         sigC = unextend(port(dsp, \C, SigSpec()));
  61
  62         SigSpec P = port(dsp, \P);
  63         if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
  64                 // Only care about those bits that are used
  65                 int i;
  66                 for (i = 0; i < GetSize(P); i++) {
  67                         if (nusers(P[i]) <= 1)
  68                                 break;
  69                         sigP.append(P[i]);
  70                 }
  71                 log_assert(nusers(P.extract_end(i)) <= 1);
  72         }
  73         else
  74                 sigP = P;
  75
  76         clock = port(dsp, \CLK, SigBit());
  77 endcode
  78
  79 // (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
  80 //     (attached to at most two $mux cells that implement clock-enable or
  81 //      reset functionality, using the in_dffe subpattern)
  82 code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
  83         argQ = sigC;
  84         subpattern(in_dffe);
  85         if (dff) {
  86                 ffC = dff;
  87                 clock = dffclock;
  88                 if (dffrstmux) {
  89                         ffCrstmux = dffrstmux;
  90                         ffCrstpol = dffrstpol;
  91                 }
  92                 if (dffcemux) {
  93                         ffCcemux = dffcemux;
  94                         ffCcepol = dffcepol;
  95                 }
  96                 sigC = dffD;
  97         }
  98 endcode
  99
 100 code
 101         if (ffC)
 102                 accept;
 103 endcode
 104
 105 // #######################
 106
 107 // Subpattern for matching against input registers, based on knowledge of the
 108 //   'Q' input. Typically, identifying registers with clock-enable and reset
 109 //   capability would be a task would be handled by other Yosys passes such as
 110 //   dff2dffe, but since DSP inference happens much before this, these patterns
 111 //   have to be manually identified.
 112 // At a high level:
 113 //   (1) Starting from a $dff cell that (partially or fully) drives the given
 114 //       'Q' argument
 115 //   (2) Match for a $mux cell implementing synchronous reset semantics ---
 116 //       one that exclusively drives the 'D' input of the $dff, with one of its
 117 //       $mux inputs being fully zero
 118 //   (3) Match for a $mux cell implement clock enable semantics --- one that
 119 //       exclusively drives the 'D' input of the $dff (or the other input of
 120 //       the reset $mux) and where one of this $mux's inputs is connected to
 121 //       the 'Q' output of the $dff
 122 subpattern in_dffe
 123 arg argD argQ clock
 124
 125 code
 126         dff = nullptr;
 127         for (const auto &c : argQ.chunks()) {
 128                 // Abandon matches when 'Q' is a constant
 129                 if (!c.wire)
 130                         reject;
 131                 // Abandon matches when 'Q' has the keep attribute set
 132                 if (c.wire->get_bool_attribute(\keep))
 133                         reject;
 134                 // Abandon matches when 'Q' has a non-zero init attribute set
 135                 // (not supported by DSP48E1)
 136                 Const init = c.wire->attributes.at(\init, Const());
 137                 for (auto b : init.extract(c.offset, c.width))
 138                         if (b != State::Sx && b != State::S0)
 139                                 reject;
 140         }
 141 endcode
 142
 143 // (1) Starting from a $dff cell that (partially or fully) drives the given
 144 //     'Q' argument
 145 match ff
 146         select ff->type.in($dff)
 147         // DSP48E1 does not support clock inversion
 148         select param(ff, \CLK_POLARITY).as_bool()
 149
 150         slice offset GetSize(port(ff, \D))
 151         index <SigBit> port(ff, \Q)[offset] === argQ[0]
 152
 153         // Check that the rest of argQ is present
 154         filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
 155         filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
 156
 157         filter clock == SigBit() || port(ff, \CLK) == clock
 158
 159         set ffoffset offset
 160 endmatch
 161
 162 code argQ argD
 163         SigSpec Q = port(ff, \Q);
 164         dff = ff;
 165         dffclock = port(ff, \CLK);
 166         dffD = argQ;
 167         argD = port(ff, \D);
 168         argQ = Q;
 169         dffD.replace(argQ, argD);
 170         // Only search for ffrstmux if dffD only
 171         //   has two (ff, ffrstmux) users
 172         if (nusers(dffD) > 2)
 173                 argD = SigSpec();
 174 endcode
 175
 176 // (2) Match for a $mux cell implementing synchronous reset semantics ---
 177 //     exclusively drives the 'D' input of the $dff, with one of the $mux
 178 //     inputs being fully zero
 179 match ffrstmux
 180         if !argD.empty()
 181         select ffrstmux->type.in($mux)
 182         index <SigSpec> port(ffrstmux, \Y) === argD
 183
 184         choice <IdString> BA {\B, \A}
 185         // DSP48E1 only supports reset to zero
 186         select port(ffrstmux, BA).is_fully_zero()
 187
 188         define <bool> pol (BA == \B)
 189         set ffrstpol pol
 190         semioptional
 191 endmatch
 192
 193 code argD
 194         if (ffrstmux) {
 195                 dffrstmux = ffrstmux;
 196                 dffrstpol = ffrstpol;
 197                 argD = port(ffrstmux, ffrstpol ? \A : \B);
 198                 dffD.replace(port(ffrstmux, \Y), argD);
 199
 200                 // Only search for ffcemux if argQ has at
 201                 //   least 3 users (ff, <upstream>, ffrstmux) and
 202                 //   dffD only has two (ff, ffrstmux)
 203                 if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
 204                         argD = SigSpec();
 205         }
 206         else
 207                 dffrstmux = nullptr;
 208 endcode
 209
 210 // (3) Match for a $mux cell implement clock enable semantics --- one that
 211 //     exclusively drives the 'D' input of the $dff (or the other input of
 212 //     the reset $mux) and where one of this $mux's inputs is connected to
 213 //     the 'Q' output of the $dff
 214 match ffcemux
 215         if !argD.empty()
 216         select ffcemux->type.in($mux)
 217         index <SigSpec> port(ffcemux, \Y) === argD
 218         choice <IdString> AB {\A, \B}
 219         index <SigSpec> port(ffcemux, AB) === argQ
 220         define <bool> pol (AB == \A)
 221         set ffcepol pol
 222         semioptional
 223 endmatch
 224
 225 code argD
 226         if (ffcemux) {
 227                 dffcemux = ffcemux;
 228                 dffcepol = ffcepol;
 229                 argD = port(ffcemux, ffcepol ? \B : \A);
 230                 dffD.replace(port(ffcemux, \Y), argD);
 231         }
 232         else
 233                 dffcemux = nullptr;
 234 endcode