passes/pmgen/xilinx_srl.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *            (C) 2019  Eddie Hung    <eddie@fpgeh.com>
   6  *
   7  *  Permission to use, copy, modify, and/or distribute this software for any
   8  *  purpose with or without fee is hereby granted, provided that the above
   9  *  copyright notice and this permission notice appear in all copies.
  10  *
  11  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include "kernel/yosys.h"
  22 #include "kernel/sigtools.h"
  23
  24 USING_YOSYS_NAMESPACE
  25 PRIVATE_NAMESPACE_BEGIN
  26
  27 // for peepopt_pm
  28 bool did_something;
  29
  30 #include "passes/pmgen/xilinx_srl_pm.h"
  31 #include "passes/pmgen/ice40_dsp_pm.h"
  32 #include "passes/pmgen/peepopt_pm.h"
  33
  34 void run_fixed(xilinx_srl_pm &pm)
  35 {
  36         auto &st = pm.st_fixed;
  37         auto &ud = pm.ud_fixed;
  38         auto param_def = [&ud](Cell *cell, IdString param) {
  39                 auto def = ud.default_params.at(std::make_pair(cell->type,param));
  40                 return cell->parameters.at(param, def);
  41         };
  42
  43         log("Found fixed chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
  44
  45         auto last_cell = ud.longest_chain.back();
  46
  47         SigSpec initval;
  48         for (auto cell : ud.longest_chain) {
  49                 log_debug("    %s\n", log_id(cell));
  50                 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
  51                         SigBit Q = cell->getPort(ID(Q));
  52                         log_assert(Q.wire);
  53                         auto it = Q.wire->attributes.find(ID(init));
  54                         if (it != Q.wire->attributes.end()) {
  55                                 auto &i = it->second[Q.offset];
  56                                 initval.append(i);
  57                                 i = State::Sx;
  58                         }
  59                         else
  60                                 initval.append(State::Sx);
  61                 }
  62                 else if (cell->type.in(ID(FDRE), ID(FDRE_1)))
  63                         initval.append(param_def(cell, ID(INIT)));
  64                 else
  65                         log_abort();
  66                 if (cell != last_cell)
  67                         pm.autoremove(cell);
  68         }
  69
  70         Cell *c = last_cell;
  71         SigBit Q = st.first->getPort(ID(Q));
  72         c->setPort(ID(Q), Q);
  73
  74         if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
  75                 c->parameters.clear();
  76                 c->setParam(ID(DEPTH), GetSize(ud.longest_chain));
  77                 c->setParam(ID(INIT), initval.as_const());
  78                 if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
  79                         c->setParam(ID(CLKPOL), 1);
  80                 else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
  81                         c->setParam(ID(CLKPOL), 0);
  82                 else if (c->type.in(ID(FDRE)))
  83                         c->setParam(ID(CLKPOL), param_def(c, ID(IS_C_INVERTED)).as_bool() ? 0 : 1);
  84                 else
  85                         log_abort();
  86                 if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
  87                         c->setParam(ID(ENPOL), 1);
  88                 else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
  89                         c->setParam(ID(ENPOL), 0);
  90                 else
  91                         c->setParam(ID(ENPOL), 2);
  92                 if (c->type.in(ID($_DFF_N_), ID($_DFF_P_)))
  93                         c->setPort(ID(E), State::S1);
  94                 c->setPort(ID(L), GetSize(ud.longest_chain)-1);
  95                 c->type = ID($__XILINX_SHREG_);
  96         }
  97         else
  98                 log_abort();
  99
 100         log("    -> %s (%s)\n", log_id(c), log_id(c->type));
 101 }
 102
 103 void run_variable(xilinx_srl_pm &pm)
 104 {
 105         auto &st = pm.st_variable;
 106         auto &ud = pm.ud_variable;
 107
 108         log("Found variable chain of length %d (%s):\n", GetSize(ud.chain), log_id(st.first->type));
 109
 110         auto last_cell = ud.chain.back().first;
 111         auto last_slice = ud.chain.back().second;
 112
 113         SigSpec initval;
 114         for (const auto &i : ud.chain) {
 115                 auto cell = i.first;
 116                 auto slice = i.second;
 117                 log_debug("    %s\n", log_id(cell));
 118                 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
 119                         SigBit Q = cell->getPort(ID(Q))[slice];
 120                         log_assert(Q.wire);
 121                         auto it = Q.wire->attributes.find(ID(init));
 122                         if (it != Q.wire->attributes.end()) {
 123                                 auto &i = it->second[Q.offset];
 124                                 initval.append(i);
 125                                 i = State::Sx;
 126                         }
 127                         else
 128                                 initval.append(State::Sx);
 129                 }
 130                 else
 131                         log_abort();
 132                 if (cell != last_cell)
 133                         cell->connections_.at(ID(Q))[slice] = pm.module->addWire(NEW_ID);
 134         }
 135         pm.autoremove(st.shiftx);
 136
 137         Cell *c = last_cell;
 138         SigBit Q = st.first->getPort(ID(Q))[last_slice];
 139         c->setPort(ID(Q), Q);
 140
 141         if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
 142                 Const clkpol, enpol;
 143                 if (c->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
 144                         clkpol = 1;
 145                 else if (c->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_)))
 146                         clkpol = 0;
 147                 else if (c->type.in(ID($dff), ID($dffe))) {
 148                         clkpol = c->getParam(ID(CLK_POLARITY));
 149                         c->setPort(ID(C), c->getPort(ID(CLK)));
 150                         c->unsetPort(ID(CLK));
 151                 }
 152                 else
 153                         log_abort();
 154                 if (c->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
 155                         enpol = 1;
 156                 else if (c->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
 157                         enpol = 0;
 158                 else if (c->type.in(ID($dffe))) {
 159                         enpol = c->getParam(ID(EN_POLARITY));
 160                         c->setPort(ID(E), c->getPort(ID(EN)));
 161                         c->unsetPort(ID(EN));
 162                 }
 163                 else
 164                         enpol = 2;
 165                 c->parameters.clear();
 166                 c->setParam(ID(DEPTH), GetSize(ud.chain));
 167                 c->setParam(ID(INIT), initval.as_const());
 168                 c->setParam(ID(CLKPOL), clkpol);
 169                 c->setParam(ID(ENPOL), enpol);
 170                 if (c->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
 171                         c->setPort(ID(E), State::S1);
 172                 c->setPort(ID(L), st.shiftx->getPort(ID(B)));
 173                 c->setPort(ID(Q), st.shiftx->getPort(ID(Y)));
 174                 c->type = ID($__XILINX_SHREG_);
 175         }
 176         else
 177                 log_abort();
 178
 179         log("    -> %s (%s)\n", log_id(c), log_id(c->type));
 180
 181 }
 182
 183 struct XilinxSrlPass : public Pass {
 184         XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
 185         void help() YS_OVERRIDE
 186         {
 187                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 188                 log("\n");
 189                 log("    xilinx_srl [options] [selection]\n");
 190                 log("\n");
 191                 log("This pass converts chains of built-in flops ($_DFF_[NP]_, $_DFFE_*) as well as\n");
 192                 log("Xilinx flops (FDRE, FDRE_1) into a $__XILINX_SHREG cell. Chains must be of the\n");
 193                 log("same type, clock, clock polarity, enable, enable polarity (when relevant).\n");
 194                 log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.");
 195                 log("\n");
 196                 log("    -minlen N\n");
 197                 log("        min length of shift register (default = 3)\n");
 198                 log("\n");
 199                 log("    -fixed\n");
 200                 log("        infer fixed-length shift registers.\n");
 201                 log("\n");
 202                 log("    -variable\n");
 203                 log("        infer variable-length shift registers (i.e. fixed-length shifts where\n");
 204                 log("        each element also fans-out to a $shiftx cell.\n");
 205                 log("\n");
 206         }
 207
 208         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 209         {
 210                 log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
 211
 212                 bool fixed = false;
 213                 bool variable = false;
 214                 int minlen = 3;
 215
 216                 size_t argidx;
 217                 for (argidx = 1; argidx < args.size(); argidx++)
 218                 {
 219                         if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
 220                                 minlen = atoi(args[++argidx].c_str());
 221                                 continue;
 222                         }
 223                         if (args[argidx] == "-fixed") {
 224                                 fixed = true;
 225                                 continue;
 226                         }
 227                         if (args[argidx] == "-variable") {
 228                                 variable = true;
 229                                 continue;
 230                         }
 231                         break;
 232                 }
 233                 extra_args(args, argidx, design);
 234
 235                 if (!fixed && !variable)
 236                         log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
 237
 238                 for (auto module : design->selected_modules()) {
 239                         auto pm = xilinx_srl_pm(module, module->selected_cells());
 240                         pm.ud_fixed.minlen = minlen;
 241                         pm.ud_variable.minlen = minlen;
 242
 243                         if (fixed) {
 244                                 // TODO: How to get these automatically?
 245                                 pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(INIT))] = State::S0;
 246                                 pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_C_INVERTED))] = State::S0;
 247                                 pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_D_INVERTED))] = State::S0;
 248                                 pm.ud_fixed.default_params[std::make_pair(ID(FDRE),ID(IS_R_INVERTED))] = State::S0;
 249                                 pm.run_fixed(run_fixed);
 250                         }
 251                         if (variable)
 252                                 pm.run_variable(run_variable);
 253                 }
 254         }
 255 } XilinxSrlPass;
 256
 257 PRIVATE_NAMESPACE_END