2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * (C) 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
25 PRIVATE_NAMESPACE_BEGIN
30 #include "passes/pmgen/xilinx_srl_pm.h"
31 #include "passes/pmgen/ice40_dsp_pm.h"
32 #include "passes/pmgen/peepopt_pm.h"
34 void run_fixed(xilinx_srl_pm
&pm
)
36 auto &st
= pm
.st_fixed
;
37 auto &ud
= pm
.ud_fixed
;
38 auto param_def
= [&ud
](Cell
*cell
, IdString param
) {
39 auto def
= ud
.default_params
.at(std::make_pair(cell
->type
,param
));
40 return cell
->parameters
.at(param
, def
);
43 log("Found fixed chain of length %d (%s):\n", GetSize(ud
.longest_chain
), log_id(st
.first
->type
));
45 auto last_cell
= ud
.longest_chain
.back();
48 for (auto cell
: ud
.longest_chain
) {
49 log_debug(" %s\n", log_id(cell
));
50 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
))) {
51 SigBit Q
= cell
->getPort(ID(Q
));
53 auto it
= Q
.wire
->attributes
.find(ID(init
));
54 if (it
!= Q
.wire
->attributes
.end()) {
55 initval
.append(it
->second
[Q
.offset
]);
58 initval
.append(State::Sx
);
60 else if (cell
->type
.in(ID(FDRE
), ID(FDRE_1
)))
61 initval
.append(param_def(cell
, ID(INIT
)));
64 if (cell
!= last_cell
)
69 SigBit Q
= st
.first
->getPort(ID(Q
));
72 if (c
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
), ID(FDRE
), ID(FDRE_1
))) {
73 c
->parameters
.clear();
74 c
->setParam(ID(DEPTH
), GetSize(ud
.longest_chain
));
75 c
->setParam(ID(INIT
), initval
.as_const());
76 if (c
->type
.in(ID($_DFF_P_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
77 c
->setParam(ID(CLKPOL
), 1);
78 else if (c
->type
.in(ID($_DFF_N_
), ID($DFFE_NN_
), ID($_DFFE_NP_
), ID(FDRE_1
)))
79 c
->setParam(ID(CLKPOL
), 0);
80 else if (c
->type
.in(ID(FDRE
)))
81 c
->setParam(ID(CLKPOL
), param_def(c
, ID(IS_C_INVERTED
)).as_bool() ? 0 : 1);
84 if (c
->type
.in(ID($_DFFE_NP_
), ID($_DFFE_PP_
)))
85 c
->setParam(ID(ENPOL
), 1);
86 else if (c
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_PN_
)))
87 c
->setParam(ID(ENPOL
), 0);
89 c
->setParam(ID(ENPOL
), 2);
90 if (c
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
91 c
->setPort(ID(E
), State::S1
);
92 c
->setPort(ID(L
), GetSize(ud
.longest_chain
)-1);
93 c
->type
= ID($__XILINX_SHREG_
);
98 log(" -> %s (%s)\n", log_id(c
), log_id(c
->type
));
101 void run_variable(xilinx_srl_pm
&pm
)
103 auto &st
= pm
.st_variable
;
104 auto &ud
= pm
.ud_variable
;
106 log("Found variable chain of length %d (%s):\n", GetSize(ud
.chain
), log_id(st
.first
->type
));
108 auto last_cell
= ud
.chain
.back().first
;
109 auto last_slice
= ud
.chain
.back().second
;
112 for (const auto &i
: ud
.chain
) {
114 auto slice
= i
.second
;
115 log_debug(" %s\n", log_id(cell
));
116 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
), ID($dff
), ID($dffe
))) {
117 SigBit Q
= cell
->getPort(ID(Q
))[slice
];
119 auto it
= Q
.wire
->attributes
.find(ID(init
));
120 if (it
!= Q
.wire
->attributes
.end()) {
121 initval
.append(it
->second
[Q
.offset
]);
124 initval
.append(State::Sx
);
128 if (cell
!= last_cell
)
129 cell
->connections_
.at(ID(Q
))[slice
] = pm
.module
->addWire(NEW_ID
);
131 pm
.autoremove(st
.shiftx
);
134 SigBit Q
= st
.first
->getPort(ID(Q
))[last_slice
];
135 c
->setPort(ID(Q
), Q
);
137 if (c
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
), ID($dff
), ID($dffe
))) {
139 if (c
->type
.in(ID($_DFF_P_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
141 else if (c
->type
.in(ID($_DFF_N_
), ID($DFFE_NN_
), ID($_DFFE_NP_
)))
143 else if (c
->type
.in(ID($dff
), ID($dffe
))) {
144 clkpol
= c
->getParam(ID(CLK_POLARITY
));
145 c
->setPort(ID(C
), c
->getPort(ID(CLK
)));
146 c
->unsetPort(ID(CLK
));
150 if (c
->type
.in(ID($_DFFE_NP_
), ID($_DFFE_PP_
)))
152 else if (c
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_PN_
)))
154 else if (c
->type
.in(ID($dffe
))) {
155 enpol
= c
->getParam(ID(EN_POLARITY
));
156 c
->setPort(ID(E
), c
->getPort(ID(EN
)));
157 c
->unsetPort(ID(EN
));
161 c
->parameters
.clear();
162 c
->setParam(ID(DEPTH
), GetSize(ud
.chain
));
163 c
->setParam(ID(INIT
), initval
.as_const());
164 c
->setParam(ID(CLKPOL
), clkpol
);
165 c
->setParam(ID(ENPOL
), enpol
);
166 if (c
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($dff
)))
167 c
->setPort(ID(E
), State::S1
);
168 c
->setPort(ID(L
), st
.shiftx
->getPort(ID(B
)));
169 c
->setPort(ID(Q
), st
.shiftx
->getPort(ID(Y
)));
170 c
->type
= ID($__XILINX_SHREG_
);
175 log(" -> %s (%s)\n", log_id(c
), log_id(c
->type
));
179 struct XilinxSrlPass
: public Pass
{
180 XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
181 void help() YS_OVERRIDE
183 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
185 log(" xilinx_srl [options] [selection]\n");
187 log("This pass converts chains of built-in flops ($_DFF_[NP]_, $_DFFE_*) as well as\n");
188 log("Xilinx flops (FDRE, FDRE_1) into a $__XILINX_SHREG cell. Chains must be of the\n");
189 log("same type, clock, clock polarity, enable, enable polarity (when relevant).\n");
190 log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.");
193 log(" min length of shift register (default = 3)\n");
196 log(" infer fixed-length shift registers.\n");
199 log(" infer variable-length shift registers (i.e. fixed-length shifts where\n");
200 log(" each element also fans-out to a $shiftx cell.\n");
204 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
206 log_header(design
, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
209 bool variable
= false;
213 for (argidx
= 1; argidx
< args
.size(); argidx
++)
215 if (args
[argidx
] == "-minlen" && argidx
+1 < args
.size()) {
216 minlen
= atoi(args
[++argidx
].c_str());
219 if (args
[argidx
] == "-fixed") {
223 if (args
[argidx
] == "-variable") {
229 extra_args(args
, argidx
, design
);
231 if (!fixed
&& !variable
)
232 log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
234 for (auto module
: design
->selected_modules()) {
235 auto pm
= xilinx_srl_pm(module
, module
->selected_cells());
236 pm
.ud_fixed
.minlen
= minlen
;
237 pm
.ud_variable
.minlen
= minlen
;
240 // TODO: How to get these automatically?
241 pm
.ud_fixed
.default_params
[std::make_pair(ID(FDRE
),ID(INIT
))] = State::S0
;
242 pm
.ud_fixed
.default_params
[std::make_pair(ID(FDRE
),ID(IS_C_INVERTED
))] = State::S0
;
243 pm
.ud_fixed
.default_params
[std::make_pair(ID(FDRE
),ID(IS_D_INVERTED
))] = State::S0
;
244 pm
.ud_fixed
.default_params
[std::make_pair(ID(FDRE
),ID(IS_R_INVERTED
))] = State::S0
;
245 pm
.run_fixed(run_fixed
);
248 pm
.run_variable(run_variable
);
253 PRIVATE_NAMESPACE_END