2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 * (C) 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include "kernel/yosys.h"
22 #include "kernel/sigtools.h"
25 PRIVATE_NAMESPACE_BEGIN
27 #include "passes/pmgen/xilinx_srl_pm.h"
29 void run_fixed(xilinx_srl_pm
&pm
)
31 auto &st
= pm
.st_fixed
;
32 auto &ud
= pm
.ud_fixed
;
33 log("Found fixed chain of length %d (%s):\n", GetSize(ud
.longest_chain
), log_id(st
.first
->type
));
36 for (auto cell
: ud
.longest_chain
) {
37 log_debug(" %s\n", log_id(cell
));
38 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
))) {
39 SigBit Q
= cell
->getPort(ID::Q
);
41 auto it
= Q
.wire
->attributes
.find(ID::init
);
42 if (it
!= Q
.wire
->attributes
.end()) {
43 auto &i
= it
->second
[Q
.offset
];
48 initval
.append(State::Sx
);
50 else if (cell
->type
.in(ID(FDRE
), ID(FDRE_1
))) {
51 if (cell
->getParam(ID::INIT
).as_bool())
52 initval
.append(State::S1
);
54 initval
.append(State::S0
);
61 auto first_cell
= ud
.longest_chain
.back();
62 auto last_cell
= ud
.longest_chain
.front();
63 Cell
*c
= pm
.module
->addCell(NEW_ID
, ID($__XILINX_SHREG_
));
64 pm
.module
->swap_names(c
, first_cell
);
66 if (first_cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
), ID(FDRE
), ID(FDRE_1
))) {
67 c
->setParam(ID::DEPTH
, GetSize(ud
.longest_chain
));
68 c
->setParam(ID::INIT
, initval
.as_const());
69 if (first_cell
->type
.in(ID($_DFF_P_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
70 c
->setParam(ID(CLKPOL
), 1);
71 else if (first_cell
->type
.in(ID($_DFF_N_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID(FDRE_1
)))
72 c
->setParam(ID(CLKPOL
), 0);
73 else if (first_cell
->type
.in(ID(FDRE
))) {
74 if (!first_cell
->getParam(ID(IS_C_INVERTED
)).as_bool())
75 c
->setParam(ID(CLKPOL
), 1);
77 c
->setParam(ID(CLKPOL
), 0);
81 if (first_cell
->type
.in(ID($_DFFE_NP_
), ID($_DFFE_PP_
)))
82 c
->setParam(ID(ENPOL
), 1);
83 else if (first_cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_PN_
)))
84 c
->setParam(ID(ENPOL
), 0);
86 c
->setParam(ID(ENPOL
), 2);
88 c
->setPort(ID::C
, first_cell
->getPort(ID::C
));
89 c
->setPort(ID::D
, first_cell
->getPort(ID::D
));
90 c
->setPort(ID::Q
, last_cell
->getPort(ID::Q
));
91 c
->setPort(ID::L
, GetSize(ud
.longest_chain
)-1);
92 if (first_cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
93 c
->setPort(ID::E
, State::S1
);
94 else if (first_cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
95 c
->setPort(ID::E
, first_cell
->getPort(ID::E
));
96 else if (first_cell
->type
.in(ID(FDRE
), ID(FDRE_1
)))
97 c
->setPort(ID::E
, first_cell
->getPort(ID(CE
)));
104 log(" -> %s (%s)\n", log_id(c
), log_id(c
->type
));
107 void run_variable(xilinx_srl_pm
&pm
)
109 auto &st
= pm
.st_variable
;
110 auto &ud
= pm
.ud_variable
;
112 log("Found variable chain of length %d (%s):\n", GetSize(ud
.chain
), log_id(st
.first
->type
));
115 for (const auto &i
: ud
.chain
) {
117 auto slice
= i
.second
;
118 log_debug(" %s\n", log_id(cell
));
119 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
), ID($dff
), ID($dffe
))) {
120 SigBit Q
= cell
->getPort(ID::Q
)[slice
];
122 auto it
= Q
.wire
->attributes
.find(ID::init
);
123 if (it
!= Q
.wire
->attributes
.end()) {
124 auto &i
= it
->second
[Q
.offset
];
129 initval
.append(State::Sx
);
134 pm
.autoremove(st
.shiftx
);
136 auto first_cell
= ud
.chain
.back().first
;
137 auto first_slice
= ud
.chain
.back().second
;
139 Cell
*c
= pm
.module
->addCell(NEW_ID
, ID($__XILINX_SHREG_
));
140 pm
.module
->swap_names(c
, first_cell
);
142 if (first_cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
), ID($dff
), ID($dffe
))) {
143 c
->setParam(ID::DEPTH
, GetSize(ud
.chain
));
144 c
->setParam(ID::INIT
, initval
.as_const());
146 if (first_cell
->type
.in(ID($_DFF_P_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
148 else if (first_cell
->type
.in(ID($_DFF_N_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
)))
150 else if (first_cell
->type
.in(ID($dff
), ID($dffe
)))
151 clkpol
= first_cell
->getParam(ID::CLK_POLARITY
);
154 if (first_cell
->type
.in(ID($_DFFE_NP_
), ID($_DFFE_PP_
)))
156 else if (first_cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_PN_
)))
158 else if (first_cell
->type
.in(ID($dffe
)))
159 enpol
= first_cell
->getParam(ID::EN_POLARITY
);
162 c
->setParam(ID(CLKPOL
), clkpol
);
163 c
->setParam(ID(ENPOL
), enpol
);
165 if (first_cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
166 c
->setPort(ID::C
, first_cell
->getPort(ID::C
));
167 else if (first_cell
->type
.in(ID($dff
), ID($dffe
)))
168 c
->setPort(ID::C
, first_cell
->getPort(ID::CLK
));
171 c
->setPort(ID::D
, first_cell
->getPort(ID::D
)[first_slice
]);
172 c
->setPort(ID::Q
, st
.shiftx
->getPort(ID::Y
));
173 c
->setPort(ID::L
, st
.shiftx
->getPort(ID::B
));
174 if (first_cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
), ID($dff
)))
175 c
->setPort(ID::E
, State::S1
);
176 else if (first_cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
177 c
->setPort(ID::E
, first_cell
->getPort(ID::E
));
178 else if (first_cell
->type
.in(ID($dffe
)))
179 c
->setPort(ID::E
, first_cell
->getPort(ID::EN
));
186 log(" -> %s (%s)\n", log_id(c
), log_id(c
->type
));
189 struct XilinxSrlPass
: public Pass
{
190 XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { }
193 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
195 log(" xilinx_srl [options] [selection]\n");
197 log("This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*\n");
198 log("and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a\n");
199 log("$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock polarity,\n");
200 log("enable, and enable polarity (where relevant).\n");
201 log("Flops with resets cannot be mapped to Xilinx devices and will not be inferred.");
204 log(" min length of shift register (default = 3)\n");
207 log(" infer fixed-length shift registers.\n");
210 log(" infer variable-length shift registers (i.e. fixed-length shifts where\n");
211 log(" each element also fans-out to a $shiftx cell).\n");
215 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) override
217 log_header(design
, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n");
220 bool variable
= false;
224 for (argidx
= 1; argidx
< args
.size(); argidx
++)
226 if (args
[argidx
] == "-minlen" && argidx
+1 < args
.size()) {
227 minlen
= atoi(args
[++argidx
].c_str());
230 if (args
[argidx
] == "-fixed") {
234 if (args
[argidx
] == "-variable") {
240 extra_args(args
, argidx
, design
);
242 if (!fixed
&& !variable
)
243 log_cmd_error("'-fixed' and/or '-variable' must be specified.\n");
245 for (auto module
: design
->selected_modules()) {
246 auto pm
= xilinx_srl_pm(module
, module
->selected_cells());
247 pm
.ud_fixed
.minlen
= minlen
;
248 pm
.ud_variable
.minlen
= minlen
;
251 pm
.run_fixed(run_fixed
);
253 pm
.run_variable(run_variable
);
258 PRIVATE_NAMESPACE_END