passes/pmgen/xilinx_srl.pmg

   1 pattern fixed
   2
   3 state <IdString> clk_port en_port
   4 udata <vector<Cell*>> chain longest_chain
   5 udata <pool<Cell*>> non_first_cells
   6 udata <int> minlen
   7
   8 code
   9         non_first_cells.clear();
  10         subpattern(setup);
  11 endcode
  12
  13 match first
  14         select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
  15         select !first->has_keep_attr()
  16         select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED).as_bool()
  17         select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED).as_bool()
  18         select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
  19         filter !non_first_cells.count(first)
  20 generate
  21         SigSpec C = module->addWire(NEW_ID);
  22         SigSpec D = module->addWire(NEW_ID);
  23         SigSpec Q = module->addWire(NEW_ID);
  24         auto r = rng(8);
  25         Cell* cell;
  26         switch (r)
  27         {
  28         case 0:
  29         case 1:
  30                 cell = module->addCell(NEW_ID, \FDRE);
  31                 cell->setPort(\C, C);
  32                 cell->setPort(\D, D);
  33                 cell->setPort(\Q, Q);
  34                 cell->setPort(\CE, module->addWire(NEW_ID));
  35                 if (r & 1)
  36                         cell->setPort(\R, module->addWire(NEW_ID));
  37                 else {
  38                         if (rng(2) == 0)
  39                                 cell->setPort(\R, State::S0);
  40                 }
  41                 break;
  42         case 2:
  43         case 3:
  44                 cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
  45                 break;
  46         case 4:
  47         case 5:
  48         case 6:
  49         case 7:
  50                 cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
  51                 break;
  52         default: log_abort();
  53         }
  54 endmatch
  55
  56 code clk_port en_port
  57         if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
  58                 clk_port = \C;
  59         else log_abort();
  60         if (first->type.in($_DFF_N_, $_DFF_P_))
  61                 en_port = IdString();
  62         else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
  63                 en_port = \E;
  64         else if (first->type.in(\FDRE, \FDRE_1))
  65                 en_port = \CE;
  66         else log_abort();
  67
  68         longest_chain.clear();
  69         chain.push_back(first);
  70         subpattern(tail);
  71 finally
  72         chain.pop_back();
  73         log_assert(chain.empty());
  74         if (GetSize(longest_chain) >= minlen)
  75                 accept;
  76 endcode
  77
  78 // ------------------------------------------------------------------
  79
  80 subpattern setup
  81 arg clk_port
  82 arg en_port
  83
  84 match first
  85         select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
  86         select !first->has_keep_attr()
  87         select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED).as_bool()
  88         select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED).as_bool()
  89         select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
  90 endmatch
  91
  92 code clk_port en_port
  93         if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
  94                 clk_port = \C;
  95         else log_abort();
  96         if (first->type.in($_DFF_N_, $_DFF_P_))
  97                 en_port = IdString();
  98         else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
  99                 en_port = \E;
 100         else if (first->type.in(\FDRE, \FDRE_1))
 101                 en_port = \CE;
 102         else log_abort();
 103 endcode
 104
 105 match next
 106         select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
 107         select !next->has_keep_attr()
 108         select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
 109         select nusers(port(next, \Q)) == 2
 110         index <IdString> next->type === first->type
 111         index <SigBit> port(next, \Q) === port(first, \D)
 112         filter port(next, clk_port) == port(first, clk_port)
 113         filter en_port == IdString() || port(next, en_port) == port(first, en_port)
 114         filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()
 115         filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()
 116         filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
 117         filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
 118 endmatch
 119
 120 code
 121         non_first_cells.insert(next);
 122 endcode
 123
 124 // ------------------------------------------------------------------
 125
 126 subpattern tail
 127 arg first
 128 arg clk_port
 129 arg en_port
 130
 131 match next
 132         semioptional
 133         select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
 134         select !next->has_keep_attr()
 135         select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
 136         select nusers(port(next, \Q)) == 2
 137         index <IdString> next->type === chain.back()->type
 138         index <SigBit> port(next, \Q) === port(chain.back(), \D)
 139         filter port(next, clk_port) == port(first, clk_port)
 140         filter en_port == IdString() || port(next, en_port) == port(first, en_port)
 141         filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()
 142         filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()
 143         filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
 144         filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
 145 generate
 146         Cell *cell = module->addCell(NEW_ID, chain.back()->type);
 147         cell->setPort(\C, chain.back()->getPort(\C));
 148         cell->setPort(\D, module->addWire(NEW_ID));
 149         cell->setPort(\Q, chain.back()->getPort(\D));
 150         if (cell->type == \FDRE) {
 151                 if (rng(2) == 0)
 152                         cell->setPort(\R, port(chain.back(), \R, State::S0));
 153                 cell->setPort(\CE, chain.back()->getPort(\CE));
 154         }
 155         else if (cell->type.begins_with("$_DFFE_"))
 156                 cell->setPort(\E, chain.back()->getPort(\E));
 157 endmatch
 158
 159 code
 160         if (next) {
 161                 chain.push_back(next);
 162                 subpattern(tail);
 163         } else {
 164                 if (GetSize(chain) > GetSize(longest_chain))
 165                         longest_chain = chain;
 166         }
 167 finally
 168         if (next)
 169                 chain.pop_back();
 170 endcode
 171
 172 // -----------
 173
 174 pattern variable
 175
 176 state <IdString> clk_port en_port
 177 state <int> shiftx_width
 178 state <int> slice
 179 udata <int> minlen
 180 udata <vector<pair<Cell*,int>>> chain
 181 udata <pool<SigBit>> chain_bits
 182
 183 code
 184         chain_bits.clear();
 185 endcode
 186
 187 match shiftx
 188         select shiftx->type.in($shiftx)
 189         select !shiftx->has_keep_attr()
 190         select param(shiftx, \Y_WIDTH).as_int() == 1
 191         filter param(shiftx, \A_WIDTH).as_int() >= minlen
 192 generate
 193         minlen = 3;
 194         module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
 195 endmatch
 196
 197 code shiftx_width
 198         shiftx_width = param(shiftx, \A_WIDTH).as_int();
 199 endcode
 200
 201 match first
 202         select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
 203         select !first->has_keep_attr()
 204         select port(first, \Q)[0].wire && !port(first, \Q)[0].wire->get_bool_attribute(\keep)
 205         slice idx GetSize(port(first, \Q))
 206         select nusers(port(first, \Q)[idx]) <= 2
 207         index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
 208         set slice idx
 209 generate
 210         SigSpec C = module->addWire(NEW_ID);
 211         auto WIDTH = rng(3)+1;
 212         SigSpec D = module->addWire(NEW_ID, WIDTH);
 213         SigSpec Q = module->addWire(NEW_ID, WIDTH);
 214         auto r = rng(8);
 215         Cell *cell = nullptr;
 216         switch (r)
 217         {
 218         case 0:
 219         case 1:
 220                 cell = module->addDff(NEW_ID, C, D, Q, r & 1);
 221                 break;
 222         case 2:
 223         case 3:
 224         case 4:
 225         case 5:
 226                 //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
 227                 //break;
 228         case 6:
 229         case 7:
 230                 WIDTH = 1;
 231                 cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
 232                 break;
 233         default: log_abort();
 234         }
 235         shiftx->connections_.at(\A)[shiftx_width-1] = port(cell, \Q)[rng(WIDTH)];
 236 endmatch
 237
 238 code clk_port en_port
 239         if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
 240                 clk_port = \C;
 241         else if (first->type.in($dff, $dffe))
 242                 clk_port = \CLK;
 243         else log_abort();
 244         if (first->type.in($_DFF_N_, $_DFF_P_, $dff))
 245                 en_port = IdString();
 246         else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
 247                 en_port = \E;
 248         else if (first->type.in($dffe))
 249                 en_port = \EN;
 250         else log_abort();
 251
 252         chain_bits.insert(port(first, \Q)[slice]);
 253         chain.emplace_back(first, slice);
 254         subpattern(tail);
 255 finally
 256         if (GetSize(chain) == shiftx_width)
 257                 accept;
 258         chain.clear();
 259 endcode
 260
 261 // ------------------------------------------------------------------
 262
 263 subpattern tail
 264 arg first
 265 arg shiftx
 266 arg shiftx_width
 267 arg slice
 268 arg clk_port
 269 arg en_port
 270
 271 match next
 272         semioptional
 273         select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
 274         select !next->has_keep_attr()
 275         select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
 276         slice idx GetSize(port(next, \Q))
 277         select nusers(port(next, \Q)[idx]) <= 3
 278         index <IdString> next->type === chain.back().first->type
 279         index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
 280         index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
 281         filter port(next, clk_port) == port(first, clk_port)
 282         filter en_port == IdString() || port(next, en_port) == port(first, en_port)
 283         filter !next->type.in($dff, $dffe) || param(next, \CLK_POLARITY).as_bool() == param(first, \CLK_POLARITY).as_bool()
 284         filter !next->type.in($dffe) || param(next, \EN_POLARITY).as_bool() == param(first, \EN_POLARITY).as_bool()
 285         filter !chain_bits.count(port(next, \D)[idx])
 286         set slice idx
 287 generate
 288         if (GetSize(chain) < shiftx_width) {
 289                 auto back = chain.back().first;
 290                 auto slice = chain.back().second;
 291                 if (back->type.in($dff, $dffe)) {
 292                         auto WIDTH = GetSize(port(back, \D));
 293                         if (rng(2) == 0 && slice < WIDTH-1) {
 294                                 auto new_slice = slice + rng(WIDTH-1-slice);
 295                                 back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
 296                         }
 297                         else {
 298                                 auto D = module->addWire(NEW_ID, WIDTH);
 299                                 if (back->type == $dff)
 300                                         module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
 301                                 else if (back->type == $dffe)
 302                                         module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
 303                                 else
 304                                         log_abort();
 305                         }
 306                 }
 307                 else if (back->type.begins_with("$_DFF_")) {
 308                         Cell *cell = module->addCell(NEW_ID, back->type);
 309                         cell->setPort(\C, back->getPort(\C));
 310                         cell->setPort(\D, module->addWire(NEW_ID));
 311                         cell->setPort(\Q, back->getPort(\D));
 312                 }
 313                 else
 314                         log_abort();
 315                 shiftx->connections_.at(\A)[shiftx_width-1-GetSize(chain)] = port(back, \D)[slice];
 316         }
 317 endmatch
 318
 319 code
 320         if (next) {
 321                 chain_bits.insert(port(next, \Q)[slice]);
 322                 chain.emplace_back(next, slice);
 323                 if (GetSize(chain) < shiftx_width)
 324                         subpattern(tail);
 325         }
 326 endcode