3 state <IdString> clk_port en_port
4 udata <vector<Cell*>> chain longest_chain
5 udata <pool<Cell*>> non_first_cells
9 non_first_cells.clear();
14 select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
15 select !first->has_keep_attr()
16 select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED).as_bool()
17 select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED).as_bool()
18 select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
19 filter !non_first_cells.count(first)
21 SigSpec C = module->addWire(NEW_ID);
22 SigSpec D = module->addWire(NEW_ID);
23 SigSpec Q = module->addWire(NEW_ID);
30 cell = module->addCell(NEW_ID, \FDRE);
34 cell->setPort(\CE, module->addWire(NEW_ID));
36 cell->setPort(\R, module->addWire(NEW_ID));
39 cell->setPort(\R, State::S0);
44 cell = module->addDffGate(NEW_ID, C, D, Q, r & 1);
50 cell = module->addDffeGate(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 2);
57 if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
60 if (first->type.in($_DFF_N_, $_DFF_P_))
62 else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
64 else if (first->type.in(\FDRE, \FDRE_1))
68 longest_chain.clear();
69 chain.push_back(first);
73 log_assert(chain.empty());
74 if (GetSize(longest_chain) >= minlen)
78 // ------------------------------------------------------------------
85 select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
86 select !first->has_keep_attr()
87 select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED).as_bool()
88 select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED).as_bool()
89 select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
93 if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1))
96 if (first->type.in($_DFF_N_, $_DFF_P_))
98 else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
100 else if (first->type.in(\FDRE, \FDRE_1))
106 select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
107 select !next->has_keep_attr()
108 select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
109 select nusers(port(next, \Q)) == 2
110 index <IdString> next->type === first->type
111 index <SigBit> port(next, \Q) === port(first, \D)
112 filter port(next, clk_port) == port(first, clk_port)
113 filter en_port == IdString() || port(next, en_port) == port(first, en_port)
114 filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()
115 filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()
116 filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
117 filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
121 non_first_cells.insert(next);
124 // ------------------------------------------------------------------
133 select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
134 select !next->has_keep_attr()
135 select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
136 select nusers(port(next, \Q)) == 2
137 index <IdString> next->type === chain.back()->type
138 index <SigBit> port(next, \Q) === port(chain.back(), \D)
139 filter port(next, clk_port) == port(first, clk_port)
140 filter en_port == IdString() || port(next, en_port) == port(first, en_port)
141 filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED).as_bool() == param(first, \IS_C_INVERTED).as_bool()
142 filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED).as_bool() == param(first, \IS_D_INVERTED).as_bool()
143 filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED).as_bool() == param(first, \IS_R_INVERTED).as_bool()
144 filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
146 Cell *cell = module->addCell(NEW_ID, chain.back()->type);
147 cell->setPort(\C, chain.back()->getPort(\C));
148 cell->setPort(\D, module->addWire(NEW_ID));
149 cell->setPort(\Q, chain.back()->getPort(\D));
150 if (cell->type == \FDRE) {
152 cell->setPort(\R, port(chain.back(), \R, State::S0));
153 cell->setPort(\CE, chain.back()->getPort(\CE));
155 else if (cell->type.begins_with("$_DFFE_"))
156 cell->setPort(\E, chain.back()->getPort(\E));
161 chain.push_back(next);
164 if (GetSize(chain) > GetSize(longest_chain))
165 longest_chain = chain;
176 state <IdString> clk_port en_port
177 state <int> shiftx_width
180 udata <vector<pair<Cell*,int>>> chain
181 udata <pool<SigBit>> chain_bits
188 select shiftx->type.in($shiftx)
189 select !shiftx->has_keep_attr()
190 select param(shiftx, \Y_WIDTH).as_int() == 1
191 filter param(shiftx, \A_WIDTH).as_int() >= minlen
194 module->addShiftx(NEW_ID, module->addWire(NEW_ID, rng(6)+minlen), module->addWire(NEW_ID, 3), module->addWire(NEW_ID));
198 shiftx_width = param(shiftx, \A_WIDTH).as_int();
202 select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
203 select !first->has_keep_attr()
204 select port(first, \Q)[0].wire && !port(first, \Q)[0].wire->get_bool_attribute(\keep)
205 slice idx GetSize(port(first, \Q))
206 select nusers(port(first, \Q)[idx]) <= 2
207 index <SigBit> port(first, \Q)[idx] === port(shiftx, \A)[shiftx_width-1]
210 SigSpec C = module->addWire(NEW_ID);
211 auto WIDTH = rng(3)+1;
212 SigSpec D = module->addWire(NEW_ID, WIDTH);
213 SigSpec Q = module->addWire(NEW_ID, WIDTH);
215 Cell *cell = nullptr;
220 cell = module->addDff(NEW_ID, C, D, Q, r & 1);
226 //cell = module->addDffe(NEW_ID, C, module->addWire(NEW_ID), D, Q, r & 1, r & 4);
231 cell = module->addDffGate(NEW_ID, C, D[0], Q[0], r & 1);
233 default: log_abort();
235 shiftx->connections_.at(\A)[shiftx_width-1] = port(cell, \Q)[rng(WIDTH)];
238 code clk_port en_port
239 if (first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
241 else if (first->type.in($dff, $dffe))
244 if (first->type.in($_DFF_N_, $_DFF_P_, $dff))
245 en_port = IdString();
246 else if (first->type.in($_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_))
248 else if (first->type.in($dffe))
252 chain_bits.insert(port(first, \Q)[slice]);
253 chain.emplace_back(first, slice);
256 if (GetSize(chain) == shiftx_width)
261 // ------------------------------------------------------------------
273 select next->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, $dff, $dffe)
274 select !next->has_keep_attr()
275 select port(next, \D)[0].wire && !port(next, \D)[0].wire->get_bool_attribute(\keep)
276 slice idx GetSize(port(next, \Q))
277 select nusers(port(next, \Q)[idx]) <= 3
278 index <IdString> next->type === chain.back().first->type
279 index <SigBit> port(next, \Q)[idx] === port(chain.back().first, \D)[chain.back().second]
280 index <SigBit> port(next, \Q)[idx] === port(shiftx, \A)[shiftx_width-1-GetSize(chain)]
281 filter port(next, clk_port) == port(first, clk_port)
282 filter en_port == IdString() || port(next, en_port) == port(first, en_port)
283 filter !next->type.in($dff, $dffe) || param(next, \CLK_POLARITY).as_bool() == param(first, \CLK_POLARITY).as_bool()
284 filter !next->type.in($dffe) || param(next, \EN_POLARITY).as_bool() == param(first, \EN_POLARITY).as_bool()
285 filter !chain_bits.count(port(next, \D)[idx])
288 if (GetSize(chain) < shiftx_width) {
289 auto back = chain.back().first;
290 auto slice = chain.back().second;
291 if (back->type.in($dff, $dffe)) {
292 auto WIDTH = GetSize(port(back, \D));
293 if (rng(2) == 0 && slice < WIDTH-1) {
294 auto new_slice = slice + rng(WIDTH-1-slice);
295 back->connections_.at(\D)[slice] = port(back, \Q)[new_slice];
298 auto D = module->addWire(NEW_ID, WIDTH);
299 if (back->type == $dff)
300 module->addDff(NEW_ID, port(back, \CLK), D, port(back, \D), param(back, \CLK_POLARITY).as_bool());
301 else if (back->type == $dffe)
302 module->addDffe(NEW_ID, port(back, \CLK), port(back, \EN), D, port(back, \D), param(back, \CLK_POLARITY).as_bool(), param(back, \EN_POLARITY).as_bool());
307 else if (back->type.begins_with("$_DFF_")) {
308 Cell *cell = module->addCell(NEW_ID, back->type);
309 cell->setPort(\C, back->getPort(\C));
310 cell->setPort(\D, module->addWire(NEW_ID));
311 cell->setPort(\Q, back->getPort(\D));
315 shiftx->connections_.at(\A)[shiftx_width-1-GetSize(chain)] = port(back, \D)[slice];
321 chain_bits.insert(port(next, \Q)[slice]);
322 chain.emplace_back(next, slice);
323 if (GetSize(chain) < shiftx_width)