2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/log.h"
25 struct ProcPass
: public Pass
{
26 ProcPass() : Pass("proc", "translate processes to netlists") { }
29 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
31 log(" proc [selection]\n");
33 log("This pass calls all the other proc_* passes in the most common order.\n");
36 log(" proc_rmdead\n");
42 log("This replaces the processes in the design with multiplexers and flip-flops.\n");
45 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
47 log_header("Executing PROC pass (convert processes to netlists).\n");
50 extra_args(args
, 1, design
);
52 Pass::call(design
, "proc_clean");
53 Pass::call(design
, "proc_rmdead");
54 Pass::call(design
, "proc_arst");
55 Pass::call(design
, "proc_mux");
56 Pass::call(design
, "proc_dff");
57 Pass::call(design
, "proc_clean");