Merge pull request #1577 from gromero/for-yosys
[yosys.git] / passes / proc / proc_clean.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/log.h"
22 #include <stdlib.h>
23 #include <stdio.h>
24
25 YOSYS_NAMESPACE_BEGIN
26 extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth);
27 YOSYS_NAMESPACE_END
28
29 USING_YOSYS_NAMESPACE
30 PRIVATE_NAMESPACE_BEGIN
31
32 void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
33 {
34 if (sw->signal.size() > 0 && sw->signal.is_fully_const())
35 {
36 int found_matching_case_idx = -1;
37 for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)
38 {
39 RTLIL::CaseRule *cs = sw->cases[i];
40 if (cs->compare.size() == 0)
41 break;
42 for (int j = 0; j < int(cs->compare.size()); j++) {
43 RTLIL::SigSpec &val = cs->compare[j];
44 if (!val.is_fully_const())
45 continue;
46 if (val == sw->signal) {
47 cs->compare.clear();
48 found_matching_case_idx = i;
49 break;
50 } else
51 cs->compare.erase(cs->compare.begin()+(j--));
52 }
53 if (cs->compare.size() == 0 && found_matching_case_idx < 0) {
54 sw->cases.erase(sw->cases.begin()+(i--));
55 delete cs;
56 }
57 }
58 while (found_matching_case_idx >= 0 && int(sw->cases.size()) > found_matching_case_idx+1) {
59 delete sw->cases.back();
60 sw->cases.pop_back();
61 }
62 if (found_matching_case_idx == 0)
63 sw->signal = RTLIL::SigSpec();
64 }
65
66 if (parent->switches.front() == sw && sw->cases.size() == 1 &&
67 (sw->signal.size() == 0 || sw->cases[0]->compare.empty()))
68 {
69 did_something = true;
70 for (auto &action : sw->cases[0]->actions)
71 parent->actions.push_back(action);
72 parent->switches.insert(parent->switches.begin(), sw->cases[0]->switches.begin(), sw->cases[0]->switches.end());
73 sw->cases[0]->switches.clear();
74 delete sw->cases[0];
75 sw->cases.clear();
76 }
77 else
78 {
79 bool all_fully_def = true;
80 for (auto cs : sw->cases)
81 {
82 if (max_depth != 0)
83 proc_clean_case(cs, did_something, count, max_depth-1);
84 int size = 0;
85 for (auto cmp : cs->compare)
86 {
87 size += cmp.size();
88 if (!cmp.is_fully_def())
89 all_fully_def = false;
90 }
91 if (sw->signal.size() != size)
92 all_fully_def = false;
93 }
94 if (all_fully_def)
95 {
96 for (auto cs = sw->cases.begin(); cs != sw->cases.end();)
97 {
98 if ((*cs)->empty())
99 {
100 did_something = true;
101 delete *cs;
102 cs = sw->cases.erase(cs);
103 }
104 else ++cs;
105 }
106 }
107 else
108 {
109 while (!sw->cases.empty() && sw->cases.back()->empty())
110 {
111 did_something = true;
112 delete sw->cases.back();
113 sw->cases.pop_back();
114 }
115 }
116 }
117 }
118
119 PRIVATE_NAMESPACE_END
120 YOSYS_NAMESPACE_BEGIN
121
122 void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)
123 {
124 for (size_t i = 0; i < cs->actions.size(); i++) {
125 if (cs->actions[i].first.size() == 0) {
126 did_something = true;
127 cs->actions.erase(cs->actions.begin() + (i--));
128 }
129 }
130 for (size_t i = 0; i < cs->switches.size(); i++) {
131 RTLIL::SwitchRule *sw = cs->switches[i];
132 if (sw->empty()) {
133 cs->switches.erase(cs->switches.begin() + (i--));
134 did_something = true;
135 delete sw;
136 count++;
137 } else if (max_depth != 0)
138 proc_clean_switch(sw, cs, did_something, count, max_depth-1);
139 }
140 }
141
142 YOSYS_NAMESPACE_END
143 PRIVATE_NAMESPACE_BEGIN
144
145 void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool quiet)
146 {
147 int count = 0;
148 bool did_something = true;
149 for (size_t i = 0; i < proc->syncs.size(); i++) {
150 for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++)
151 if (proc->syncs[i]->actions[j].first.size() == 0)
152 proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--));
153 if (proc->syncs[i]->actions.size() == 0) {
154 delete proc->syncs[i];
155 proc->syncs.erase(proc->syncs.begin() + (i--));
156 }
157 }
158 while (did_something) {
159 did_something = false;
160 proc_clean_case(&proc->root_case, did_something, count, -1);
161 }
162 if (count > 0 && !quiet)
163 log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name.c_str(), proc->name.c_str());
164 total_count += count;
165 }
166
167 struct ProcCleanPass : public Pass {
168 ProcCleanPass() : Pass("proc_clean", "remove empty parts of processes") { }
169 void help() YS_OVERRIDE
170 {
171 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
172 log("\n");
173 log(" proc_clean [options] [selection]\n");
174 log("\n");
175 log(" -quiet\n");
176 log(" do not print any messages.\n");
177 log("\n");
178 log("This pass removes empty parts of processes and ultimately removes a process\n");
179 log("if it contains only empty structures.\n");
180 log("\n");
181 }
182 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
183 {
184 int total_count = 0;
185 bool quiet = false;
186
187 if (find(args.begin(), args.end(), "-quiet") == args.end())
188 log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
189
190 size_t argidx;
191 for (argidx = 1; argidx < args.size(); argidx++)
192 {
193 if (args[argidx] == "-quiet") {
194 quiet = true;
195 continue;
196 }
197 }
198 extra_args(args, argidx, design);
199
200 for (auto mod : design->modules()) {
201 std::vector<RTLIL::IdString> delme;
202 if (!design->selected(mod))
203 continue;
204 for (auto &proc_it : mod->processes) {
205 if (!design->selected(mod, proc_it.second))
206 continue;
207 proc_clean(mod, proc_it.second, total_count, quiet);
208 if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
209 proc_it.second->root_case.actions.size() == 0) {
210 if (!quiet)
211 log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
212 delme.push_back(proc_it.first);
213 }
214 }
215 for (auto &id : delme) {
216 delete mod->processes[id];
217 mod->processes.erase(id);
218 }
219 }
220
221 if (!quiet)
222 log("Cleaned up %d empty switch%s.\n", total_count, total_count == 1 ? "" : "es");
223 }
224 } ProcCleanPass;
225
226 PRIVATE_NAMESPACE_END