Merge branch 'eddie/abc9_refactor' into xaig_dff
[yosys.git] / passes / proc / proc_clean.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/log.h"
22 #include <stdlib.h>
23 #include <stdio.h>
24
25 YOSYS_NAMESPACE_BEGIN
26 extern void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth);
27 YOSYS_NAMESPACE_END
28
29 USING_YOSYS_NAMESPACE
30 PRIVATE_NAMESPACE_BEGIN
31
32 void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
33 {
34 if (sw->signal.size() > 0 && sw->signal.is_fully_const())
35 {
36 int found_matching_case_idx = -1;
37 for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)
38 {
39 RTLIL::CaseRule *cs = sw->cases[i];
40 if (cs->compare.size() == 0)
41 break;
42 for (int j = 0; j < int(cs->compare.size()); j++) {
43 RTLIL::SigSpec &val = cs->compare[j];
44 if (!val.is_fully_const())
45 continue;
46 if (val == sw->signal) {
47 cs->compare.clear();
48 found_matching_case_idx = i;
49 break;
50 } else
51 cs->compare.erase(cs->compare.begin()+(j--));
52 }
53 if (cs->compare.size() == 0 && found_matching_case_idx < 0) {
54 sw->cases.erase(sw->cases.begin()+(i--));
55 delete cs;
56 }
57 }
58 while (found_matching_case_idx >= 0 && int(sw->cases.size()) > found_matching_case_idx+1) {
59 delete sw->cases.back();
60 sw->cases.pop_back();
61 }
62 if (found_matching_case_idx == 0)
63 sw->signal = RTLIL::SigSpec();
64 }
65
66 if (parent->switches.front() == sw && sw->cases.size() == 1 &&
67 (sw->signal.size() == 0 || sw->cases[0]->compare.empty()))
68 {
69 did_something = true;
70 for (auto &action : sw->cases[0]->actions)
71 parent->actions.push_back(action);
72 for (auto sw2 : sw->cases[0]->switches)
73 parent->switches.push_back(sw2);
74 sw->cases[0]->switches.clear();
75 delete sw->cases[0];
76 sw->cases.clear();
77 }
78 else
79 {
80 bool all_fully_def = true;
81 for (auto cs : sw->cases)
82 {
83 if (max_depth != 0)
84 proc_clean_case(cs, did_something, count, max_depth-1);
85 int size = 0;
86 for (auto cmp : cs->compare)
87 {
88 size += cmp.size();
89 if (!cmp.is_fully_def())
90 all_fully_def = false;
91 }
92 if (sw->signal.size() != size)
93 all_fully_def = false;
94 }
95 if (all_fully_def)
96 {
97 for (auto cs = sw->cases.begin(); cs != sw->cases.end();)
98 {
99 if ((*cs)->empty())
100 {
101 did_something = true;
102 delete *cs;
103 cs = sw->cases.erase(cs);
104 }
105 else ++cs;
106 }
107 }
108 else
109 {
110 while (!sw->cases.empty() && sw->cases.back()->empty())
111 {
112 did_something = true;
113 delete sw->cases.back();
114 sw->cases.pop_back();
115 }
116 }
117 }
118 }
119
120 PRIVATE_NAMESPACE_END
121 YOSYS_NAMESPACE_BEGIN
122
123 void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int max_depth)
124 {
125 for (size_t i = 0; i < cs->actions.size(); i++) {
126 if (cs->actions[i].first.size() == 0) {
127 did_something = true;
128 cs->actions.erase(cs->actions.begin() + (i--));
129 }
130 }
131 for (size_t i = 0; i < cs->switches.size(); i++) {
132 RTLIL::SwitchRule *sw = cs->switches[i];
133 if (sw->empty()) {
134 cs->switches.erase(cs->switches.begin() + (i--));
135 did_something = true;
136 delete sw;
137 count++;
138 } else if (max_depth != 0)
139 proc_clean_switch(sw, cs, did_something, count, max_depth-1);
140 }
141 }
142
143 YOSYS_NAMESPACE_END
144 PRIVATE_NAMESPACE_BEGIN
145
146 void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool quiet)
147 {
148 int count = 0;
149 bool did_something = true;
150 for (size_t i = 0; i < proc->syncs.size(); i++) {
151 for (size_t j = 0; j < proc->syncs[i]->actions.size(); j++)
152 if (proc->syncs[i]->actions[j].first.size() == 0)
153 proc->syncs[i]->actions.erase(proc->syncs[i]->actions.begin() + (j--));
154 if (proc->syncs[i]->actions.size() == 0) {
155 delete proc->syncs[i];
156 proc->syncs.erase(proc->syncs.begin() + (i--));
157 }
158 }
159 while (did_something) {
160 did_something = false;
161 proc_clean_case(&proc->root_case, did_something, count, -1);
162 }
163 if (count > 0 && !quiet)
164 log("Found and cleaned up %d empty switch%s in `%s.%s'.\n", count, count == 1 ? "" : "es", mod->name.c_str(), proc->name.c_str());
165 total_count += count;
166 }
167
168 struct ProcCleanPass : public Pass {
169 ProcCleanPass() : Pass("proc_clean", "remove empty parts of processes") { }
170 void help() YS_OVERRIDE
171 {
172 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
173 log("\n");
174 log(" proc_clean [options] [selection]\n");
175 log("\n");
176 log(" -quiet\n");
177 log(" do not print any messages.\n");
178 log("\n");
179 log("This pass removes empty parts of processes and ultimately removes a process\n");
180 log("if it contains only empty structures.\n");
181 log("\n");
182 }
183 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
184 {
185 int total_count = 0;
186 bool quiet = false;
187
188 if (find(args.begin(), args.end(), "-quiet") == args.end())
189 log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
190
191 size_t argidx;
192 for (argidx = 1; argidx < args.size(); argidx++)
193 {
194 if (args[argidx] == "-quiet") {
195 quiet = true;
196 continue;
197 }
198 }
199 extra_args(args, argidx, design);
200
201 for (auto mod : design->modules()) {
202 std::vector<RTLIL::IdString> delme;
203 if (!design->selected(mod))
204 continue;
205 for (auto &proc_it : mod->processes) {
206 if (!design->selected(mod, proc_it.second))
207 continue;
208 proc_clean(mod, proc_it.second, total_count, quiet);
209 if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 &&
210 proc_it.second->root_case.actions.size() == 0) {
211 if (!quiet)
212 log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str());
213 delme.push_back(proc_it.first);
214 }
215 }
216 for (auto &id : delme) {
217 delete mod->processes[id];
218 mod->processes.erase(id);
219 }
220 }
221
222 if (!quiet)
223 log("Cleaned up %d empty switch%s.\n", total_count, total_count == 1 ? "" : "es");
224 }
225 } ProcCleanPass;
226
227 PRIVATE_NAMESPACE_END