passes/proc/proc_dff.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/sigtools.h"
  22 #include "kernel/consteval.h"
  23 #include "kernel/log.h"
  24 #include <sstream>
  25 #include <stdlib.h>
  26 #include <stdio.h>
  27
  28 USING_YOSYS_NAMESPACE
  29 PRIVATE_NAMESPACE_BEGIN
  30
  31 RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
  32 {
  33         RTLIL::SigSpec lvalue;
  34
  35         for (auto sync : proc->syncs)
  36         for (auto &action : sync->actions)
  37                 if (action.first.size() > 0) {
  38                         lvalue = action.first;
  39                         lvalue.sort_and_unify();
  40                         break;
  41                 }
  42
  43         for (auto sync : proc->syncs) {
  44                 RTLIL::SigSpec this_lvalue;
  45                 for (auto &action : sync->actions)
  46                         this_lvalue.append(action.first);
  47                 this_lvalue.sort_and_unify();
  48                 RTLIL::SigSpec common_sig = this_lvalue.extract(lvalue);
  49                 if (common_sig.size() > 0)
  50                         lvalue = common_sig;
  51         }
  52
  53         return lvalue;
  54 }
  55
  56 void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
  57                 std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> &async_rules, RTLIL::Process *proc)
  58 {
  59         RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
  60         RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());
  61
  62         for (auto &it : async_rules)
  63         {
  64                 RTLIL::SigSpec sync_value = it.first;
  65                 RTLIL::SigSpec sync_value_inv;
  66                 RTLIL::SigSpec sync_high_signals;
  67                 RTLIL::SigSpec sync_low_signals;
  68
  69                 for (auto &it2 : it.second)
  70                         if (it2->type == RTLIL::SyncType::ST0)
  71                                 sync_low_signals.append(it2->signal);
  72                         else if (it2->type == RTLIL::SyncType::ST1)
  73                                 sync_high_signals.append(it2->signal);
  74                         else
  75                                 log_abort();
  76
  77                 if (sync_low_signals.size() > 1) {
  78                         RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
  79                         cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
  80                         cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
  81                         cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
  82                         cell->setPort(ID::A, sync_low_signals);
  83                         cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
  84                 }
  85
  86                 if (sync_low_signals.size() > 0) {
  87                         RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not));
  88                         cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
  89                         cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
  90                         cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
  91                         cell->setPort(ID::A, sync_low_signals);
  92                         cell->setPort(ID::Y, mod->addWire(NEW_ID));
  93                         sync_high_signals.append(cell->getPort(ID::Y));
  94                 }
  95
  96                 if (sync_high_signals.size() > 1) {
  97                         RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
  98                         cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
  99                         cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size());
 100                         cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
 101                         cell->setPort(ID::A, sync_high_signals);
 102                         cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
 103                 }
 104
 105                 RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not));
 106                 inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
 107                 inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size());
 108                 inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size());
 109                 inv_cell->setPort(ID::A, sync_value);
 110                 inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
 111
 112                 RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux));
 113                 mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
 114                 mux_set_cell->setPort(ID::A, sig_sr_set);
 115                 mux_set_cell->setPort(ID::B, sync_value);
 116                 mux_set_cell->setPort(ID::S, sync_high_signals);
 117                 mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
 118
 119                 RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux));
 120                 mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
 121                 mux_clr_cell->setPort(ID::A, sig_sr_clr);
 122                 mux_clr_cell->setPort(ID::B, sync_value_inv);
 123                 mux_clr_cell->setPort(ID::S, sync_high_signals);
 124                 mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
 125         }
 126
 127         std::stringstream sstr;
 128         sstr << "$procdff$" << (autoidx++);
 129
 130         RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
 131         cell->attributes = proc->attributes;
 132         cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
 133         cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
 134         cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
 135         cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
 136         cell->setPort(ID::D, sig_d);
 137         cell->setPort(ID::Q, sig_q);
 138         cell->setPort(ID::CLK, clk);
 139         cell->setPort(ID::SET, sig_sr_set);
 140         cell->setPort(ID::CLR, sig_sr_clr);
 141
 142         log("  created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
 143                         cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
 144 }
 145
 146 void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_out,
 147                 bool clk_polarity, bool set_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec set, RTLIL::Process *proc)
 148 {
 149         std::stringstream sstr;
 150         sstr << "$procdff$" << (autoidx++);
 151
 152         RTLIL::SigSpec sig_set_inv = mod->addWire(NEW_ID, sig_in.size());
 153         RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
 154         RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());
 155
 156         RTLIL::Cell *inv_set = mod->addCell(NEW_ID, ID($not));
 157         inv_set->parameters[ID::A_SIGNED] = RTLIL::Const(0);
 158         inv_set->parameters[ID::A_WIDTH] = RTLIL::Const(sig_in.size());
 159         inv_set->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_in.size());
 160         inv_set->setPort(ID::A, sig_set);
 161         inv_set->setPort(ID::Y, sig_set_inv);
 162
 163         RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, ID($mux));
 164         mux_sr_set->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
 165         mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
 166         mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set);
 167         mux_sr_set->setPort(ID::Y, sig_sr_set);
 168         mux_sr_set->setPort(ID::S, set);
 169
 170         RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, ID($mux));
 171         mux_sr_clr->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
 172         mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
 173         mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv);
 174         mux_sr_clr->setPort(ID::Y, sig_sr_clr);
 175         mux_sr_clr->setPort(ID::S, set);
 176
 177         RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
 178         cell->attributes = proc->attributes;
 179         cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
 180         cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
 181         cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
 182         cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
 183         cell->setPort(ID::D, sig_in);
 184         cell->setPort(ID::Q, sig_out);
 185         cell->setPort(ID::CLK, clk);
 186         cell->setPort(ID::SET, sig_sr_set);
 187         cell->setPort(ID::CLR, sig_sr_clr);
 188
 189         log("  created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
 190                         clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
 191 }
 192
 193 void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RTLIL::SigSpec sig_out,
 194                 bool clk_polarity, bool arst_polarity, RTLIL::SigSpec clk, RTLIL::SigSpec *arst, RTLIL::Process *proc)
 195 {
 196         std::stringstream sstr;
 197         sstr << "$procdff$" << (autoidx++);
 198
 199         RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
 200         cell->attributes = proc->attributes;
 201
 202         cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
 203         if (arst) {
 204                 cell->parameters[ID::ARST_POLARITY] = RTLIL::Const(arst_polarity, 1);
 205                 cell->parameters[ID::ARST_VALUE] = val_rst;
 206         }
 207         if (!clk.empty()) {
 208                 cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
 209         }
 210
 211         cell->setPort(ID::D, sig_in);
 212         cell->setPort(ID::Q, sig_out);
 213         if (arst)
 214                 cell->setPort(ID::ARST, *arst);
 215         if (!clk.empty())
 216                 cell->setPort(ID::CLK, clk);
 217
 218         if (!clk.empty())
 219                 log("  created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
 220         else
 221                 log("  created %s cell `%s' with global clock", cell->type.c_str(), cell->name.c_str());
 222         if (arst)
 223                 log(" and %s level reset", arst_polarity ? "positive" : "negative");
 224         log(".\n");
 225 }
 226
 227 void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 228 {
 229         while (1)
 230         {
 231                 RTLIL::SigSpec sig = find_any_lvalue(proc);
 232                 bool free_sync_level = false;
 233
 234                 if (sig.size() == 0)
 235                         break;
 236
 237                 log("Creating register for signal `%s.%s' using process `%s.%s'.\n",
 238                                 mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());
 239
 240                 RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 241                 RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 242                 RTLIL::SyncRule *sync_level = NULL;
 243                 RTLIL::SyncRule *sync_edge = NULL;
 244                 RTLIL::SyncRule *sync_always = NULL;
 245                 bool global_clock = false;
 246
 247                 std::map<RTLIL::SigSpec, std::set<RTLIL::SyncRule*>> many_async_rules;
 248
 249                 for (auto sync : proc->syncs)
 250                 for (auto &action : sync->actions)
 251                 {
 252                         if (action.first.extract(sig).size() == 0)
 253                                 continue;
 254
 255                         if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
 256                                 if (sync_level != NULL && sync_level != sync) {
 257                                         // log_error("Multiple level sensitive events found for this signal!\n");
 258                                         many_async_rules[rstval].insert(sync_level);
 259                                         rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 260                                 }
 261                                 rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 262                                 sig.replace(action.first, action.second, &rstval);
 263                                 sync_level = sync;
 264                         }
 265                         else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
 266                                 if (sync_edge != NULL && sync_edge != sync)
 267                                         log_error("Multiple edge sensitive events found for this signal!\n");
 268                                 sig.replace(action.first, action.second, &insig);
 269                                 sync_edge = sync;
 270                         }
 271                         else if (sync->type == RTLIL::SyncType::STa) {
 272                                 if (sync_always != NULL && sync_always != sync)
 273                                         log_error("Multiple always events found for this signal!\n");
 274                                 sig.replace(action.first, action.second, &insig);
 275                                 sync_always = sync;
 276                         }
 277                         else if (sync->type == RTLIL::SyncType::STg) {
 278                                 sig.replace(action.first, action.second, &insig);
 279                                 global_clock = true;
 280                         }
 281                         else {
 282                                 log_error("Event with any-edge sensitivity found for this signal!\n");
 283                         }
 284
 285                         action.first.remove2(sig, &action.second);
 286                 }
 287
 288                 if (many_async_rules.size() > 0)
 289                 {
 290                         many_async_rules[rstval].insert(sync_level);
 291                         if (many_async_rules.size() == 1)
 292                         {
 293                                 sync_level = new RTLIL::SyncRule;
 294                                 sync_level->type = RTLIL::SyncType::ST1;
 295                                 sync_level->signal = mod->addWire(NEW_ID);
 296                                 sync_level->actions.push_back(RTLIL::SigSig(sig, rstval));
 297                                 free_sync_level = true;
 298
 299                                 RTLIL::SigSpec inputs, compare;
 300                                 for (auto &it : many_async_rules[rstval]) {
 301                                         inputs.append(it->signal);
 302                                         compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);
 303                                 }
 304                                 log_assert(inputs.size() == compare.size());
 305
 306                                 RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne));
 307                                 cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1);
 308                                 cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1);
 309                                 cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size());
 310                                 cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size());
 311                                 cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
 312                                 cell->setPort(ID::A, inputs);
 313                                 cell->setPort(ID::B, compare);
 314                                 cell->setPort(ID::Y, sync_level->signal);
 315
 316                                 many_async_rules.clear();
 317                         }
 318                         else
 319                         {
 320                                 rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 321                                 sync_level = NULL;
 322                         }
 323                 }
 324
 325                 SigSpec sig_q = sig;
 326                 ce.assign_map.apply(insig);
 327                 ce.assign_map.apply(rstval);
 328                 ce.assign_map.apply(sig);
 329
 330                 if (rstval == sig) {
 331                         rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
 332                         sync_level = NULL;
 333                 }
 334
 335                 if (sync_always) {
 336                         if (sync_edge || sync_level || many_async_rules.size() > 0)
 337                                 log_error("Mixed always event with edge and/or level sensitive events!\n");
 338                         log("  created direct connection (no actual register cell created).\n");
 339                         mod->connect(RTLIL::SigSig(sig, insig));
 340                         continue;
 341                 }
 342
 343                 if (!sync_edge && !global_clock)
 344                         log_error("Missing edge-sensitive event for this signal!\n");
 345
 346                 if (many_async_rules.size() > 0)
 347                 {
 348                         log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
 349                         gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc);
 350                 }
 351                 else if (!rstval.is_fully_const() && !ce.eval(rstval))
 352                 {
 353                         log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
 354                         gen_dffsr(mod, insig, rstval, sig_q,
 355                                         sync_edge->type == RTLIL::SyncType::STp,
 356                                         sync_level && sync_level->type == RTLIL::SyncType::ST1,
 357                                         sync_edge->signal, sync_level->signal, proc);
 358                 }
 359                 else
 360                         gen_dff(mod, insig, rstval.as_const(), sig_q,
 361                                         sync_edge && sync_edge->type == RTLIL::SyncType::STp,
 362                                         sync_level && sync_level->type == RTLIL::SyncType::ST1,
 363                                         sync_edge ? sync_edge->signal : SigSpec(),
 364                                         sync_level ? &sync_level->signal : NULL, proc);
 365
 366                 if (free_sync_level)
 367                         delete sync_level;
 368         }
 369 }
 370
 371 struct ProcDffPass : public Pass {
 372         ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { }
 373         void help() override
 374         {
 375                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 376                 log("\n");
 377                 log("    proc_dff [selection]\n");
 378                 log("\n");
 379                 log("This pass identifies flip-flops in the processes and converts them to\n");
 380                 log("d-type flip-flop cells.\n");
 381                 log("\n");
 382         }
 383         void execute(std::vector<std::string> args, RTLIL::Design *design) override
 384         {
 385                 log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
 386
 387                 extra_args(args, 1, design);
 388
 389                 for (auto mod : design->modules())
 390                         if (design->selected(mod)) {
 391                                 ConstEval ce(mod);
 392                                 for (auto &proc_it : mod->processes)
 393                                         if (design->selected(mod, proc_it.second))
 394                                                 proc_dff(mod, proc_it.second, ce);
 395                         }
 396         }
 397 } ProcDffPass;
 398
 399 PRIVATE_NAMESPACE_END