2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/sigtools.h"
22 #include "kernel/consteval.h"
23 #include "kernel/log.h"
29 static RTLIL::SigSpec
find_any_lvalue(const RTLIL::Process
*proc
)
31 RTLIL::SigSpec lvalue
;
33 for (auto sync
: proc
->syncs
)
34 for (auto &action
: sync
->actions
)
35 if (action
.first
.width
> 0) {
36 lvalue
= action
.first
;
37 lvalue
.sort_and_unify();
41 for (auto sync
: proc
->syncs
) {
42 RTLIL::SigSpec this_lvalue
;
43 for (auto &action
: sync
->actions
)
44 this_lvalue
.append(action
.first
);
45 this_lvalue
.sort_and_unify();
46 RTLIL::SigSpec common_sig
= this_lvalue
.extract(lvalue
);
47 if (common_sig
.width
> 0)
54 static void gen_dffsr(RTLIL::Module
*mod
, RTLIL::SigSpec sig_in
, RTLIL::SigSpec sig_set
, RTLIL::SigSpec sig_out
,
55 bool clk_polarity
, bool set_polarity
, RTLIL::SigSpec clk
, RTLIL::SigSpec set
, RTLIL::Process
*proc
)
57 std::stringstream sstr
;
58 sstr
<< "$procdff$" << (RTLIL::autoidx
++);
60 RTLIL::SigSpec sig_set_inv
= NEW_WIRE(mod
, sig_in
.width
);
61 RTLIL::SigSpec sig_sr_set
= NEW_WIRE(mod
, sig_in
.width
);
62 RTLIL::SigSpec sig_sr_clr
= NEW_WIRE(mod
, sig_in
.width
);
64 RTLIL::Cell
*inv_set
= new RTLIL::Cell
;
65 inv_set
->name
= NEW_ID
;
66 inv_set
->type
= "$not";
67 inv_set
->parameters
["\\A_WIDTH"] = RTLIL::Const(sig_in
.width
);
68 inv_set
->parameters
["\\Y_WIDTH"] = RTLIL::Const(sig_in
.width
);
69 inv_set
->connections
["\\A"] = sig_set
;
70 inv_set
->connections
["\\Y"] = sig_set_inv
;
73 RTLIL::Cell
*mux_sr_set
= new RTLIL::Cell
;
74 mux_sr_set
->name
= NEW_ID
;
75 mux_sr_set
->type
= "$mux";
76 mux_sr_set
->parameters
["\\WIDTH"] = RTLIL::Const(sig_in
.width
);
77 mux_sr_set
->connections
[set_polarity
? "\\A" : "\\B"] = RTLIL::Const(0, sig_in
.width
);
78 mux_sr_set
->connections
[set_polarity
? "\\B" : "\\A"] = sig_set
;
79 mux_sr_set
->connections
["\\Y"] = sig_sr_set
;
80 mux_sr_set
->connections
["\\S"] = set
;
83 RTLIL::Cell
*mux_sr_clr
= new RTLIL::Cell
;
84 mux_sr_clr
->name
= NEW_ID
;
85 mux_sr_clr
->type
= "$mux";
86 mux_sr_clr
->parameters
["\\WIDTH"] = RTLIL::Const(sig_in
.width
);
87 mux_sr_clr
->connections
[set_polarity
? "\\A" : "\\B"] = RTLIL::Const(0, sig_in
.width
);
88 mux_sr_clr
->connections
[set_polarity
? "\\B" : "\\A"] = sig_set_inv
;
89 mux_sr_clr
->connections
["\\Y"] = sig_sr_clr
;
90 mux_sr_clr
->connections
["\\S"] = set
;
93 RTLIL::Cell
*cell
= new RTLIL::Cell
;
94 cell
->name
= sstr
.str();
95 cell
->type
= "$dffsr";
96 cell
->attributes
= proc
->attributes
;
99 cell
->parameters
["\\WIDTH"] = RTLIL::Const(sig_in
.width
);
100 cell
->parameters
["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity
, 1);
101 cell
->parameters
["\\SET_POLARITY"] = RTLIL::Const(true, 1);
102 cell
->parameters
["\\CLR_POLARITY"] = RTLIL::Const(true, 1);
104 cell
->connections
["\\D"] = sig_in
;
105 cell
->connections
["\\Q"] = sig_out
;
106 cell
->connections
["\\CLK"] = clk
;
107 cell
->connections
["\\SET"] = sig_sr_set
;
108 cell
->connections
["\\CLR"] = sig_sr_clr
;
110 log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell
->type
.c_str(), cell
->name
.c_str(),
111 clk_polarity
? "positive" : "negative", set_polarity
? "positive" : "negative");
114 static void gen_dff(RTLIL::Module
*mod
, RTLIL::SigSpec sig_in
, RTLIL::Const val_rst
, RTLIL::SigSpec sig_out
,
115 bool clk_polarity
, bool arst_polarity
, RTLIL::SigSpec clk
, RTLIL::SigSpec
*arst
, RTLIL::Process
*proc
)
117 std::stringstream sstr
;
118 sstr
<< "$procdff$" << (RTLIL::autoidx
++);
120 RTLIL::Cell
*cell
= new RTLIL::Cell
;
121 cell
->name
= sstr
.str();
122 cell
->type
= arst
? "$adff" : "$dff";
123 cell
->attributes
= proc
->attributes
;
124 mod
->cells
[cell
->name
] = cell
;
126 cell
->parameters
["\\WIDTH"] = RTLIL::Const(sig_in
.width
);
128 cell
->parameters
["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity
, 1);
129 cell
->parameters
["\\ARST_VALUE"] = val_rst
;
131 cell
->parameters
["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity
, 1);
133 cell
->connections
["\\D"] = sig_in
;
134 cell
->connections
["\\Q"] = sig_out
;
136 cell
->connections
["\\ARST"] = *arst
;
137 cell
->connections
["\\CLK"] = clk
;
139 log(" created %s cell `%s' with %s edge clock", cell
->type
.c_str(), cell
->name
.c_str(), clk_polarity
? "positive" : "negative");
141 log(" and %s level reset", arst_polarity
? "positive" : "negative");
145 static void proc_dff(RTLIL::Module
*mod
, RTLIL::Process
*proc
, ConstEval
&ce
)
149 RTLIL::SigSpec sig
= find_any_lvalue(proc
);
150 bool free_sync_level
= false;
155 log("Creating register for signal `%s.%s' using process `%s.%s'.\n",
156 mod
->name
.c_str(), log_signal(sig
), mod
->name
.c_str(), proc
->name
.c_str());
158 RTLIL::SigSpec insig
= RTLIL::SigSpec(RTLIL::State::Sz
, sig
.width
);
159 RTLIL::SigSpec rstval
= RTLIL::SigSpec(RTLIL::State::Sz
, sig
.width
);
160 RTLIL::SyncRule
*sync_level
= NULL
;
161 RTLIL::SyncRule
*sync_edge
= NULL
;
162 RTLIL::SyncRule
*sync_always
= NULL
;
164 std::map
<RTLIL::SigSpec
, std::set
<RTLIL::SyncRule
*>> many_async_rules
;
166 for (auto sync
: proc
->syncs
)
167 for (auto &action
: sync
->actions
)
169 if (action
.first
.extract(sig
).width
== 0)
172 if (sync
->type
== RTLIL::SyncType::ST0
|| sync
->type
== RTLIL::SyncType::ST1
) {
173 if (sync_level
!= NULL
&& sync_level
!= sync
) {
174 // log_error("Multiple level sensitive events found for this signal!\n");
175 many_async_rules
[rstval
].insert(sync_level
);
176 rstval
= RTLIL::SigSpec(RTLIL::State::Sz
, sig
.width
);
178 rstval
= RTLIL::SigSpec(RTLIL::State::Sz
, sig
.width
);
179 sig
.replace(action
.first
, action
.second
, &rstval
);
182 else if (sync
->type
== RTLIL::SyncType::STp
|| sync
->type
== RTLIL::SyncType::STn
) {
183 if (sync_edge
!= NULL
&& sync_edge
!= sync
)
184 log_error("Multiple edge sensitive events found for this signal!\n");
185 sig
.replace(action
.first
, action
.second
, &insig
);
188 else if (sync
->type
== RTLIL::SyncType::STa
) {
189 if (sync_always
!= NULL
&& sync_always
!= sync
)
190 log_error("Multiple always events found for this signal!\n");
191 sig
.replace(action
.first
, action
.second
, &insig
);
195 log_error("Event with any-edge sensitivity found for this signal!\n");
198 action
.first
.remove2(sig
, &action
.second
);
201 if (many_async_rules
.size() > 0)
203 many_async_rules
[rstval
].insert(sync_level
);
204 if (many_async_rules
.size() == 1)
206 sync_level
= new RTLIL::SyncRule
;
207 sync_level
->type
= RTLIL::SyncType::ST1
;
208 sync_level
->signal
= NEW_WIRE(mod
, 1);
209 sync_level
->actions
.push_back(RTLIL::SigSig(sig
, rstval
));
210 free_sync_level
= true;
212 RTLIL::SigSpec inputs
, compare
;
213 for (auto &it
: many_async_rules
[rstval
]) {
214 inputs
.append(it
->signal
);
215 compare
.append(it
->type
== RTLIL::SyncType::ST0
? RTLIL::State::S1
: RTLIL::State::S0
);
217 assert(inputs
.width
== compare
.width
);
219 RTLIL::Cell
*cell
= new RTLIL::Cell
;
222 cell
->parameters
["\\A_SIGNED"] = RTLIL::Const(false, 1);
223 cell
->parameters
["\\B_SIGNED"] = RTLIL::Const(false, 1);
224 cell
->parameters
["\\A_WIDTH"] = RTLIL::Const(inputs
.width
);
225 cell
->parameters
["\\B_WIDTH"] = RTLIL::Const(inputs
.width
);
226 cell
->parameters
["\\Y_WIDTH"] = RTLIL::Const(1);
227 cell
->connections
["\\A"] = inputs
;
228 cell
->connections
["\\B"] = compare
;
229 cell
->connections
["\\Y"] = sync_level
->signal
;
232 many_async_rules
.clear();
236 rstval
= RTLIL::SigSpec(RTLIL::State::Sz
, sig
.width
);
241 ce
.assign_map
.apply(insig
);
242 ce
.assign_map
.apply(rstval
);
243 ce
.assign_map
.apply(sig
);
250 if (sync_edge
|| sync_level
|| many_async_rules
.size() > 0)
251 log_error("Mixed always event with edge and/or level sensitive events!\n");
252 log(" created direct connection (no actual register cell created).\n");
253 mod
->connections
.push_back(RTLIL::SigSig(sig
, insig
));
258 log_error("Missing edge-sensitive event for this signal!\n");
260 if (many_async_rules
.size() > 0)
262 log_error("Multiple async resets for different values (feature under construction)!\n");
264 else if (!rstval
.is_fully_const() && !ce
.eval(rstval
))
266 log("WARNING: Async reset value `%s' is not constant!\n", log_signal(rstval
));
267 gen_dffsr(mod
, insig
, rstval
, sig
,
268 sync_edge
->type
== RTLIL::SyncType::STp
,
269 sync_level
&& sync_level
->type
== RTLIL::SyncType::ST1
,
270 sync_edge
->signal
, sync_level
->signal
, proc
);
273 gen_dff(mod
, insig
, rstval
.chunks
[0].data
, sig
,
274 sync_edge
->type
== RTLIL::SyncType::STp
,
275 sync_level
&& sync_level
->type
== RTLIL::SyncType::ST1
,
276 sync_edge
->signal
, sync_level
? &sync_level
->signal
: NULL
, proc
);
283 struct ProcDffPass
: public Pass
{
284 ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { }
287 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
289 log(" proc_dff [selection]\n");
291 log("This pass identifies flip-flops in the processes and converts them to\n");
292 log("d-type flip-flop cells.\n");
295 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
297 log_header("Executing PROC_DFF pass (convert process syncs to FFs).\n");
299 extra_args(args
, 1, design
);
301 for (auto &mod_it
: design
->modules
)
302 if (design
->selected(mod_it
.second
)) {
303 ConstEval
ce(mod_it
.second
);
304 for (auto &proc_it
: mod_it
.second
->processes
)
305 if (design
->selected(mod_it
.second
, proc_it
.second
))
306 proc_dff(mod_it
.second
, proc_it
.second
, ce
);