Added "proc_arst -global_arst" feature
[yosys.git] / passes / proc / proc_rmdead.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/bitpattern.h"
22 #include "kernel/log.h"
23 #include <sstream>
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <assert.h>
27 #include <set>
28
29 static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
30 {
31 BitPatternPool pool(sw->signal);
32
33 for (size_t i = 0; i < sw->cases.size(); i++)
34 {
35 bool is_default = sw->cases[i]->compare.size() == 0 && !pool.empty();
36
37 for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
38 RTLIL::SigSpec sig = sw->cases[i]->compare[j];
39 if (!sig.is_fully_const())
40 continue;
41 if (!pool.take(sig))
42 sw->cases[i]->compare.erase(sw->cases[i]->compare.begin() + (j--));
43 }
44
45 if (!is_default) {
46 if (sw->cases[i]->compare.size() == 0) {
47 delete sw->cases[i];
48 sw->cases.erase(sw->cases.begin() + (i--));
49 counter++;
50 continue;
51 }
52 if (pool.empty())
53 sw->cases[i]->compare.clear();
54 }
55
56 for (auto switch_it : sw->cases[i]->switches)
57 proc_rmdead(switch_it, counter);
58
59 if (is_default)
60 pool.take_all();
61 }
62 }
63
64 struct ProcRmdeadPass : public Pass {
65 ProcRmdeadPass() : Pass("proc_rmdead", "eliminate dead trees in decision trees") { }
66 virtual void help()
67 {
68 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
69 log("\n");
70 log(" proc_rmdead [selection]\n");
71 log("\n");
72 log("This pass identifies unreachable branches in decision trees and removes them.\n");
73 log("\n");
74 }
75 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
76 {
77 log_header("Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
78
79 extra_args(args, 1, design);
80
81 int total_counter = 0;
82 for (auto &mod_it : design->modules) {
83 if (!design->selected(mod_it.second))
84 continue;
85 for (auto &proc_it : mod_it.second->processes) {
86 if (!design->selected(mod_it.second, proc_it.second))
87 continue;
88 int counter = 0;
89 for (auto switch_it : proc_it.second->root_case.switches)
90 proc_rmdead(switch_it, counter);
91 if (counter > 0)
92 log("Removed %d dead cases from process %s in module %s.\n", counter,
93 proc_it.first.c_str(), mod_it.first.c_str());
94 total_counter += counter;
95 }
96 }
97
98 log("Removed a total of %d dead cases.\n", total_counter);
99 }
100 } ProcRmdeadPass;
101