Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
[yosys.git] / passes / proc / proc_rmdead.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/bitpattern.h"
22 #include "kernel/log.h"
23 #include <sstream>
24 #include <stdlib.h>
25 #include <stdio.h>
26 #include <set>
27
28 static void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
29 {
30 BitPatternPool pool(sw->signal);
31
32 for (size_t i = 0; i < sw->cases.size(); i++)
33 {
34 bool is_default = SIZE(sw->cases[i]->compare) == 0 && (!pool.empty() || SIZE(sw->signal) == 0);
35
36 for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
37 RTLIL::SigSpec sig = sw->cases[i]->compare[j];
38 if (!sig.is_fully_const())
39 continue;
40 if (!pool.take(sig))
41 sw->cases[i]->compare.erase(sw->cases[i]->compare.begin() + (j--));
42 }
43
44 if (!is_default) {
45 if (sw->cases[i]->compare.size() == 0) {
46 delete sw->cases[i];
47 sw->cases.erase(sw->cases.begin() + (i--));
48 counter++;
49 continue;
50 }
51 if (pool.empty())
52 sw->cases[i]->compare.clear();
53 }
54
55 for (auto switch_it : sw->cases[i]->switches)
56 proc_rmdead(switch_it, counter);
57
58 if (is_default)
59 pool.take_all();
60 }
61 }
62
63 struct ProcRmdeadPass : public Pass {
64 ProcRmdeadPass() : Pass("proc_rmdead", "eliminate dead trees in decision trees") { }
65 virtual void help()
66 {
67 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
68 log("\n");
69 log(" proc_rmdead [selection]\n");
70 log("\n");
71 log("This pass identifies unreachable branches in decision trees and removes them.\n");
72 log("\n");
73 }
74 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
75 {
76 log_header("Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
77
78 extra_args(args, 1, design);
79
80 int total_counter = 0;
81 for (auto mod : design->modules()) {
82 if (!design->selected(mod))
83 continue;
84 for (auto &proc_it : mod->processes) {
85 if (!design->selected(mod, proc_it.second))
86 continue;
87 int counter = 0;
88 for (auto switch_it : proc_it.second->root_case.switches)
89 proc_rmdead(switch_it, counter);
90 if (counter > 0)
91 log("Removed %d dead cases from process %s in module %s.\n", counter,
92 proc_it.first.c_str(), log_id(mod));
93 total_counter += counter;
94 }
95 }
96
97 log("Removed a total of %d dead cases.\n", total_counter);
98 }
99 } ProcRmdeadPass;
100