passes/sat/async2sync.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct Async2syncPass : public Pass {
  27         Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { }
  28         void help() YS_OVERRIDE
  29         {
  30                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  31                 log("\n");
  32                 log("    async2sync [options] [selection]\n");
  33                 log("\n");
  34                 log("This command replaces async FF inputs with sync circuits emulating the same\n");
  35                 log("behavior for when the async signals are actually synchronized to the clock.\n");
  36                 log("\n");
  37                 log("This pass assumes negative hold time for the async FF inputs. For example when\n");
  38                 log("a reset deasserts with the clock edge, then the FF output will still drive the\n");
  39                 log("reset value in the next cycle regardless of the data-in value at the time of\n");
  40                 log("the clock edge.\n");
  41                 log("\n");
  42                 log("Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.\n");
  43                 log("\n");
  44         }
  45         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  46         {
  47                 // bool flag_noinit = false;
  48
  49                 log_header(design, "Executing ASYNC2SYNC pass.\n");
  50
  51                 size_t argidx;
  52                 for (argidx = 1; argidx < args.size(); argidx++)
  53                 {
  54                         // if (args[argidx] == "-noinit") {
  55                         //      flag_noinit = true;
  56                         //      continue;
  57                         // }
  58                         break;
  59                 }
  60                 extra_args(args, argidx, design);
  61
  62                 for (auto module : design->selected_modules())
  63                 {
  64                         SigMap sigmap(module);
  65                         dict<SigBit, State> initbits;
  66                         pool<SigBit> del_initbits;
  67
  68                         for (auto wire : module->wires())
  69                                 if (wire->attributes.count("\\init") > 0)
  70                                 {
  71                                         Const initval = wire->attributes.at("\\init");
  72                                         SigSpec initsig = sigmap(wire);
  73
  74                                         for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
  75                                                 if (initval[i] == State::S0 || initval[i] == State::S1)
  76                                                         initbits[initsig[i]] = initval[i];
  77                                 }
  78
  79                         for (auto cell : vector<Cell*>(module->selected_cells()))
  80                         {
  81                                 if (cell->type.in("$adff"))
  82                                 {
  83                                         // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
  84                                         bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool();
  85                                         Const arst_val = cell->parameters["\\ARST_VALUE"];
  86
  87                                         // SigSpec sig_clk = cell->getPort("\\CLK");
  88                                         SigSpec sig_arst = cell->getPort("\\ARST");
  89                                         SigSpec sig_d = cell->getPort("\\D");
  90                                         SigSpec sig_q = cell->getPort("\\Q");
  91
  92                                         log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
  93                                                         log_id(module), log_id(cell), log_id(cell->type),
  94                                                         log_signal(sig_arst), log_signal(sig_d), log_signal(sig_q));
  95
  96                                         Const init_val;
  97                                         for (int i = 0; i < GetSize(sig_q); i++) {
  98                                                 SigBit bit = sigmap(sig_q[i]);
  99                                                 init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
 100                                                 del_initbits.insert(bit);
 101                                         }
 102
 103                                         Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
 104                                         Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
 105                                         new_q->attributes["\\init"] = init_val;
 106
 107                                         if (arst_pol) {
 108                                                 module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
 109                                                 module->addMux(NEW_ID, new_q, arst_val, sig_arst, sig_q);
 110                                         } else {
 111                                                 module->addMux(NEW_ID, arst_val, sig_d, sig_arst, new_d);
 112                                                 module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
 113                                         }
 114
 115                                         cell->setPort("\\D", new_d);
 116                                         cell->setPort("\\Q", new_q);
 117                                         cell->unsetPort("\\ARST");
 118                                         cell->unsetParam("\\ARST_POLARITY");
 119                                         cell->unsetParam("\\ARST_VALUE");
 120                                         cell->type = "$dff";
 121                                         continue;
 122                                 }
 123
 124                                 if (cell->type.in("$dffsr"))
 125                                 {
 126                                         // bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
 127                                         bool set_pol = cell->parameters["\\SET_POLARITY"].as_bool();
 128                                         bool clr_pol = cell->parameters["\\CLR_POLARITY"].as_bool();
 129
 130                                         // SigSpec sig_clk = cell->getPort("\\CLK");
 131                                         SigSpec sig_set = cell->getPort("\\SET");
 132                                         SigSpec sig_clr = cell->getPort("\\CLR");
 133                                         SigSpec sig_d = cell->getPort("\\D");
 134                                         SigSpec sig_q = cell->getPort("\\Q");
 135
 136                                         log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
 137                                                         log_id(module), log_id(cell), log_id(cell->type),
 138                                                         log_signal(sig_set), log_signal(sig_clr), log_signal(sig_d), log_signal(sig_q));
 139
 140                                         Const init_val;
 141                                         for (int i = 0; i < GetSize(sig_q); i++) {
 142                                                 SigBit bit = sigmap(sig_q[i]);
 143                                                 init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
 144                                                 del_initbits.insert(bit);
 145                                         }
 146
 147                                         Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
 148                                         Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
 149                                         new_q->attributes["\\init"] = init_val;
 150
 151                                         if (!set_pol)
 152                                                 sig_set = module->Not(NEW_ID, sig_set);
 153
 154                                         if (clr_pol)
 155                                                 sig_clr = module->Not(NEW_ID, sig_clr);
 156
 157                                         SigSpec tmp = module->Or(NEW_ID, sig_d, sig_set);
 158                                         module->addAnd(NEW_ID, tmp, sig_clr, new_d);
 159
 160                                         tmp = module->Or(NEW_ID, new_q, sig_set);
 161                                         module->addAnd(NEW_ID, tmp, sig_clr, sig_q);
 162
 163                                         cell->setPort("\\D", new_d);
 164                                         cell->setPort("\\Q", new_q);
 165                                         cell->unsetPort("\\SET");
 166                                         cell->unsetPort("\\CLR");
 167                                         cell->unsetParam("\\SET_POLARITY");
 168                                         cell->unsetParam("\\CLR_POLARITY");
 169                                         cell->type = "$dff";
 170                                         continue;
 171                                 }
 172
 173                                 if (cell->type.in("$dlatch"))
 174                                 {
 175                                         bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool();
 176
 177                                         SigSpec sig_en = cell->getPort("\\EN");
 178                                         SigSpec sig_d = cell->getPort("\\D");
 179                                         SigSpec sig_q = cell->getPort("\\Q");
 180
 181                                         log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
 182                                                         log_id(module), log_id(cell), log_id(cell->type),
 183                                                         log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
 184
 185                                         Const init_val;
 186                                         for (int i = 0; i < GetSize(sig_q); i++) {
 187                                                 SigBit bit = sigmap(sig_q[i]);
 188                                                 init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
 189                                                 del_initbits.insert(bit);
 190                                         }
 191
 192                                         Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
 193                                         new_q->attributes["\\init"] = init_val;
 194
 195                                         if (en_pol) {
 196                                                 module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
 197                                         } else {
 198                                                 module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
 199                                         }
 200
 201                                         cell->setPort("\\Q", new_q);
 202                                         cell->unsetPort("\\EN");
 203                                         cell->unsetParam("\\EN_POLARITY");
 204                                         cell->type = "$ff";
 205                                         continue;
 206                                 }
 207                         }
 208
 209                         for (auto wire : module->wires())
 210                                 if (wire->attributes.count("\\init") > 0)
 211                                 {
 212                                         bool delete_initattr = true;
 213                                         Const initval = wire->attributes.at("\\init");
 214                                         SigSpec initsig = sigmap(wire);
 215
 216                                         for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
 217                                                 if (del_initbits.count(initsig[i]) > 0)
 218                                                         initval[i] = State::Sx;
 219                                                 else if (initval[i] != State::Sx)
 220                                                         delete_initattr = false;
 221
 222                                         if (delete_initattr)
 223                                                 wire->attributes.erase("\\init");
 224                                         else
 225                                                 wire->attributes.at("\\init") = initval;
 226                                 }
 227                 }
 228         }
 229 } Async2syncPass;
 230
 231 PRIVATE_NAMESPACE_END