passes/sat/clk2fflogic.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include "kernel/sigtools.h"
  22
  23 USING_YOSYS_NAMESPACE
  24 PRIVATE_NAMESPACE_BEGIN
  25
  26 struct Clk2fflogicPass : public Pass {
  27         Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { }
  28         virtual void help()
  29         {
  30                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  31                 log("\n");
  32                 log("    clk2fflogic [options] [selection]\n");
  33                 log("\n");
  34                 log("This command replaces clocked flip-flops with generic $ff cells that use the\n");
  35                 log("implicit global clock. This is useful for formal verification of designs with\n");
  36                 log("multiple clocks.\n");
  37                 log("\n");
  38         }
  39         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
  40         {
  41                 // bool flag_noinit = false;
  42
  43                 log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
  44
  45                 size_t argidx;
  46                 for (argidx = 1; argidx < args.size(); argidx++)
  47                 {
  48                         // if (args[argidx] == "-noinit") {
  49                         //      flag_noinit = true;
  50                         //      continue;
  51                         // }
  52                         break;
  53                 }
  54                 extra_args(args, argidx, design);
  55
  56                 for (auto module : design->selected_modules())
  57                 {
  58                         SigMap sigmap(module);
  59                         dict<SigBit, State> initbits;
  60                         pool<SigBit> del_initbits;
  61                         vector<Cell*> ffcells;
  62
  63                         for (auto wire : module->wires())
  64                                 if (wire->attributes.count("\\init") > 0)
  65                                 {
  66                                         Const initval = wire->attributes.at("\\init");
  67                                         SigSpec initsig = sigmap(wire);
  68
  69                                         for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
  70                                                 if (initval[i] == State::S0 || initval[i] == State::S1)
  71                                                         initbits[initsig[i]] = initval[i];
  72                                 }
  73
  74                         for (auto cell : module->selected_cells())
  75                                 if (cell->type.in("$dff"))
  76                                         ffcells.push_back(cell);
  77
  78                         for (auto cell : ffcells)
  79                         {
  80                                 if (cell->type == "$dff")
  81                                 {
  82                                         bool clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
  83
  84                                         SigSpec clk = cell->getPort("\\CLK");
  85                                         SigSpec past_clk = module->addWire(NEW_ID);
  86                                         module->addFf(NEW_ID, clk, past_clk);
  87
  88                                         SigSpec sig_d = cell->getPort("\\D");
  89                                         SigSpec sig_q = cell->getPort("\\Q");
  90
  91                                         log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
  92                                                         log_id(module), log_id(cell), log_id(cell->type),
  93                                                         log_signal(clk), log_signal(sig_d), log_signal(sig_q));
  94                                         module->remove(cell);
  95
  96                                         SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk},
  97                                                         clkpol ? SigSpec({State::S0, State::S1}) : SigSpec({State::S1, State::S0}));
  98
  99                                         Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d));
 100                                         Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
 101                                         module->addFf(NEW_ID, sig_d, past_d);
 102                                         module->addFf(NEW_ID, sig_q, past_q);
 103
 104                                         module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
 105
 106                                         Const initval;
 107                                         bool assign_initval = false;
 108                                         for (int i = 0; i < GetSize(sig_d); i++) {
 109                                                 SigBit qbit = sigmap(sig_q[i]);
 110                                                 if (initbits.count(qbit)) {
 111                                                         initval.bits.push_back(initbits.at(qbit));
 112                                                         del_initbits.insert(qbit);
 113                                                 } else
 114                                                         initval.bits.push_back(State::Sx);
 115                                                 if (initval.bits.back() != State::Sx)
 116                                                         assign_initval = true;
 117                                         }
 118
 119                                         if (assign_initval) {
 120                                                 past_d->attributes["\\init"] = initval;
 121                                                 past_q->attributes["\\init"] = initval;
 122                                         }
 123
 124                                         continue;
 125                                 }
 126
 127                                 log_abort();
 128                         }
 129
 130                         for (auto wire : module->wires())
 131                                 if (wire->attributes.count("\\init") > 0)
 132                                 {
 133                                         bool delete_initattr = true;
 134                                         Const initval = wire->attributes.at("\\init");
 135                                         SigSpec initsig = sigmap(wire);
 136
 137                                         for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
 138                                                 if (del_initbits.count(initsig[i]) > 0)
 139                                                         initval[i] = State::Sx;
 140                                                 else if (initval[i] != State::Sx)
 141                                                         delete_initattr = false;
 142
 143                                         if (delete_initattr)
 144                                                 wire->attributes.erase("\\init");
 145                                         else
 146                                                 wire->attributes.at("\\init") = initval;
 147                                 }
 148                 }
 149
 150         }
 151 } Clk2fflogicPass;
 152
 153 PRIVATE_NAMESPACE_END