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45011f70d1d6559a23d223265fe78dc9b3217670
[yosys.git]
/
passes
/
sat
/
example.v
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module example(a, y);
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input [15:0] a;
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output y;
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wire gt = a > 12345;
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wire lt = a < 12345;
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assign y = !gt && !lt;
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endmodule
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