passes/sat/example.v

   1
   2 module example001(a, y);
   3
   4 input [15:0] a;
   5 output y;
   6
   7 wire gt = a > 12345;
   8 wire lt = a < 12345;
   9 assign y = !gt && !lt;
  10
  11 endmodule
  12
  13 // ------------------------------------
  14
  15 module example002(a, y);
  16
  17 input [3:0] a;
  18 output y;
  19 reg [1:0] t1, t2;
  20
  21 always @* begin
  22         casex (a)
  23                 16'b1xxx:
  24                         t1 <= 1;
  25                 16'bx1xx:
  26                         t1 <= 2;
  27                 16'bxx1x:
  28                         t1 <= 3;
  29                 16'bxxx1:
  30                         t1 <= 4;
  31                 default:
  32                         t1 <= 0;
  33         endcase
  34         casex (a)
  35                 16'b1xxx:
  36                         t2 <= 1;
  37                 16'b01xx:
  38                         t2 <= 2;
  39                 16'b001x:
  40                         t2 <= 3;
  41                 16'b0001:
  42                         t2 <= 4;
  43                 default:
  44                         t2 <= 0;
  45         endcase
  46 end
  47
  48 assign y = t1 != t2;
  49
  50 endmodule
  51
  52 // ------------------------------------
  53
  54 module example003(a_shl, a_shr, a_sshl, a_sshr, sh, y_shl, y_shr, y_sshl, y_sshr);
  55
  56 input [7:0] a_shl, a_shr;
  57 input signed [7:0] a_sshl, a_sshr;
  58 input [3:0] sh;
  59
  60 output [7:0] y_shl = a_shl << sh, y_shr = a_shr >> sh;
  61 output signed [7:0] y_sshl = a_sshl <<< sh, y_sshr = a_sshr >>> sh;
  62
  63 endmodule
  64
  65 // ------------------------------------
  66
  67 module example004(clk, rst, y);
  68
  69 input clk, rst;
  70 output y;
  71
  72 reg [3:0] counter;
  73
  74 always @(posedge clk)
  75         case (1'b1)
  76                 rst, counter == 9:
  77                         counter <= 0;
  78                 default:
  79                         counter <= counter+1;
  80         endcase
  81
  82 assign y = counter == 12;
  83
  84 endmodule
  85