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[yosys.git] / passes / sat / sat.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] Temporal Induction by Incremental SAT Solving
21 // Niklas Een and Niklas Sörensson (2003)
22 // http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.4.8161
23
24 #include "kernel/register.h"
25 #include "kernel/celltypes.h"
26 #include "kernel/consteval.h"
27 #include "kernel/sigtools.h"
28 #include "kernel/log.h"
29 #include "kernel/satgen.h"
30 #include <stdlib.h>
31 #include <stdio.h>
32 #include <algorithm>
33 #include <errno.h>
34 #include <string.h>
35
36 USING_YOSYS_NAMESPACE
37 PRIVATE_NAMESPACE_BEGIN
38
39 struct SatHelper
40 {
41 RTLIL::Design *design;
42 RTLIL::Module *module;
43
44 SigMap sigmap;
45 CellTypes ct;
46
47 ezSatPtr ez;
48 SatGen satgen;
49
50 // additional constraints
51 std::vector<std::pair<std::string, std::string>> sets, prove, prove_x, sets_init;
52 std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
53 std::map<int, std::vector<std::string>> unsets_at;
54 bool prove_asserts, set_assumes;
55
56 // undef constraints
57 bool enable_undef, set_init_def, set_init_undef, set_init_zero, ignore_unknown_cells;
58 std::vector<std::string> sets_def, sets_any_undef, sets_all_undef;
59 std::map<int, std::vector<std::string>> sets_def_at, sets_any_undef_at, sets_all_undef_at;
60
61 // model variables
62 std::vector<std::string> shows;
63 SigPool show_signal_pool;
64 SigSet<RTLIL::Cell*> show_drivers;
65 int max_timestep, timeout;
66 bool gotTimeout;
67
68 SatHelper(RTLIL::Design *design, RTLIL::Module *module, bool enable_undef) :
69 design(design), module(module), sigmap(module), ct(design), satgen(ez.get(), &sigmap)
70 {
71 this->enable_undef = enable_undef;
72 satgen.model_undef = enable_undef;
73 set_init_def = false;
74 set_init_undef = false;
75 set_init_zero = false;
76 ignore_unknown_cells = false;
77 max_timestep = -1;
78 timeout = 0;
79 gotTimeout = false;
80 }
81
82 void check_undef_enabled(const RTLIL::SigSpec &sig)
83 {
84 if (enable_undef)
85 return;
86
87 std::vector<RTLIL::SigBit> sigbits = sig.to_sigbit_vector();
88 for (size_t i = 0; i < sigbits.size(); i++)
89 if (sigbits[i].wire == NULL && sigbits[i].data == RTLIL::State::Sx)
90 log_cmd_error("Bit %d of %s is undef but option -enable_undef is missing!\n", int(i), log_signal(sig));
91 }
92
93 void setup(int timestep = -1, bool initstate = false)
94 {
95 if (timestep > 0)
96 log ("\nSetting up time step %d:\n", timestep);
97 else
98 log ("\nSetting up SAT problem:\n");
99
100 if (initstate)
101 satgen.setInitState(timestep);
102
103 if (timestep > max_timestep)
104 max_timestep = timestep;
105
106 RTLIL::SigSpec big_lhs, big_rhs;
107
108 for (auto &s : sets)
109 {
110 RTLIL::SigSpec lhs, rhs;
111
112 if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
113 log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
114 if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
115 log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
116 show_signal_pool.add(sigmap(lhs));
117 show_signal_pool.add(sigmap(rhs));
118
119 if (lhs.size() != rhs.size())
120 log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
121 s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
122
123 log("Import set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
124 big_lhs.remove2(lhs, &big_rhs);
125 big_lhs.append(lhs);
126 big_rhs.append(rhs);
127 }
128
129 for (auto &s : sets_at[timestep])
130 {
131 RTLIL::SigSpec lhs, rhs;
132
133 if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
134 log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
135 if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
136 log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
137 show_signal_pool.add(sigmap(lhs));
138 show_signal_pool.add(sigmap(rhs));
139
140 if (lhs.size() != rhs.size())
141 log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
142 s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
143
144 log("Import set-constraint for this timestep: %s = %s\n", log_signal(lhs), log_signal(rhs));
145 big_lhs.remove2(lhs, &big_rhs);
146 big_lhs.append(lhs);
147 big_rhs.append(rhs);
148 }
149
150 for (auto &s : unsets_at[timestep])
151 {
152 RTLIL::SigSpec lhs;
153
154 if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s))
155 log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str());
156 show_signal_pool.add(sigmap(lhs));
157
158 log("Import unset-constraint for this timestep: %s\n", log_signal(lhs));
159 big_lhs.remove2(lhs, &big_rhs);
160 }
161
162 log("Final constraint equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
163 check_undef_enabled(big_lhs), check_undef_enabled(big_rhs);
164 ez->assume(satgen.signals_eq(big_lhs, big_rhs, timestep));
165
166 // 0 = sets_def
167 // 1 = sets_any_undef
168 // 2 = sets_all_undef
169 std::set<RTLIL::SigSpec> sets_def_undef[3];
170
171 for (auto &s : sets_def) {
172 RTLIL::SigSpec sig;
173 if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
174 log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
175 sets_def_undef[0].insert(sig);
176 }
177
178 for (auto &s : sets_any_undef) {
179 RTLIL::SigSpec sig;
180 if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
181 log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
182 sets_def_undef[1].insert(sig);
183 }
184
185 for (auto &s : sets_all_undef) {
186 RTLIL::SigSpec sig;
187 if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
188 log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
189 sets_def_undef[2].insert(sig);
190 }
191
192 for (auto &s : sets_def_at[timestep]) {
193 RTLIL::SigSpec sig;
194 if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
195 log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
196 sets_def_undef[0].insert(sig);
197 sets_def_undef[1].erase(sig);
198 sets_def_undef[2].erase(sig);
199 }
200
201 for (auto &s : sets_any_undef_at[timestep]) {
202 RTLIL::SigSpec sig;
203 if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
204 log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
205 sets_def_undef[0].erase(sig);
206 sets_def_undef[1].insert(sig);
207 sets_def_undef[2].erase(sig);
208 }
209
210 for (auto &s : sets_all_undef_at[timestep]) {
211 RTLIL::SigSpec sig;
212 if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
213 log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str());
214 sets_def_undef[0].erase(sig);
215 sets_def_undef[1].erase(sig);
216 sets_def_undef[2].insert(sig);
217 }
218
219 for (int t = 0; t < 3; t++)
220 for (auto &sig : sets_def_undef[t]) {
221 log("Import %s constraint for this timestep: %s\n", t == 0 ? "def" : t == 1 ? "any_undef" : "all_undef", log_signal(sig));
222 std::vector<int> undef_sig = satgen.importUndefSigSpec(sig, timestep);
223 if (t == 0)
224 ez->assume(ez->NOT(ez->expression(ezSAT::OpOr, undef_sig)));
225 if (t == 1)
226 ez->assume(ez->expression(ezSAT::OpOr, undef_sig));
227 if (t == 2)
228 ez->assume(ez->expression(ezSAT::OpAnd, undef_sig));
229 }
230
231 int import_cell_counter = 0;
232 for (auto cell : module->cells())
233 if (design->selected(module, cell)) {
234 // log("Import cell: %s\n", RTLIL::id2cstr(cell->name));
235 if (satgen.importCell(cell, timestep)) {
236 for (auto &p : cell->connections())
237 if (ct.cell_output(cell->type, p.first))
238 show_drivers.insert(sigmap(p.second), cell);
239 import_cell_counter++;
240 } else if (ignore_unknown_cells)
241 log_warning("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
242 else
243 log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
244 }
245 log("Imported %d cells to SAT database.\n", import_cell_counter);
246
247 if (set_assumes) {
248 RTLIL::SigSpec assumes_a, assumes_en;
249 satgen.getAssumes(assumes_a, assumes_en, timestep);
250 for (int i = 0; i < GetSize(assumes_a); i++)
251 log("Import constraint from assume cell: %s when %s.\n", log_signal(assumes_a[i]), log_signal(assumes_en[i]));
252 ez->assume(satgen.importAssumes(timestep));
253 }
254
255 if (initstate)
256 {
257 RTLIL::SigSpec big_lhs, big_rhs;
258
259 for (auto &it : module->wires_)
260 {
261 if (it.second->attributes.count("\\init") == 0)
262 continue;
263
264 RTLIL::SigSpec lhs = sigmap(it.second);
265 RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
266 log_assert(lhs.size() == rhs.size());
267
268 RTLIL::SigSpec removed_bits;
269 for (int i = 0; i < lhs.size(); i++) {
270 RTLIL::SigSpec bit = lhs.extract(i, 1);
271 if (!satgen.initial_state.check_all(bit)) {
272 removed_bits.append(bit);
273 lhs.remove(i, 1);
274 rhs.remove(i, 1);
275 i--;
276 }
277 }
278
279 if (removed_bits.size())
280 log_warning("ignoring initial value on non-register: %s\n", log_signal(removed_bits));
281
282 if (lhs.size()) {
283 log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
284 big_lhs.remove2(lhs, &big_rhs);
285 big_lhs.append(lhs);
286 big_rhs.append(rhs);
287 }
288 }
289
290 for (auto &s : sets_init)
291 {
292 RTLIL::SigSpec lhs, rhs;
293
294 if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
295 log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str());
296 if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
297 log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str());
298 show_signal_pool.add(sigmap(lhs));
299 show_signal_pool.add(sigmap(rhs));
300
301 if (lhs.size() != rhs.size())
302 log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
303 s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
304
305 log("Import init set-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
306 big_lhs.remove2(lhs, &big_rhs);
307 big_lhs.append(lhs);
308 big_rhs.append(rhs);
309 }
310
311 if (!satgen.initial_state.check_all(big_lhs)) {
312 RTLIL::SigSpec rem = satgen.initial_state.remove(big_lhs);
313 log_cmd_error("Found -set-init bits that are not part of the initial_state: %s\n", log_signal(rem));
314 }
315
316 if (set_init_def) {
317 RTLIL::SigSpec rem = satgen.initial_state.export_all();
318 std::vector<int> undef_rem = satgen.importUndefSigSpec(rem, 1);
319 ez->assume(ez->NOT(ez->expression(ezSAT::OpOr, undef_rem)));
320 }
321
322 if (set_init_undef) {
323 RTLIL::SigSpec rem = satgen.initial_state.export_all();
324 rem.remove(big_lhs);
325 big_lhs.append(rem);
326 big_rhs.append(RTLIL::SigSpec(RTLIL::State::Sx, rem.size()));
327 }
328
329 if (set_init_zero) {
330 RTLIL::SigSpec rem = satgen.initial_state.export_all();
331 rem.remove(big_lhs);
332 big_lhs.append(rem);
333 big_rhs.append(RTLIL::SigSpec(RTLIL::State::S0, rem.size()));
334 }
335
336 if (big_lhs.size() == 0) {
337 log("No constraints for initial state found.\n\n");
338 return;
339 }
340
341 log("Final init constraint equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
342 check_undef_enabled(big_lhs), check_undef_enabled(big_rhs);
343 ez->assume(satgen.signals_eq(big_lhs, big_rhs, timestep));
344 }
345 }
346
347 int setup_proof(int timestep = -1)
348 {
349 log_assert(prove.size() || prove_x.size() || prove_asserts);
350
351 RTLIL::SigSpec big_lhs, big_rhs;
352 std::vector<int> prove_bits;
353
354 if (prove.size() > 0)
355 {
356 for (auto &s : prove)
357 {
358 RTLIL::SigSpec lhs, rhs;
359
360 if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
361 log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first.c_str());
362 if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
363 log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second.c_str());
364 show_signal_pool.add(sigmap(lhs));
365 show_signal_pool.add(sigmap(rhs));
366
367 if (lhs.size() != rhs.size())
368 log_cmd_error("Proof expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
369 s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
370
371 log("Import proof-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
372 big_lhs.remove2(lhs, &big_rhs);
373 big_lhs.append(lhs);
374 big_rhs.append(rhs);
375 }
376
377 log("Final proof equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
378 check_undef_enabled(big_lhs), check_undef_enabled(big_rhs);
379 prove_bits.push_back(satgen.signals_eq(big_lhs, big_rhs, timestep));
380 }
381
382 if (prove_x.size() > 0)
383 {
384 for (auto &s : prove_x)
385 {
386 RTLIL::SigSpec lhs, rhs;
387
388 if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first))
389 log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first.c_str());
390 if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second))
391 log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second.c_str());
392 show_signal_pool.add(sigmap(lhs));
393 show_signal_pool.add(sigmap(rhs));
394
395 if (lhs.size() != rhs.size())
396 log_cmd_error("Proof-x expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n",
397 s.first.c_str(), log_signal(lhs), lhs.size(), s.second.c_str(), log_signal(rhs), rhs.size());
398
399 log("Import proof-x-constraint: %s = %s\n", log_signal(lhs), log_signal(rhs));
400 big_lhs.remove2(lhs, &big_rhs);
401 big_lhs.append(lhs);
402 big_rhs.append(rhs);
403 }
404
405 log("Final proof-x equation: %s = %s\n", log_signal(big_lhs), log_signal(big_rhs));
406
407 std::vector<int> value_lhs = satgen.importDefSigSpec(big_lhs, timestep);
408 std::vector<int> value_rhs = satgen.importDefSigSpec(big_rhs, timestep);
409
410 std::vector<int> undef_lhs = satgen.importUndefSigSpec(big_lhs, timestep);
411 std::vector<int> undef_rhs = satgen.importUndefSigSpec(big_rhs, timestep);
412
413 for (size_t i = 0; i < value_lhs.size(); i++)
414 prove_bits.push_back(ez->OR(undef_lhs.at(i), ez->AND(ez->NOT(undef_rhs.at(i)), ez->NOT(ez->XOR(value_lhs.at(i), value_rhs.at(i))))));
415 }
416
417 if (prove_asserts) {
418 RTLIL::SigSpec asserts_a, asserts_en;
419 satgen.getAsserts(asserts_a, asserts_en, timestep);
420 for (int i = 0; i < GetSize(asserts_a); i++)
421 log("Import proof for assert: %s when %s.\n", log_signal(asserts_a[i]), log_signal(asserts_en[i]));
422 prove_bits.push_back(satgen.importAsserts(timestep));
423 }
424
425 return ez->expression(ezSAT::OpAnd, prove_bits);
426 }
427
428 void force_unique_state(int timestep_from, int timestep_to)
429 {
430 RTLIL::SigSpec state_signals = satgen.initial_state.export_all();
431 for (int i = timestep_from; i < timestep_to; i++)
432 ez->assume(ez->NOT(satgen.signals_eq(state_signals, state_signals, i, timestep_to)));
433 }
434
435 bool solve(const std::vector<int> &assumptions)
436 {
437 log_assert(gotTimeout == false);
438 ez->setSolverTimeout(timeout);
439 bool success = ez->solve(modelExpressions, modelValues, assumptions);
440 if (ez->getSolverTimoutStatus())
441 gotTimeout = true;
442 return success;
443 }
444
445 bool solve(int a = 0, int b = 0, int c = 0, int d = 0, int e = 0, int f = 0)
446 {
447 log_assert(gotTimeout == false);
448 ez->setSolverTimeout(timeout);
449 bool success = ez->solve(modelExpressions, modelValues, a, b, c, d, e, f);
450 if (ez->getSolverTimoutStatus())
451 gotTimeout = true;
452 return success;
453 }
454
455 struct ModelBlockInfo {
456 int timestep, offset, width;
457 std::string description;
458 bool operator < (const ModelBlockInfo &other) const {
459 if (timestep != other.timestep)
460 return timestep < other.timestep;
461 if (description != other.description)
462 return description < other.description;
463 if (offset != other.offset)
464 return offset < other.offset;
465 if (width != other.width)
466 return width < other.width;
467 return false;
468 }
469 };
470
471 std::vector<int> modelExpressions;
472 std::vector<bool> modelValues;
473 std::set<ModelBlockInfo> modelInfo;
474
475 void maximize_undefs()
476 {
477 log_assert(enable_undef);
478 std::vector<bool> backupValues;
479
480 while (1)
481 {
482 std::vector<int> must_undef, maybe_undef;
483
484 for (size_t i = 0; i < modelExpressions.size()/2; i++)
485 if (modelValues.at(modelExpressions.size()/2 + i))
486 must_undef.push_back(modelExpressions.at(modelExpressions.size()/2 + i));
487 else
488 maybe_undef.push_back(modelExpressions.at(modelExpressions.size()/2 + i));
489
490 backupValues.swap(modelValues);
491 if (!solve(ez->expression(ezSAT::OpAnd, must_undef), ez->expression(ezSAT::OpOr, maybe_undef)))
492 break;
493 }
494
495 backupValues.swap(modelValues);
496 }
497
498 void generate_model()
499 {
500 RTLIL::SigSpec modelSig;
501 modelExpressions.clear();
502 modelInfo.clear();
503
504 // Add "show" signals or alternatively the leaves on the input cone on all set and prove signals
505
506 if (shows.size() == 0)
507 {
508 SigPool queued_signals, handled_signals, final_signals;
509 queued_signals = show_signal_pool;
510 while (queued_signals.size() > 0) {
511 RTLIL::SigSpec sig = queued_signals.export_one();
512 queued_signals.del(sig);
513 handled_signals.add(sig);
514 std::set<RTLIL::Cell*> drivers = show_drivers.find(sig);
515 if (drivers.size() == 0) {
516 final_signals.add(sig);
517 } else {
518 for (auto &d : drivers)
519 for (auto &p : d->connections()) {
520 if (d->type == "$dff" && p.first == "\\CLK")
521 continue;
522 if (d->type.substr(0, 6) == "$_DFF_" && p.first == "\\C")
523 continue;
524 queued_signals.add(handled_signals.remove(sigmap(p.second)));
525 }
526 }
527 }
528 modelSig = final_signals.export_all();
529
530 // additionally add all set and prove signals directly
531 // (it improves user confidence if we write the constraints back ;-)
532 modelSig.append(show_signal_pool.export_all());
533 }
534 else
535 {
536 for (auto &s : shows) {
537 RTLIL::SigSpec sig;
538 if (!RTLIL::SigSpec::parse_sel(sig, design, module, s))
539 log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str());
540 log("Import show expression: %s\n", log_signal(sig));
541 modelSig.append(sig);
542 }
543 }
544
545 modelSig.sort_and_unify();
546 // log("Model signals: %s\n", log_signal(modelSig));
547
548 std::vector<int> modelUndefExpressions;
549
550 for (auto &c : modelSig.chunks())
551 if (c.wire != NULL)
552 {
553 ModelBlockInfo info;
554 RTLIL::SigSpec chunksig = c;
555 info.width = chunksig.size();
556 info.description = log_signal(chunksig);
557
558 for (int timestep = -1; timestep <= max_timestep; timestep++)
559 {
560 if ((timestep == -1 && max_timestep > 0) || timestep == 0)
561 continue;
562
563 info.timestep = timestep;
564 info.offset = modelExpressions.size();
565 modelInfo.insert(info);
566
567 std::vector<int> vec = satgen.importSigSpec(chunksig, timestep);
568 modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
569
570 if (enable_undef) {
571 std::vector<int> undef_vec = satgen.importUndefSigSpec(chunksig, timestep);
572 modelUndefExpressions.insert(modelUndefExpressions.end(), undef_vec.begin(), undef_vec.end());
573 }
574 }
575 }
576
577 // Add initial state signals as collected by satgen
578 //
579 modelSig = satgen.initial_state.export_all();
580 for (auto &c : modelSig.chunks())
581 if (c.wire != NULL)
582 {
583 ModelBlockInfo info;
584 RTLIL::SigSpec chunksig = c;
585
586 info.timestep = 0;
587 info.offset = modelExpressions.size();
588 info.width = chunksig.size();
589 info.description = log_signal(chunksig);
590 modelInfo.insert(info);
591
592 std::vector<int> vec = satgen.importSigSpec(chunksig, 1);
593 modelExpressions.insert(modelExpressions.end(), vec.begin(), vec.end());
594
595 if (enable_undef) {
596 std::vector<int> undef_vec = satgen.importUndefSigSpec(chunksig, 1);
597 modelUndefExpressions.insert(modelUndefExpressions.end(), undef_vec.begin(), undef_vec.end());
598 }
599 }
600
601 modelExpressions.insert(modelExpressions.end(), modelUndefExpressions.begin(), modelUndefExpressions.end());
602 }
603
604 void print_model()
605 {
606 int maxModelName = 10;
607 int maxModelWidth = 10;
608
609 for (auto &info : modelInfo) {
610 maxModelName = max(maxModelName, int(info.description.size()));
611 maxModelWidth = max(maxModelWidth, info.width);
612 }
613
614 log("\n");
615
616 int last_timestep = -2;
617 for (auto &info : modelInfo)
618 {
619 RTLIL::Const value;
620 bool found_undef = false;
621
622 for (int i = 0; i < info.width; i++) {
623 value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
624 if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
625 value.bits.back() = RTLIL::State::Sx, found_undef = true;
626 }
627
628 if (info.timestep != last_timestep) {
629 const char *hline = "---------------------------------------------------------------------------------------------------"
630 "---------------------------------------------------------------------------------------------------"
631 "---------------------------------------------------------------------------------------------------";
632 if (last_timestep == -2) {
633 log(max_timestep > 0 ? " Time " : " ");
634 log("%-*s %11s %9s %*s\n", maxModelName+5, "Signal Name", "Dec", "Hex", maxModelWidth+3, "Bin");
635 }
636 log(max_timestep > 0 ? " ---- " : " ");
637 log("%*.*s %11.11s %9.9s %*.*s\n", maxModelName+5, maxModelName+5,
638 hline, hline, hline, maxModelWidth+3, maxModelWidth+3, hline);
639 last_timestep = info.timestep;
640 }
641
642 if (max_timestep > 0) {
643 if (info.timestep > 0)
644 log(" %4d ", info.timestep);
645 else
646 log(" init ");
647 } else
648 log(" ");
649
650 if (info.width <= 32 && !found_undef)
651 log("%-*s %11d %9x %*s\n", maxModelName+5, info.description.c_str(), value.as_int(), value.as_int(), maxModelWidth+3, value.as_string().c_str());
652 else
653 log("%-*s %11s %9s %*s\n", maxModelName+5, info.description.c_str(), "--", "--", maxModelWidth+3, value.as_string().c_str());
654 }
655
656 if (last_timestep == -2)
657 log(" no model variables selected for display.\n");
658 }
659
660 void dump_model_to_vcd(std::string vcd_file_name)
661 {
662 FILE *f = fopen(vcd_file_name.c_str(), "w");
663 if (!f)
664 log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno));
665
666 log("Dumping SAT model to VCD file %s\n", vcd_file_name.c_str());
667
668 time_t timestamp;
669 struct tm* now;
670 char stime[128] = {};
671 time(&timestamp);
672 now = localtime(&timestamp);
673 strftime(stime, sizeof(stime), "%c", now);
674
675 std::string module_fname = "unknown";
676 auto apos = module->attributes.find("\\src");
677 if(apos != module->attributes.end())
678 module_fname = module->attributes["\\src"].decode_string();
679
680 fprintf(f, "$date\n");
681 fprintf(f, " %s\n", stime);
682 fprintf(f, "$end\n");
683 fprintf(f, "$version\n");
684 fprintf(f, " Generated by %s\n", yosys_version_str);
685 fprintf(f, "$end\n");
686 fprintf(f, "$comment\n");
687 fprintf(f, " Generated from SAT problem in module %s (declared at %s)\n",
688 module->name.c_str(), module_fname.c_str());
689 fprintf(f, "$end\n");
690
691 // VCD has some limits on internal (non-display) identifier names, so make legal ones
692 std::map<std::string, std::string> vcdnames;
693
694 fprintf(f, "$scope module %s $end\n", module->name.c_str());
695 for (auto &info : modelInfo)
696 {
697 if (vcdnames.find(info.description) != vcdnames.end())
698 continue;
699
700 char namebuf[16];
701 snprintf(namebuf, sizeof(namebuf), "v%d", static_cast<int>(vcdnames.size()));
702 vcdnames[info.description] = namebuf;
703
704 // Even display identifiers can't use some special characters
705 std::string legal_desc = info.description.c_str();
706 for (auto &c : legal_desc) {
707 if(c == '$')
708 c = '_';
709 if(c == ':')
710 c = '_';
711 }
712
713 fprintf(f, "$var wire %d %s %s $end\n", info.width, namebuf, legal_desc.c_str());
714
715 // Need to look at first *two* cycles!
716 // We need to put a name on all variables but those without an initialization clause
717 // have no value at timestep 0
718 if(info.timestep > 1)
719 break;
720 }
721 fprintf(f, "$upscope $end\n");
722 fprintf(f, "$enddefinitions $end\n");
723 fprintf(f, "$dumpvars\n");
724
725 static const char bitvals[] = "01xzxx";
726
727 int last_timestep = -2;
728 for (auto &info : modelInfo)
729 {
730 RTLIL::Const value;
731
732 for (int i = 0; i < info.width; i++) {
733 value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
734 if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
735 value.bits.back() = RTLIL::State::Sx;
736 }
737
738 if (info.timestep != last_timestep) {
739 if(last_timestep == 0)
740 fprintf(f, "$end\n");
741 else
742 fprintf(f, "#%d\n", info.timestep);
743 last_timestep = info.timestep;
744 }
745
746 if(info.width == 1) {
747 fprintf(f, "%c%s\n", bitvals[value.bits[0]], vcdnames[info.description].c_str());
748 } else {
749 fprintf(f, "b");
750 for(int k=info.width-1; k >= 0; k --) //need to flip bit ordering for VCD
751 fprintf(f, "%c", bitvals[value.bits[k]]);
752 fprintf(f, " %s\n", vcdnames[info.description].c_str());
753 }
754 }
755
756 if (last_timestep == -2)
757 log(" no model variables selected for display.\n");
758
759 fclose(f);
760 }
761
762 void dump_model_to_json(std::string json_file_name)
763 {
764 FILE *f = fopen(json_file_name.c_str(), "w");
765 if (!f)
766 log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno));
767
768 log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name.c_str());
769
770 int mintime = 1, maxtime = 0, maxwidth = 0;;
771 dict<string, pair<int, dict<int, Const>>> wavedata;
772
773 for (auto &info : modelInfo)
774 {
775 Const value;
776 for (int i = 0; i < info.width; i++) {
777 value.bits.push_back(modelValues.at(info.offset+i) ? RTLIL::State::S1 : RTLIL::State::S0);
778 if (enable_undef && modelValues.at(modelExpressions.size()/2 + info.offset + i))
779 value.bits.back() = RTLIL::State::Sx;
780 }
781
782 wavedata[info.description].first = info.width;
783 wavedata[info.description].second[info.timestep] = value;
784 mintime = min(mintime, info.timestep);
785 maxtime = max(maxtime, info.timestep);
786 maxwidth = max(maxwidth, info.width);
787 }
788
789 fprintf(f, "{ \"signal\": [");
790 bool fist_wavedata = true;
791 for (auto &wd : wavedata)
792 {
793 fprintf(f, "%s", fist_wavedata ? "\n" : ",\n");
794 fist_wavedata = false;
795
796 vector<string> data;
797 string name = wd.first.c_str();
798 while (name.substr(0, 1) == "\\")
799 name = name.substr(1);
800
801 fprintf(f, " { \"name\": \"%s\", \"wave\": \"", name.c_str());
802 for (int i = mintime; i <= maxtime; i++) {
803 if (wd.second.second.count(i)) {
804 string this_data = wd.second.second[i].as_string();
805 char ch = '=';
806 if (wd.second.first == 1)
807 ch = this_data[0];
808 if (!data.empty() && data.back() == this_data) {
809 fprintf(f, ".");
810 } else {
811 data.push_back(this_data);
812 fprintf(f, "%c", ch);
813 }
814 } else {
815 data.push_back("");
816 fprintf(f, "4");
817 }
818 }
819 if (wd.second.first != 1) {
820 fprintf(f, "\", \"data\": [");
821 for (int i = 0; i < GetSize(data); i++)
822 fprintf(f, "%s\"%s\"", i ? ", " : "", data[i].c_str());
823 fprintf(f, "] }");
824 } else {
825 fprintf(f, "\" }");
826 }
827 }
828 fprintf(f, "\n ],\n");
829 fprintf(f, " \"config\": {\n");
830 fprintf(f, " \"hscale\": %.2f\n", maxwidth / 4.0);
831 fprintf(f, " }\n");
832 fprintf(f, "}\n");
833 fclose(f);
834 }
835
836 void invalidate_model(bool max_undef)
837 {
838 std::vector<int> clause;
839 if (enable_undef) {
840 for (size_t i = 0; i < modelExpressions.size()/2; i++) {
841 int bit = modelExpressions.at(i), bit_undef = modelExpressions.at(modelExpressions.size()/2 + i);
842 bool val = modelValues.at(i), val_undef = modelValues.at(modelExpressions.size()/2 + i);
843 if (!max_undef || !val_undef)
844 clause.push_back(val_undef ? ez->NOT(bit_undef) : val ? ez->NOT(bit) : bit);
845 }
846 } else
847 for (size_t i = 0; i < modelExpressions.size(); i++)
848 clause.push_back(modelValues.at(i) ? ez->NOT(modelExpressions.at(i)) : modelExpressions.at(i));
849 ez->assume(ez->expression(ezSAT::OpOr, clause));
850 }
851 };
852
853 void print_proof_failed()
854 {
855 log("\n");
856 log(" ______ ___ ___ _ _ _ _ \n");
857 log(" (_____ \\ / __) / __) (_) | | | |\n");
858 log(" _____) )___ ___ ___ _| |__ _| |__ _____ _| | _____ __| | |\n");
859 log(" | ____/ ___) _ \\ / _ (_ __) (_ __|____ | | || ___ |/ _ |_|\n");
860 log(" | | | | | |_| | |_| || | | | / ___ | | || ____( (_| |_ \n");
861 log(" |_| |_| \\___/ \\___/ |_| |_| \\_____|_|\\_)_____)\\____|_|\n");
862 log("\n");
863 }
864
865 void print_timeout()
866 {
867 log("\n");
868 log(" _____ _ _ _____ ____ _ _____\n");
869 log(" /__ __\\/ \\/ \\__/|/ __// _ \\/ \\ /\\/__ __\\\n");
870 log(" / \\ | || |\\/||| \\ | / \\|| | || / \\\n");
871 log(" | | | || | ||| /_ | \\_/|| \\_/| | |\n");
872 log(" \\_/ \\_/\\_/ \\|\\____\\\\____/\\____/ \\_/\n");
873 log("\n");
874 }
875
876 void print_qed()
877 {
878 log("\n");
879 log(" /$$$$$$ /$$$$$$$$ /$$$$$$$ \n");
880 log(" /$$__ $$ | $$_____/ | $$__ $$ \n");
881 log(" | $$ \\ $$ | $$ | $$ \\ $$ \n");
882 log(" | $$ | $$ | $$$$$ | $$ | $$ \n");
883 log(" | $$ | $$ | $$__/ | $$ | $$ \n");
884 log(" | $$/$$ $$ | $$ | $$ | $$ \n");
885 log(" | $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$\n");
886 log(" \\____ $$$|__/|________/|__/|_______/|__/\n");
887 log(" \\__/ \n");
888 log("\n");
889 }
890
891 struct SatPass : public Pass {
892 SatPass() : Pass("sat", "solve a SAT problem in the circuit") { }
893 void help() YS_OVERRIDE
894 {
895 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
896 log("\n");
897 log(" sat [options] [selection]\n");
898 log("\n");
899 log("This command solves a SAT problem defined over the currently selected circuit\n");
900 log("and additional constraints passed as parameters.\n");
901 log("\n");
902 log(" -all\n");
903 log(" show all solutions to the problem (this can grow exponentially, use\n");
904 log(" -max <N> instead to get <N> solutions)\n");
905 log("\n");
906 log(" -max <N>\n");
907 log(" like -all, but limit number of solutions to <N>\n");
908 log("\n");
909 log(" -enable_undef\n");
910 log(" enable modeling of undef value (aka 'x-bits')\n");
911 log(" this option is implied by -set-def, -set-undef et. cetera\n");
912 log("\n");
913 log(" -max_undef\n");
914 log(" maximize the number of undef bits in solutions, giving a better\n");
915 log(" picture of which input bits are actually vital to the solution.\n");
916 log("\n");
917 log(" -set <signal> <value>\n");
918 log(" set the specified signal to the specified value.\n");
919 log("\n");
920 log(" -set-def <signal>\n");
921 log(" add a constraint that all bits of the given signal must be defined\n");
922 log("\n");
923 log(" -set-any-undef <signal>\n");
924 log(" add a constraint that at least one bit of the given signal is undefined\n");
925 log("\n");
926 log(" -set-all-undef <signal>\n");
927 log(" add a constraint that all bits of the given signal are undefined\n");
928 log("\n");
929 log(" -set-def-inputs\n");
930 log(" add -set-def constraints for all module inputs\n");
931 log("\n");
932 log(" -show <signal>\n");
933 log(" show the model for the specified signal. if no -show option is\n");
934 log(" passed then a set of signals to be shown is automatically selected.\n");
935 log("\n");
936 log(" -show-inputs, -show-outputs, -show-ports\n");
937 log(" add all module (input/output) ports to the list of shown signals\n");
938 log("\n");
939 log(" -show-regs, -show-public, -show-all\n");
940 log(" show all registers, show signals with 'public' names, show all signals\n");
941 log("\n");
942 log(" -ignore_div_by_zero\n");
943 log(" ignore all solutions that involve a division by zero\n");
944 log("\n");
945 log(" -ignore_unknown_cells\n");
946 log(" ignore all cells that can not be matched to a SAT model\n");
947 log("\n");
948 log("The following options can be used to set up a sequential problem:\n");
949 log("\n");
950 log(" -seq <N>\n");
951 log(" set up a sequential problem with <N> time steps. The steps will\n");
952 log(" be numbered from 1 to N.\n");
953 log("\n");
954 log(" note: for large <N> it can be significantly faster to use\n");
955 log(" -tempinduct-baseonly -maxsteps <N> instead of -seq <N>.\n");
956 log("\n");
957 log(" -set-at <N> <signal> <value>\n");
958 log(" -unset-at <N> <signal>\n");
959 log(" set or unset the specified signal to the specified value in the\n");
960 log(" given timestep. this has priority over a -set for the same signal.\n");
961 log("\n");
962 log(" -set-assumes\n");
963 log(" set all assumptions provided via $assume cells\n");
964 log("\n");
965 log(" -set-def-at <N> <signal>\n");
966 log(" -set-any-undef-at <N> <signal>\n");
967 log(" -set-all-undef-at <N> <signal>\n");
968 log(" add undef constraints in the given timestep.\n");
969 log("\n");
970 log(" -set-init <signal> <value>\n");
971 log(" set the initial value for the register driving the signal to the value\n");
972 log("\n");
973 log(" -set-init-undef\n");
974 log(" set all initial states (not set using -set-init) to undef\n");
975 log("\n");
976 log(" -set-init-def\n");
977 log(" do not force a value for the initial state but do not allow undef\n");
978 log("\n");
979 log(" -set-init-zero\n");
980 log(" set all initial states (not set using -set-init) to zero\n");
981 log("\n");
982 log(" -dump_vcd <vcd-file-name>\n");
983 log(" dump SAT model (counter example in proof) to VCD file\n");
984 log("\n");
985 log(" -dump_json <json-file-name>\n");
986 log(" dump SAT model (counter example in proof) to a WaveJSON file.\n");
987 log("\n");
988 log(" -dump_cnf <cnf-file-name>\n");
989 log(" dump CNF of SAT problem (in DIMACS format). in temporal induction\n");
990 log(" proofs this is the CNF of the first induction step.\n");
991 log("\n");
992 log("The following additional options can be used to set up a proof. If also -seq\n");
993 log("is passed, a temporal induction proof is performed.\n");
994 log("\n");
995 log(" -tempinduct\n");
996 log(" Perform a temporal induction proof. In a temporal induction proof it is\n");
997 log(" proven that the condition holds forever after the number of time steps\n");
998 log(" specified using -seq.\n");
999 log("\n");
1000 log(" -tempinduct-def\n");
1001 log(" Perform a temporal induction proof. Assume an initial state with all\n");
1002 log(" registers set to defined values for the induction step.\n");
1003 log("\n");
1004 log(" -tempinduct-baseonly\n");
1005 log(" Run only the basecase half of temporal induction (requires -maxsteps)\n");
1006 log("\n");
1007 log(" -tempinduct-inductonly\n");
1008 log(" Run only the induction half of temporal induction\n");
1009 log("\n");
1010 log(" -tempinduct-skip <N>\n");
1011 log(" Skip the first <N> steps of the induction proof.\n");
1012 log("\n");
1013 log(" note: this will assume that the base case holds for <N> steps.\n");
1014 log(" this must be proven independently with \"-tempinduct-baseonly\n");
1015 log(" -maxsteps <N>\". Use -initsteps if you just want to set a\n");
1016 log(" minimal induction length.\n");
1017 log("\n");
1018 log(" -prove <signal> <value>\n");
1019 log(" Attempt to proof that <signal> is always <value>.\n");
1020 log("\n");
1021 log(" -prove-x <signal> <value>\n");
1022 log(" Like -prove, but an undef (x) bit in the lhs matches any value on\n");
1023 log(" the right hand side. Useful for equivalence checking.\n");
1024 log("\n");
1025 log(" -prove-asserts\n");
1026 log(" Prove that all asserts in the design hold.\n");
1027 log("\n");
1028 log(" -prove-skip <N>\n");
1029 log(" Do not enforce the prove-condition for the first <N> time steps.\n");
1030 log("\n");
1031 log(" -maxsteps <N>\n");
1032 log(" Set a maximum length for the induction.\n");
1033 log("\n");
1034 log(" -initsteps <N>\n");
1035 log(" Set initial length for the induction.\n");
1036 log(" This will speed up the search of the right induction length\n");
1037 log(" for deep induction proofs.\n");
1038 log("\n");
1039 log(" -stepsize <N>\n");
1040 log(" Increase the size of the induction proof in steps of <N>.\n");
1041 log(" This will speed up the search of the right induction length\n");
1042 log(" for deep induction proofs.\n");
1043 log("\n");
1044 log(" -timeout <N>\n");
1045 log(" Maximum number of seconds a single SAT instance may take.\n");
1046 log("\n");
1047 log(" -verify\n");
1048 log(" Return an error and stop the synthesis script if the proof fails.\n");
1049 log("\n");
1050 log(" -verify-no-timeout\n");
1051 log(" Like -verify but do not return an error for timeouts.\n");
1052 log("\n");
1053 log(" -falsify\n");
1054 log(" Return an error and stop the synthesis script if the proof succeeds.\n");
1055 log("\n");
1056 log(" -falsify-no-timeout\n");
1057 log(" Like -falsify but do not return an error for timeouts.\n");
1058 log("\n");
1059 }
1060 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1061 {
1062 std::vector<std::pair<std::string, std::string>> sets, sets_init, prove, prove_x;
1063 std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
1064 std::map<int, std::vector<std::string>> unsets_at, sets_def_at, sets_any_undef_at, sets_all_undef_at;
1065 std::vector<std::string> shows, sets_def, sets_any_undef, sets_all_undef;
1066 int loopcount = 0, seq_len = 0, maxsteps = 0, initsteps = 0, timeout = 0, prove_skip = 0;
1067 bool verify = false, fail_on_timeout = false, enable_undef = false, set_def_inputs = false;
1068 bool ignore_div_by_zero = false, set_init_undef = false, set_init_zero = false, max_undef = false;
1069 bool tempinduct = false, prove_asserts = false, show_inputs = false, show_outputs = false;
1070 bool show_regs = false, show_public = false, show_all = false;
1071 bool ignore_unknown_cells = false, falsify = false, tempinduct_def = false, set_init_def = false;
1072 bool tempinduct_baseonly = false, tempinduct_inductonly = false, set_assumes = false;
1073 int tempinduct_skip = 0, stepsize = 1;
1074 std::string vcd_file_name, json_file_name, cnf_file_name;
1075
1076 log_header(design, "Executing SAT pass (solving SAT problems in the circuit).\n");
1077
1078 size_t argidx;
1079 for (argidx = 1; argidx < args.size(); argidx++) {
1080 if (args[argidx] == "-all") {
1081 loopcount = -1;
1082 continue;
1083 }
1084 if (args[argidx] == "-verify") {
1085 fail_on_timeout = true;
1086 verify = true;
1087 continue;
1088 }
1089 if (args[argidx] == "-verify-no-timeout") {
1090 verify = true;
1091 continue;
1092 }
1093 if (args[argidx] == "-falsify") {
1094 fail_on_timeout = true;
1095 falsify = true;
1096 continue;
1097 }
1098 if (args[argidx] == "-falsify-no-timeout") {
1099 falsify = true;
1100 continue;
1101 }
1102 if (args[argidx] == "-timeout" && argidx+1 < args.size()) {
1103 timeout = atoi(args[++argidx].c_str());
1104 continue;
1105 }
1106 if (args[argidx] == "-max" && argidx+1 < args.size()) {
1107 loopcount = atoi(args[++argidx].c_str());
1108 continue;
1109 }
1110 if (args[argidx] == "-maxsteps" && argidx+1 < args.size()) {
1111 maxsteps = atoi(args[++argidx].c_str());
1112 continue;
1113 }
1114 if (args[argidx] == "-initsteps" && argidx+1 < args.size()) {
1115 initsteps = atoi(args[++argidx].c_str());
1116 continue;
1117 }
1118 if (args[argidx] == "-stepsize" && argidx+1 < args.size()) {
1119 stepsize = max(1, atoi(args[++argidx].c_str()));
1120 continue;
1121 }
1122 if (args[argidx] == "-ignore_div_by_zero") {
1123 ignore_div_by_zero = true;
1124 continue;
1125 }
1126 if (args[argidx] == "-enable_undef") {
1127 enable_undef = true;
1128 continue;
1129 }
1130 if (args[argidx] == "-max_undef") {
1131 enable_undef = true;
1132 max_undef = true;
1133 continue;
1134 }
1135 if (args[argidx] == "-set-def-inputs") {
1136 enable_undef = true;
1137 set_def_inputs = true;
1138 continue;
1139 }
1140 if (args[argidx] == "-set" && argidx+2 < args.size()) {
1141 std::string lhs = args[++argidx];
1142 std::string rhs = args[++argidx];
1143 sets.push_back(std::pair<std::string, std::string>(lhs, rhs));
1144 continue;
1145 }
1146 if (args[argidx] == "-set-def" && argidx+1 < args.size()) {
1147 sets_def.push_back(args[++argidx]);
1148 enable_undef = true;
1149 continue;
1150 }
1151 if (args[argidx] == "-set-any-undef" && argidx+1 < args.size()) {
1152 sets_any_undef.push_back(args[++argidx]);
1153 enable_undef = true;
1154 continue;
1155 }
1156 if (args[argidx] == "-set-all-undef" && argidx+1 < args.size()) {
1157 sets_all_undef.push_back(args[++argidx]);
1158 enable_undef = true;
1159 continue;
1160 }
1161 if (args[argidx] == "-set-assumes") {
1162 set_assumes = true;
1163 continue;
1164 }
1165 if (args[argidx] == "-tempinduct") {
1166 tempinduct = true;
1167 continue;
1168 }
1169 if (args[argidx] == "-tempinduct-def") {
1170 tempinduct = true;
1171 tempinduct_def = true;
1172 continue;
1173 }
1174 if (args[argidx] == "-tempinduct-baseonly") {
1175 tempinduct = true;
1176 tempinduct_baseonly = true;
1177 continue;
1178 }
1179 if (args[argidx] == "-tempinduct-inductonly") {
1180 tempinduct = true;
1181 tempinduct_inductonly = true;
1182 continue;
1183 }
1184 if (args[argidx] == "-tempinduct-skip" && argidx+1 < args.size()) {
1185 tempinduct_skip = atoi(args[++argidx].c_str());
1186 continue;
1187 }
1188 if (args[argidx] == "-prove" && argidx+2 < args.size()) {
1189 std::string lhs = args[++argidx];
1190 std::string rhs = args[++argidx];
1191 prove.push_back(std::pair<std::string, std::string>(lhs, rhs));
1192 continue;
1193 }
1194 if (args[argidx] == "-prove-x" && argidx+2 < args.size()) {
1195 std::string lhs = args[++argidx];
1196 std::string rhs = args[++argidx];
1197 prove_x.push_back(std::pair<std::string, std::string>(lhs, rhs));
1198 enable_undef = true;
1199 continue;
1200 }
1201 if (args[argidx] == "-prove-asserts") {
1202 prove_asserts = true;
1203 continue;
1204 }
1205 if (args[argidx] == "-prove-skip" && argidx+1 < args.size()) {
1206 prove_skip = atoi(args[++argidx].c_str());
1207 continue;
1208 }
1209 if (args[argidx] == "-seq" && argidx+1 < args.size()) {
1210 seq_len = atoi(args[++argidx].c_str());
1211 continue;
1212 }
1213 if (args[argidx] == "-set-at" && argidx+3 < args.size()) {
1214 int timestep = atoi(args[++argidx].c_str());
1215 std::string lhs = args[++argidx];
1216 std::string rhs = args[++argidx];
1217 sets_at[timestep].push_back(std::pair<std::string, std::string>(lhs, rhs));
1218 continue;
1219 }
1220 if (args[argidx] == "-unset-at" && argidx+2 < args.size()) {
1221 int timestep = atoi(args[++argidx].c_str());
1222 unsets_at[timestep].push_back(args[++argidx]);
1223 continue;
1224 }
1225 if (args[argidx] == "-set-def-at" && argidx+2 < args.size()) {
1226 int timestep = atoi(args[++argidx].c_str());
1227 sets_def_at[timestep].push_back(args[++argidx]);
1228 enable_undef = true;
1229 continue;
1230 }
1231 if (args[argidx] == "-set-any-undef-at" && argidx+2 < args.size()) {
1232 int timestep = atoi(args[++argidx].c_str());
1233 sets_any_undef_at[timestep].push_back(args[++argidx]);
1234 enable_undef = true;
1235 continue;
1236 }
1237 if (args[argidx] == "-set-all-undef-at" && argidx+2 < args.size()) {
1238 int timestep = atoi(args[++argidx].c_str());
1239 sets_all_undef_at[timestep].push_back(args[++argidx]);
1240 enable_undef = true;
1241 continue;
1242 }
1243 if (args[argidx] == "-set-init" && argidx+2 < args.size()) {
1244 std::string lhs = args[++argidx];
1245 std::string rhs = args[++argidx];
1246 sets_init.push_back(std::pair<std::string, std::string>(lhs, rhs));
1247 continue;
1248 }
1249 if (args[argidx] == "-set-init-undef") {
1250 set_init_undef = true;
1251 enable_undef = true;
1252 continue;
1253 }
1254 if (args[argidx] == "-set-init-def") {
1255 set_init_def = true;
1256 continue;
1257 }
1258 if (args[argidx] == "-set-init-zero") {
1259 set_init_zero = true;
1260 continue;
1261 }
1262 if (args[argidx] == "-show" && argidx+1 < args.size()) {
1263 shows.push_back(args[++argidx]);
1264 continue;
1265 }
1266 if (args[argidx] == "-show-inputs") {
1267 show_inputs = true;
1268 continue;
1269 }
1270 if (args[argidx] == "-show-outputs") {
1271 show_outputs = true;
1272 continue;
1273 }
1274 if (args[argidx] == "-show-ports") {
1275 show_inputs = true;
1276 show_outputs = true;
1277 continue;
1278 }
1279 if (args[argidx] == "-show-regs") {
1280 show_regs = true;
1281 continue;
1282 }
1283 if (args[argidx] == "-show-public") {
1284 show_public = true;
1285 continue;
1286 }
1287 if (args[argidx] == "-show-all") {
1288 show_all = true;
1289 continue;
1290 }
1291 if (args[argidx] == "-ignore_unknown_cells") {
1292 ignore_unknown_cells = true;
1293 continue;
1294 }
1295 if (args[argidx] == "-dump_vcd" && argidx+1 < args.size()) {
1296 vcd_file_name = args[++argidx];
1297 continue;
1298 }
1299 if (args[argidx] == "-dump_json" && argidx+1 < args.size()) {
1300 json_file_name = args[++argidx];
1301 continue;
1302 }
1303 if (args[argidx] == "-dump_cnf" && argidx+1 < args.size()) {
1304 cnf_file_name = args[++argidx];
1305 continue;
1306 }
1307 break;
1308 }
1309 extra_args(args, argidx, design);
1310
1311 RTLIL::Module *module = NULL;
1312 for (auto mod : design->selected_modules()) {
1313 if (module)
1314 log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", log_id(module), log_id(mod));
1315 module = mod;
1316 }
1317 if (module == NULL)
1318 log_cmd_error("Can't perform SAT on an empty selection!\n");
1319
1320 if (!prove.size() && !prove_x.size() && !prove_asserts && tempinduct)
1321 log_cmd_error("Got -tempinduct but nothing to prove!\n");
1322
1323 if (prove_skip && tempinduct)
1324 log_cmd_error("Options -prove-skip and -tempinduct don't work with each other. Use -seq instead of -prove-skip.\n");
1325
1326 if (prove_skip >= seq_len && prove_skip > 0)
1327 log_cmd_error("The value of -prove-skip must be smaller than the one of -seq.\n");
1328
1329 if (set_init_undef + set_init_zero + set_init_def > 1)
1330 log_cmd_error("The options -set-init-undef, -set-init-def, and -set-init-zero are exclusive!\n");
1331
1332 if (set_def_inputs) {
1333 for (auto &it : module->wires_)
1334 if (it.second->port_input)
1335 sets_def.push_back(it.second->name.str());
1336 }
1337
1338 if (show_inputs) {
1339 for (auto &it : module->wires_)
1340 if (it.second->port_input)
1341 shows.push_back(it.second->name.str());
1342 }
1343
1344 if (show_outputs) {
1345 for (auto &it : module->wires_)
1346 if (it.second->port_output)
1347 shows.push_back(it.second->name.str());
1348 }
1349
1350 if (show_regs) {
1351 pool<Wire*> reg_wires;
1352 for (auto cell : module->cells()) {
1353 if (cell->type == "$dff" || cell->type.substr(0, 6) == "$_DFF_")
1354 for (auto bit : cell->getPort("\\Q"))
1355 if (bit.wire)
1356 reg_wires.insert(bit.wire);
1357 }
1358 for (auto wire : reg_wires)
1359 shows.push_back(wire->name.str());
1360 }
1361
1362 if (show_public) {
1363 for (auto wire : module->wires())
1364 if (wire->name[0] == '\\')
1365 shows.push_back(wire->name.str());
1366 }
1367
1368 if (show_all) {
1369 for (auto wire : module->wires())
1370 shows.push_back(wire->name.str());
1371 }
1372
1373 if (tempinduct)
1374 {
1375 if (loopcount > 0 || max_undef)
1376 log_cmd_error("The options -max, -all, and -max_undef are not supported for temporal induction proofs!\n");
1377
1378 SatHelper basecase(design, module, enable_undef);
1379 SatHelper inductstep(design, module, enable_undef);
1380
1381 basecase.sets = sets;
1382 basecase.set_assumes = set_assumes;
1383 basecase.prove = prove;
1384 basecase.prove_x = prove_x;
1385 basecase.prove_asserts = prove_asserts;
1386 basecase.sets_at = sets_at;
1387 basecase.unsets_at = unsets_at;
1388 basecase.shows = shows;
1389 basecase.timeout = timeout;
1390 basecase.sets_def = sets_def;
1391 basecase.sets_any_undef = sets_any_undef;
1392 basecase.sets_all_undef = sets_all_undef;
1393 basecase.sets_def_at = sets_def_at;
1394 basecase.sets_any_undef_at = sets_any_undef_at;
1395 basecase.sets_all_undef_at = sets_all_undef_at;
1396 basecase.sets_init = sets_init;
1397 basecase.set_init_def = set_init_def;
1398 basecase.set_init_undef = set_init_undef;
1399 basecase.set_init_zero = set_init_zero;
1400 basecase.satgen.ignore_div_by_zero = ignore_div_by_zero;
1401 basecase.ignore_unknown_cells = ignore_unknown_cells;
1402
1403 for (int timestep = 1; timestep <= seq_len; timestep++)
1404 if (!tempinduct_inductonly)
1405 basecase.setup(timestep, timestep == 1);
1406
1407 inductstep.sets = sets;
1408 inductstep.set_assumes = set_assumes;
1409 inductstep.prove = prove;
1410 inductstep.prove_x = prove_x;
1411 inductstep.prove_asserts = prove_asserts;
1412 inductstep.shows = shows;
1413 inductstep.timeout = timeout;
1414 inductstep.sets_def = sets_def;
1415 inductstep.sets_any_undef = sets_any_undef;
1416 inductstep.sets_all_undef = sets_all_undef;
1417 inductstep.satgen.ignore_div_by_zero = ignore_div_by_zero;
1418 inductstep.ignore_unknown_cells = ignore_unknown_cells;
1419
1420 if (!tempinduct_baseonly) {
1421 inductstep.setup(1);
1422 inductstep.ez->assume(inductstep.setup_proof(1));
1423 }
1424
1425 if (tempinduct_def) {
1426 std::vector<int> undef_state = inductstep.satgen.importUndefSigSpec(inductstep.satgen.initial_state.export_all(), 1);
1427 inductstep.ez->assume(inductstep.ez->NOT(inductstep.ez->expression(ezSAT::OpOr, undef_state)));
1428 }
1429
1430 for (int inductlen = 1; inductlen <= maxsteps || maxsteps == 0; inductlen++)
1431 {
1432 log("\n** Trying induction with length %d **\n", inductlen);
1433
1434 // phase 1: proving base case
1435
1436 if (!tempinduct_inductonly)
1437 {
1438 basecase.setup(seq_len + inductlen, seq_len + inductlen == 1);
1439 int property = basecase.setup_proof(seq_len + inductlen);
1440 basecase.generate_model();
1441
1442 if (inductlen > 1)
1443 basecase.force_unique_state(seq_len + 1, seq_len + inductlen);
1444
1445 if (tempinduct_skip < inductlen)
1446 {
1447 log("\n[base case %d] Solving problem with %d variables and %d clauses..\n",
1448 inductlen, basecase.ez->numCnfVariables(), basecase.ez->numCnfClauses());
1449 log_flush();
1450
1451 if (basecase.solve(basecase.ez->NOT(property))) {
1452 log("SAT temporal induction proof finished - model found for base case: FAIL!\n");
1453 print_proof_failed();
1454 basecase.print_model();
1455 if(!vcd_file_name.empty())
1456 basecase.dump_model_to_vcd(vcd_file_name);
1457 if(!json_file_name.empty())
1458 basecase.dump_model_to_json(json_file_name);
1459 goto tip_failed;
1460 }
1461
1462 if (basecase.gotTimeout)
1463 goto timeout;
1464
1465 log("Base case for induction length %d proven.\n", inductlen);
1466 }
1467 else
1468 {
1469 log("\n[base case %d] Skipping prove for this step (-tempinduct-skip %d).",
1470 inductlen, tempinduct_skip);
1471 log("\n[base case %d] Problem size so far: %d variables and %d clauses.\n",
1472 inductlen, basecase.ez->numCnfVariables(), basecase.ez->numCnfClauses());
1473 }
1474 basecase.ez->assume(property);
1475 }
1476
1477 // phase 2: proving induction step
1478
1479 if (!tempinduct_baseonly)
1480 {
1481 inductstep.setup(inductlen + 1);
1482 int property = inductstep.setup_proof(inductlen + 1);
1483 inductstep.generate_model();
1484
1485 if (inductlen > 1)
1486 inductstep.force_unique_state(1, inductlen + 1);
1487
1488 if (inductlen <= tempinduct_skip || inductlen <= initsteps || inductlen % stepsize != 0)
1489 {
1490 if (inductlen < tempinduct_skip)
1491 log("\n[induction step %d] Skipping prove for this step (-tempinduct-skip %d).",
1492 inductlen, tempinduct_skip);
1493 if (inductlen < initsteps)
1494 log("\n[induction step %d] Skipping prove for this step (-initsteps %d).",
1495 inductlen, tempinduct_skip);
1496 if (inductlen % stepsize != 0)
1497 log("\n[induction step %d] Skipping prove for this step (-stepsize %d).",
1498 inductlen, stepsize);
1499 log("\n[induction step %d] Problem size so far: %d variables and %d clauses.\n",
1500 inductlen, inductstep.ez->numCnfVariables(), inductstep.ez->numCnfClauses());
1501 inductstep.ez->assume(property);
1502 }
1503 else
1504 {
1505 if (!cnf_file_name.empty())
1506 {
1507 FILE *f = fopen(cnf_file_name.c_str(), "w");
1508 if (!f)
1509 log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
1510
1511 log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str());
1512 cnf_file_name.clear();
1513
1514 inductstep.ez->printDIMACS(f, false);
1515 fclose(f);
1516 }
1517
1518 log("\n[induction step %d] Solving problem with %d variables and %d clauses..\n",
1519 inductlen, inductstep.ez->numCnfVariables(), inductstep.ez->numCnfClauses());
1520 log_flush();
1521
1522 if (!inductstep.solve(inductstep.ez->NOT(property))) {
1523 if (inductstep.gotTimeout)
1524 goto timeout;
1525 log("Induction step proven: SUCCESS!\n");
1526 print_qed();
1527 goto tip_success;
1528 }
1529
1530 log("Induction step failed. Incrementing induction length.\n");
1531 inductstep.ez->assume(property);
1532 inductstep.print_model();
1533 }
1534 }
1535 }
1536
1537 if (tempinduct_baseonly) {
1538 log("\nReached maximum number of time steps -> proved base case for %d steps: SUCCESS!\n", maxsteps);
1539 goto tip_success;
1540 }
1541
1542 log("\nReached maximum number of time steps -> proof failed.\n");
1543 if(!vcd_file_name.empty())
1544 inductstep.dump_model_to_vcd(vcd_file_name);
1545 if(!json_file_name.empty())
1546 inductstep.dump_model_to_json(json_file_name);
1547 print_proof_failed();
1548
1549 tip_failed:
1550 if (verify) {
1551 log("\n");
1552 log_error("Called with -verify and proof did fail!\n");
1553 }
1554
1555 if (0)
1556 tip_success:
1557 if (falsify) {
1558 log("\n");
1559 log_error("Called with -falsify and proof did succeed!\n");
1560 }
1561 }
1562 else
1563 {
1564 if (maxsteps > 0)
1565 log_cmd_error("The options -maxsteps is only supported for temporal induction proofs!\n");
1566
1567 SatHelper sathelper(design, module, enable_undef);
1568
1569 sathelper.sets = sets;
1570 sathelper.set_assumes = set_assumes;
1571 sathelper.prove = prove;
1572 sathelper.prove_x = prove_x;
1573 sathelper.prove_asserts = prove_asserts;
1574 sathelper.sets_at = sets_at;
1575 sathelper.unsets_at = unsets_at;
1576 sathelper.shows = shows;
1577 sathelper.timeout = timeout;
1578 sathelper.sets_def = sets_def;
1579 sathelper.sets_any_undef = sets_any_undef;
1580 sathelper.sets_all_undef = sets_all_undef;
1581 sathelper.sets_def_at = sets_def_at;
1582 sathelper.sets_any_undef_at = sets_any_undef_at;
1583 sathelper.sets_all_undef_at = sets_all_undef_at;
1584 sathelper.sets_init = sets_init;
1585 sathelper.set_init_def = set_init_def;
1586 sathelper.set_init_undef = set_init_undef;
1587 sathelper.set_init_zero = set_init_zero;
1588 sathelper.satgen.ignore_div_by_zero = ignore_div_by_zero;
1589 sathelper.ignore_unknown_cells = ignore_unknown_cells;
1590
1591 if (seq_len == 0) {
1592 sathelper.setup();
1593 if (sathelper.prove.size() || sathelper.prove_x.size() || sathelper.prove_asserts)
1594 sathelper.ez->assume(sathelper.ez->NOT(sathelper.setup_proof()));
1595 } else {
1596 std::vector<int> prove_bits;
1597 for (int timestep = 1; timestep <= seq_len; timestep++) {
1598 sathelper.setup(timestep, timestep == 1);
1599 if (sathelper.prove.size() || sathelper.prove_x.size() || sathelper.prove_asserts)
1600 if (timestep > prove_skip)
1601 prove_bits.push_back(sathelper.setup_proof(timestep));
1602 }
1603 if (sathelper.prove.size() || sathelper.prove_x.size() || sathelper.prove_asserts)
1604 sathelper.ez->assume(sathelper.ez->NOT(sathelper.ez->expression(ezSAT::OpAnd, prove_bits)));
1605 }
1606 sathelper.generate_model();
1607
1608 if (!cnf_file_name.empty())
1609 {
1610 FILE *f = fopen(cnf_file_name.c_str(), "w");
1611 if (!f)
1612 log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno));
1613
1614 log("Dumping CNF to file `%s'.\n", cnf_file_name.c_str());
1615 cnf_file_name.clear();
1616
1617 sathelper.ez->printDIMACS(f, false);
1618 fclose(f);
1619 }
1620
1621 int rerun_counter = 0;
1622
1623 rerun_solver:
1624 log("\nSolving problem with %d variables and %d clauses..\n",
1625 sathelper.ez->numCnfVariables(), sathelper.ez->numCnfClauses());
1626 log_flush();
1627
1628 if (sathelper.solve())
1629 {
1630 if (max_undef) {
1631 log("SAT model found. maximizing number of undefs.\n");
1632 sathelper.maximize_undefs();
1633 }
1634
1635 if (!prove.size() && !prove_x.size() && !prove_asserts) {
1636 log("SAT solving finished - model found:\n");
1637 } else {
1638 log("SAT proof finished - model found: FAIL!\n");
1639 print_proof_failed();
1640 }
1641
1642 sathelper.print_model();
1643
1644 if(!vcd_file_name.empty())
1645 sathelper.dump_model_to_vcd(vcd_file_name);
1646 if(!json_file_name.empty())
1647 sathelper.dump_model_to_json(json_file_name);
1648
1649 if (loopcount != 0) {
1650 loopcount--, rerun_counter++;
1651 sathelper.invalidate_model(max_undef);
1652 goto rerun_solver;
1653 }
1654
1655 if (!prove.size() && !prove_x.size() && !prove_asserts) {
1656 if (falsify) {
1657 log("\n");
1658 log_error("Called with -falsify and found a model!\n");
1659 }
1660 } else {
1661 if (verify) {
1662 log("\n");
1663 log_error("Called with -verify and proof did fail!\n");
1664 }
1665 }
1666 }
1667 else
1668 {
1669 if (sathelper.gotTimeout)
1670 goto timeout;
1671 if (rerun_counter)
1672 log("SAT solving finished - no more models found (after %d distinct solutions).\n", rerun_counter);
1673 else if (!prove.size() && !prove_x.size() && !prove_asserts) {
1674 log("SAT solving finished - no model found.\n");
1675 if (verify) {
1676 log("\n");
1677 log_error("Called with -verify and found no model!\n");
1678 }
1679 } else {
1680 log("SAT proof finished - no model found: SUCCESS!\n");
1681 print_qed();
1682 if (falsify) {
1683 log("\n");
1684 log_error("Called with -falsify and proof did succeed!\n");
1685 }
1686 }
1687 }
1688
1689 if (!prove.size() && !prove_x.size() && !prove_asserts) {
1690 if (falsify && rerun_counter) {
1691 log("\n");
1692 log_error("Called with -falsify and found a model!\n");
1693 }
1694 } else {
1695 if (verify && rerun_counter) {
1696 log("\n");
1697 log_error("Called with -verify and proof did fail!\n");
1698 }
1699 }
1700 }
1701
1702 if (0) {
1703 timeout:
1704 log("Interrupted SAT solver: TIMEOUT!\n");
1705 print_timeout();
1706 if (fail_on_timeout)
1707 log_error("Called with -verify and proof did time out!\n");
1708 }
1709 }
1710 } SatPass;
1711
1712 PRIVATE_NAMESPACE_END