2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/sigtools.h"
24 PRIVATE_NAMESPACE_BEGIN
26 struct SupercoverPass
: public Pass
{
27 SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { }
28 void help() YS_OVERRIDE
30 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
32 log(" supercover [options] [selection]\n");
34 log("This command adds two cover cells for each bit of each selected wire, one\n");
35 log("checking for a hi signal level and one checking for lo level.\n");
38 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
40 // bool flag_noinit = false;
42 log_header(design
, "Executing SUPERCOVER pass.\n");
45 for (argidx
= 1; argidx
< args
.size(); argidx
++)
47 // if (args[argidx] == "-noinit") {
48 // flag_noinit = true;
53 extra_args(args
, argidx
, design
);
55 for (auto module
: design
->selected_modules())
57 SigMap
sigmap(module
);
58 pool
<SigBit
> handled_bits
;
60 int cnt_wire
= 0, cnt_bits
= 0;
61 log("Adding cover cells to module %s.\n", log_id(module
));
62 for (auto wire
: module
->selected_wires())
64 bool counted_wire
= false;
65 std::string src
= wire
->get_src_attribute();
67 for (auto bit
: sigmap(SigSpec(wire
)))
69 if (bit
.wire
== nullptr)
72 if (handled_bits
.count(bit
))
75 SigSpec inv
= module
->Not(NEW_ID
, bit
);
76 module
->addCover(NEW_ID
, bit
, State::S1
, src
);
77 module
->addCover(NEW_ID
, inv
, State::S1
, src
);
79 handled_bits
.insert(bit
);
87 log(" added cover cells to %d wires, %d bits.\n", cnt_wire
, cnt_bits
);