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abc9_ops: still emit delay table even box has no timing
[yosys.git] / passes / techmap / abc.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] ABC
21 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
22 // http://www.eecs.berkeley.edu/~alanmi/abc/
23
24 // [[CITE]] Berkeley Logic Interchange Format (BLIF)
25 // University of California. Berkeley. July 28, 1992
26 // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
27
28 // [[CITE]] Kahn's Topological sorting algorithm
29 // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
30 // http://en.wikipedia.org/wiki/Topological_sorting
31
32 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
33 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
34 #define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
35 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
36 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
37
38 #define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
39 #define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
40 #define ABC_FAST_COMMAND_LUT "strash; dretime; if"
41 #define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
42 #define ABC_FAST_COMMAND_DFL "strash; dretime; map"
43
44 #include "kernel/register.h"
45 #include "kernel/sigtools.h"
46 #include "kernel/celltypes.h"
47 #include "kernel/cost.h"
48 #include "kernel/log.h"
49 #include <stdlib.h>
50 #include <stdio.h>
51 #include <string.h>
52 #include <cctype>
53 #include <cerrno>
54 #include <sstream>
55 #include <climits>
56
57 #ifndef _WIN32
58 # include <unistd.h>
59 # include <dirent.h>
60 #endif
61
62 #include "frontends/blif/blifparse.h"
63
64 #ifdef YOSYS_LINK_ABC
65 extern "C" int Abc_RealMain(int argc, char *argv[]);
66 #endif
67
68 USING_YOSYS_NAMESPACE
69 PRIVATE_NAMESPACE_BEGIN
70
71 enum class gate_type_t {
72 G_NONE,
73 G_FF,
74 G_BUF,
75 G_NOT,
76 G_AND,
77 G_NAND,
78 G_OR,
79 G_NOR,
80 G_XOR,
81 G_XNOR,
82 G_ANDNOT,
83 G_ORNOT,
84 G_MUX,
85 G_NMUX,
86 G_AOI3,
87 G_OAI3,
88 G_AOI4,
89 G_OAI4
90 };
91
92 #define G(_name) gate_type_t::G_ ## _name
93
94 struct gate_t
95 {
96 int id;
97 gate_type_t type;
98 int in1, in2, in3, in4;
99 bool is_port;
100 RTLIL::SigBit bit;
101 RTLIL::State init;
102 };
103
104 bool map_mux4;
105 bool map_mux8;
106 bool map_mux16;
107
108 bool markgroups;
109 int map_autoidx;
110 SigMap assign_map;
111 RTLIL::Module *module;
112 std::vector<gate_t> signal_list;
113 std::map<RTLIL::SigBit, int> signal_map;
114 std::map<RTLIL::SigBit, RTLIL::State> signal_init;
115 pool<std::string> enabled_gates;
116 bool recover_init, cmos_cost;
117
118 bool clk_polarity, en_polarity;
119 RTLIL::SigSpec clk_sig, en_sig;
120 dict<int, std::string> pi_map, po_map;
121
122 int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1)
123 {
124 assign_map.apply(bit);
125
126 if (signal_map.count(bit) == 0) {
127 gate_t gate;
128 gate.id = signal_list.size();
129 gate.type = G(NONE);
130 gate.in1 = -1;
131 gate.in2 = -1;
132 gate.in3 = -1;
133 gate.in4 = -1;
134 gate.is_port = false;
135 gate.bit = bit;
136 if (signal_init.count(bit))
137 gate.init = signal_init.at(bit);
138 else
139 gate.init = State::Sx;
140 signal_list.push_back(gate);
141 signal_map[bit] = gate.id;
142 }
143
144 gate_t &gate = signal_list[signal_map[bit]];
145
146 if (gate_type != G(NONE))
147 gate.type = gate_type;
148 if (in1 >= 0)
149 gate.in1 = in1;
150 if (in2 >= 0)
151 gate.in2 = in2;
152 if (in3 >= 0)
153 gate.in3 = in3;
154 if (in4 >= 0)
155 gate.in4 = in4;
156
157 return gate.id;
158 }
159
160 void mark_port(RTLIL::SigSpec sig)
161 {
162 for (auto &bit : assign_map(sig))
163 if (bit.wire != NULL && signal_map.count(bit) > 0)
164 signal_list[signal_map[bit]].is_port = true;
165 }
166
167 void extract_cell(RTLIL::Cell *cell, bool keepff)
168 {
169 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
170 {
171 if (clk_polarity != (cell->type == ID($_DFF_P_)))
172 return;
173 if (clk_sig != assign_map(cell->getPort(ID(C))))
174 return;
175 if (GetSize(en_sig) != 0)
176 return;
177 goto matching_dff;
178 }
179
180 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
181 {
182 if (clk_polarity != cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_)))
183 return;
184 if (en_polarity != cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
185 return;
186 if (clk_sig != assign_map(cell->getPort(ID(C))))
187 return;
188 if (en_sig != assign_map(cell->getPort(ID(E))))
189 return;
190 goto matching_dff;
191 }
192
193 if (0) {
194 matching_dff:
195 RTLIL::SigSpec sig_d = cell->getPort(ID(D));
196 RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
197
198 if (keepff)
199 for (auto &c : sig_q.chunks())
200 if (c.wire != NULL)
201 c.wire->attributes[ID::keep] = 1;
202
203 assign_map.apply(sig_d);
204 assign_map.apply(sig_q);
205
206 map_signal(sig_q, G(FF), map_signal(sig_d));
207
208 module->remove(cell);
209 return;
210 }
211
212 if (cell->type.in(ID($_BUF_), ID($_NOT_)))
213 {
214 RTLIL::SigSpec sig_a = cell->getPort(ID::A);
215 RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
216
217 assign_map.apply(sig_a);
218 assign_map.apply(sig_y);
219
220 map_signal(sig_y, cell->type == ID($_BUF_) ? G(BUF) : G(NOT), map_signal(sig_a));
221
222 module->remove(cell);
223 return;
224 }
225
226 if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
227 {
228 RTLIL::SigSpec sig_a = cell->getPort(ID::A);
229 RTLIL::SigSpec sig_b = cell->getPort(ID::B);
230 RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
231
232 assign_map.apply(sig_a);
233 assign_map.apply(sig_b);
234 assign_map.apply(sig_y);
235
236 int mapped_a = map_signal(sig_a);
237 int mapped_b = map_signal(sig_b);
238
239 if (cell->type == ID($_AND_))
240 map_signal(sig_y, G(AND), mapped_a, mapped_b);
241 else if (cell->type == ID($_NAND_))
242 map_signal(sig_y, G(NAND), mapped_a, mapped_b);
243 else if (cell->type == ID($_OR_))
244 map_signal(sig_y, G(OR), mapped_a, mapped_b);
245 else if (cell->type == ID($_NOR_))
246 map_signal(sig_y, G(NOR), mapped_a, mapped_b);
247 else if (cell->type == ID($_XOR_))
248 map_signal(sig_y, G(XOR), mapped_a, mapped_b);
249 else if (cell->type == ID($_XNOR_))
250 map_signal(sig_y, G(XNOR), mapped_a, mapped_b);
251 else if (cell->type == ID($_ANDNOT_))
252 map_signal(sig_y, G(ANDNOT), mapped_a, mapped_b);
253 else if (cell->type == ID($_ORNOT_))
254 map_signal(sig_y, G(ORNOT), mapped_a, mapped_b);
255 else
256 log_abort();
257
258 module->remove(cell);
259 return;
260 }
261
262 if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
263 {
264 RTLIL::SigSpec sig_a = cell->getPort(ID::A);
265 RTLIL::SigSpec sig_b = cell->getPort(ID::B);
266 RTLIL::SigSpec sig_s = cell->getPort(ID(S));
267 RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
268
269 assign_map.apply(sig_a);
270 assign_map.apply(sig_b);
271 assign_map.apply(sig_s);
272 assign_map.apply(sig_y);
273
274 int mapped_a = map_signal(sig_a);
275 int mapped_b = map_signal(sig_b);
276 int mapped_s = map_signal(sig_s);
277
278 map_signal(sig_y, cell->type == ID($_MUX_) ? G(MUX) : G(NMUX), mapped_a, mapped_b, mapped_s);
279
280 module->remove(cell);
281 return;
282 }
283
284 if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
285 {
286 RTLIL::SigSpec sig_a = cell->getPort(ID::A);
287 RTLIL::SigSpec sig_b = cell->getPort(ID::B);
288 RTLIL::SigSpec sig_c = cell->getPort(ID(C));
289 RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
290
291 assign_map.apply(sig_a);
292 assign_map.apply(sig_b);
293 assign_map.apply(sig_c);
294 assign_map.apply(sig_y);
295
296 int mapped_a = map_signal(sig_a);
297 int mapped_b = map_signal(sig_b);
298 int mapped_c = map_signal(sig_c);
299
300 map_signal(sig_y, cell->type == ID($_AOI3_) ? G(AOI3) : G(OAI3), mapped_a, mapped_b, mapped_c);
301
302 module->remove(cell);
303 return;
304 }
305
306 if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
307 {
308 RTLIL::SigSpec sig_a = cell->getPort(ID::A);
309 RTLIL::SigSpec sig_b = cell->getPort(ID::B);
310 RTLIL::SigSpec sig_c = cell->getPort(ID(C));
311 RTLIL::SigSpec sig_d = cell->getPort(ID(D));
312 RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
313
314 assign_map.apply(sig_a);
315 assign_map.apply(sig_b);
316 assign_map.apply(sig_c);
317 assign_map.apply(sig_d);
318 assign_map.apply(sig_y);
319
320 int mapped_a = map_signal(sig_a);
321 int mapped_b = map_signal(sig_b);
322 int mapped_c = map_signal(sig_c);
323 int mapped_d = map_signal(sig_d);
324
325 map_signal(sig_y, cell->type == ID($_AOI4_) ? G(AOI4) : G(OAI4), mapped_a, mapped_b, mapped_c, mapped_d);
326
327 module->remove(cell);
328 return;
329 }
330 }
331
332 std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr)
333 {
334 std::string abc_sname = abc_name.substr(1);
335 bool isnew = false;
336 if (abc_sname.compare(0, 4, "new_") == 0)
337 {
338 abc_sname.erase(0, 4);
339 isnew = true;
340 }
341 if (abc_sname.compare(0, 5, "ys__n") == 0)
342 {
343 abc_sname.erase(0, 5);
344 if (std::isdigit(abc_sname.at(0)))
345 {
346 int sid = std::atoi(abc_sname.c_str());
347 size_t postfix_start = abc_sname.find_first_not_of("0123456789");
348 std::string postfix = postfix_start != std::string::npos ? abc_sname.substr(postfix_start) : "";
349
350 if (sid < GetSize(signal_list))
351 {
352 auto sig = signal_list.at(sid);
353 if (sig.bit.wire != nullptr)
354 {
355 std::string s = stringf("$abc$%d$%s", map_autoidx, sig.bit.wire->name.c_str()+1);
356 if (sig.bit.wire->width != 1)
357 s += stringf("[%d]", sig.bit.offset);
358 if (isnew)
359 s += "_new";
360 s += postfix;
361 if (orig_wire != nullptr)
362 *orig_wire = sig.bit.wire;
363 return s;
364 }
365 }
366 }
367 }
368 return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
369 }
370
371 void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std::set<int> &workpool, std::vector<int> &in_counts)
372 {
373 if (f == NULL)
374 return;
375
376 log("Dumping loop state graph to slide %d.\n", ++nr);
377
378 fprintf(f, "digraph \"slide%d\" {\n", nr);
379 fprintf(f, " label=\"slide%d\";\n", nr);
380 fprintf(f, " rankdir=\"TD\";\n");
381
382 std::set<int> nodes;
383 for (auto &e : edges) {
384 nodes.insert(e.first);
385 for (auto n : e.second)
386 nodes.insert(n);
387 }
388
389 for (auto n : nodes)
390 fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
391 n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
392
393 for (auto &e : edges)
394 for (auto n : e.second)
395 fprintf(f, " ys__n%d -> ys__n%d;\n", e.first, n);
396
397 fprintf(f, "}\n");
398 }
399
400 void handle_loops()
401 {
402 // http://en.wikipedia.org/wiki/Topological_sorting
403 // (Kahn, Arthur B. (1962), "Topological sorting of large networks")
404
405 std::map<int, std::set<int>> edges;
406 std::vector<int> in_edges_count(signal_list.size());
407 std::set<int> workpool;
408
409 FILE *dot_f = NULL;
410 int dot_nr = 0;
411
412 // uncomment for troubleshooting the loop detection code
413 // dot_f = fopen("test.dot", "w");
414
415 for (auto &g : signal_list) {
416 if (g.type == G(NONE) || g.type == G(FF)) {
417 workpool.insert(g.id);
418 } else {
419 if (g.in1 >= 0) {
420 edges[g.in1].insert(g.id);
421 in_edges_count[g.id]++;
422 }
423 if (g.in2 >= 0 && g.in2 != g.in1) {
424 edges[g.in2].insert(g.id);
425 in_edges_count[g.id]++;
426 }
427 if (g.in3 >= 0 && g.in3 != g.in2 && g.in3 != g.in1) {
428 edges[g.in3].insert(g.id);
429 in_edges_count[g.id]++;
430 }
431 if (g.in4 >= 0 && g.in4 != g.in3 && g.in4 != g.in2 && g.in4 != g.in1) {
432 edges[g.in4].insert(g.id);
433 in_edges_count[g.id]++;
434 }
435 }
436 }
437
438 dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
439
440 while (workpool.size() > 0)
441 {
442 int id = *workpool.begin();
443 workpool.erase(id);
444
445 // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit));
446
447 for (int id2 : edges[id]) {
448 log_assert(in_edges_count[id2] > 0);
449 if (--in_edges_count[id2] == 0)
450 workpool.insert(id2);
451 }
452 edges.erase(id);
453
454 dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
455
456 while (workpool.size() == 0)
457 {
458 if (edges.size() == 0)
459 break;
460
461 int id1 = edges.begin()->first;
462
463 for (auto &edge_it : edges) {
464 int id2 = edge_it.first;
465 RTLIL::Wire *w1 = signal_list[id1].bit.wire;
466 RTLIL::Wire *w2 = signal_list[id2].bit.wire;
467 if (w1 == NULL)
468 id1 = id2;
469 else if (w2 == NULL)
470 continue;
471 else if (w1->name[0] == '$' && w2->name[0] == '\\')
472 id1 = id2;
473 else if (w1->name[0] == '\\' && w2->name[0] == '$')
474 continue;
475 else if (edges[id1].size() < edges[id2].size())
476 id1 = id2;
477 else if (edges[id1].size() > edges[id2].size())
478 continue;
479 else if (w2->name.str() < w1->name.str())
480 id1 = id2;
481 }
482
483 if (edges[id1].size() == 0) {
484 edges.erase(id1);
485 continue;
486 }
487
488 log_assert(signal_list[id1].bit.wire != NULL);
489
490 std::stringstream sstr;
491 sstr << "$abcloop$" << (autoidx++);
492 RTLIL::Wire *wire = module->addWire(sstr.str());
493
494 bool first_line = true;
495 for (int id2 : edges[id1]) {
496 if (first_line)
497 log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire)),
498 log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
499 else
500 log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire)))), "",
501 log_signal(signal_list[id1].bit), log_signal(signal_list[id2].bit));
502 first_line = false;
503 }
504
505 int id3 = map_signal(RTLIL::SigSpec(wire));
506 signal_list[id1].is_port = true;
507 signal_list[id3].is_port = true;
508 log_assert(id3 == int(in_edges_count.size()));
509 in_edges_count.push_back(0);
510 workpool.insert(id3);
511
512 for (int id2 : edges[id1]) {
513 if (signal_list[id2].in1 == id1)
514 signal_list[id2].in1 = id3;
515 if (signal_list[id2].in2 == id1)
516 signal_list[id2].in2 = id3;
517 if (signal_list[id2].in3 == id1)
518 signal_list[id2].in3 = id3;
519 if (signal_list[id2].in4 == id1)
520 signal_list[id2].in4 = id3;
521 }
522 edges[id1].swap(edges[id3]);
523
524 module->connect(RTLIL::SigSig(signal_list[id3].bit, signal_list[id1].bit));
525 dump_loop_graph(dot_f, dot_nr, edges, workpool, in_edges_count);
526 }
527 }
528
529 if (dot_f != NULL)
530 fclose(dot_f);
531 }
532
533 std::string add_echos_to_abc_cmd(std::string str)
534 {
535 std::string new_str, token;
536 for (size_t i = 0; i < str.size(); i++) {
537 token += str[i];
538 if (str[i] == ';') {
539 while (i+1 < str.size() && str[i+1] == ' ')
540 i++;
541 new_str += "echo + " + token + " " + token + " ";
542 token.clear();
543 }
544 }
545
546 if (!token.empty()) {
547 if (!new_str.empty())
548 new_str += "echo + " + token + "; ";
549 new_str += token;
550 }
551
552 return new_str;
553 }
554
555 std::string fold_abc_cmd(std::string str)
556 {
557 std::string token, new_str = " ";
558 int char_counter = 10;
559
560 for (size_t i = 0; i <= str.size(); i++) {
561 if (i < str.size())
562 token += str[i];
563 if (i == str.size() || str[i] == ';') {
564 if (char_counter + token.size() > 75)
565 new_str += "\n ", char_counter = 14;
566 new_str += token, char_counter += token.size();
567 token.clear();
568 }
569 }
570
571 return new_str;
572 }
573
574 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
575 {
576 if (show_tempdir)
577 return text;
578
579 while (1) {
580 size_t pos = text.find(tempdir_name);
581 if (pos == std::string::npos)
582 break;
583 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
584 }
585
586 std::string selfdir_name = proc_self_dirname();
587 if (selfdir_name != "/") {
588 while (1) {
589 size_t pos = text.find(selfdir_name);
590 if (pos == std::string::npos)
591 break;
592 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
593 }
594 }
595
596 return text;
597 }
598
599 struct abc_output_filter
600 {
601 bool got_cr;
602 int escape_seq_state;
603 std::string linebuf;
604 std::string tempdir_name;
605 bool show_tempdir;
606
607 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
608 {
609 got_cr = false;
610 escape_seq_state = 0;
611 }
612
613 void next_char(char ch)
614 {
615 if (escape_seq_state == 0 && ch == '\033') {
616 escape_seq_state = 1;
617 return;
618 }
619 if (escape_seq_state == 1) {
620 escape_seq_state = ch == '[' ? 2 : 0;
621 return;
622 }
623 if (escape_seq_state == 2) {
624 if ((ch < '0' || '9' < ch) && ch != ';')
625 escape_seq_state = 0;
626 return;
627 }
628 escape_seq_state = 0;
629 if (ch == '\r') {
630 got_cr = true;
631 return;
632 }
633 if (ch == '\n') {
634 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
635 got_cr = false, linebuf.clear();
636 return;
637 }
638 if (got_cr)
639 got_cr = false, linebuf.clear();
640 linebuf += ch;
641 }
642
643 void next_line(const std::string &line)
644 {
645 int pi, po;
646 if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
647 log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
648 pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
649 po, po_map.count(po) ? po_map.at(po).c_str() : "???");
650 return;
651 }
652
653 for (char ch : line)
654 next_char(ch);
655 }
656 };
657
658 void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
659 std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
660 bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
661 const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress)
662 {
663 module = current_module;
664 map_autoidx = autoidx++;
665
666 signal_map.clear();
667 signal_list.clear();
668 pi_map.clear();
669 po_map.clear();
670 recover_init = false;
671
672 if (clk_str != "$")
673 {
674 clk_polarity = true;
675 clk_sig = RTLIL::SigSpec();
676
677 en_polarity = true;
678 en_sig = RTLIL::SigSpec();
679 }
680
681 if (!clk_str.empty() && clk_str != "$")
682 {
683 if (clk_str.find(',') != std::string::npos) {
684 int pos = clk_str.find(',');
685 std::string en_str = clk_str.substr(pos+1);
686 clk_str = clk_str.substr(0, pos);
687 if (en_str[0] == '!') {
688 en_polarity = false;
689 en_str = en_str.substr(1);
690 }
691 if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
692 en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
693 }
694 if (clk_str[0] == '!') {
695 clk_polarity = false;
696 clk_str = clk_str.substr(1);
697 }
698 if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
699 clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
700 }
701
702 if (dff_mode && clk_sig.empty())
703 log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
704
705 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
706 if (!cleanup)
707 tempdir_name[0] = tempdir_name[4] = '_';
708 tempdir_name = make_temp_dir(tempdir_name);
709 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
710 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
711
712 std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
713
714 if (!liberty_file.empty()) {
715 abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
716 if (!constr_file.empty())
717 abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
718 } else
719 if (!lut_costs.empty())
720 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
721 else
722 abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
723
724 if (!script_file.empty()) {
725 if (script_file[0] == '+') {
726 for (size_t i = 1; i < script_file.size(); i++)
727 if (script_file[i] == '\'')
728 abc_script += "'\\''";
729 else if (script_file[i] == ',')
730 abc_script += " ";
731 else
732 abc_script += script_file[i];
733 } else
734 abc_script += stringf("source %s", script_file.c_str());
735 } else if (!lut_costs.empty()) {
736 bool all_luts_cost_same = true;
737 for (int this_cost : lut_costs)
738 if (this_cost != lut_costs.front())
739 all_luts_cost_same = false;
740 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
741 if (all_luts_cost_same && !fast_mode)
742 abc_script += "; lutpack {S}";
743 } else if (!liberty_file.empty())
744 abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
745 else if (sop_mode)
746 abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
747 else
748 abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
749
750 if (script_file.empty() && !delay_target.empty())
751 for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
752 abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
753
754 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
755 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
756
757 for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
758 abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
759
760 for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
761 abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
762
763 for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
764 abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
765 if (abc_dress)
766 abc_script += "; dress";
767 abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
768 abc_script = add_echos_to_abc_cmd(abc_script);
769
770 for (size_t i = 0; i+1 < abc_script.size(); i++)
771 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
772 abc_script[i+1] = '\n';
773
774 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
775 fprintf(f, "%s\n", abc_script.c_str());
776 fclose(f);
777
778 if (dff_mode || !clk_str.empty())
779 {
780 if (clk_sig.size() == 0)
781 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
782 else {
783 log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
784 if (en_sig.size() != 0)
785 log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
786 log("\n");
787 }
788 }
789
790 for (auto c : cells)
791 extract_cell(c, keepff);
792
793 for (auto &wire_it : module->wires_) {
794 if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID::keep))
795 mark_port(RTLIL::SigSpec(wire_it.second));
796 }
797
798 for (auto &cell_it : module->cells_)
799 for (auto &port_it : cell_it.second->connections())
800 mark_port(port_it.second);
801
802 if (clk_sig.size() != 0)
803 mark_port(clk_sig);
804
805 if (en_sig.size() != 0)
806 mark_port(en_sig);
807
808 handle_loops();
809
810 std::string buffer = stringf("%s/input.blif", tempdir_name.c_str());
811 f = fopen(buffer.c_str(), "wt");
812 if (f == NULL)
813 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
814
815 fprintf(f, ".model netlist\n");
816
817 int count_input = 0;
818 fprintf(f, ".inputs");
819 for (auto &si : signal_list) {
820 if (!si.is_port || si.type != G(NONE))
821 continue;
822 fprintf(f, " ys__n%d", si.id);
823 pi_map[count_input++] = log_signal(si.bit);
824 }
825 if (count_input == 0)
826 fprintf(f, " dummy_input\n");
827 fprintf(f, "\n");
828
829 int count_output = 0;
830 fprintf(f, ".outputs");
831 for (auto &si : signal_list) {
832 if (!si.is_port || si.type == G(NONE))
833 continue;
834 fprintf(f, " ys__n%d", si.id);
835 po_map[count_output++] = log_signal(si.bit);
836 }
837 fprintf(f, "\n");
838
839 for (auto &si : signal_list)
840 fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit));
841
842 for (auto &si : signal_list) {
843 if (si.bit.wire == NULL) {
844 fprintf(f, ".names ys__n%d\n", si.id);
845 if (si.bit == RTLIL::State::S1)
846 fprintf(f, "1\n");
847 }
848 }
849
850 int count_gates = 0;
851 for (auto &si : signal_list) {
852 if (si.type == G(BUF)) {
853 fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
854 fprintf(f, "1 1\n");
855 } else if (si.type == G(NOT)) {
856 fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
857 fprintf(f, "0 1\n");
858 } else if (si.type == G(AND)) {
859 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
860 fprintf(f, "11 1\n");
861 } else if (si.type == G(NAND)) {
862 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
863 fprintf(f, "0- 1\n");
864 fprintf(f, "-0 1\n");
865 } else if (si.type == G(OR)) {
866 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
867 fprintf(f, "-1 1\n");
868 fprintf(f, "1- 1\n");
869 } else if (si.type == G(NOR)) {
870 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
871 fprintf(f, "00 1\n");
872 } else if (si.type == G(XOR)) {
873 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
874 fprintf(f, "01 1\n");
875 fprintf(f, "10 1\n");
876 } else if (si.type == G(XNOR)) {
877 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
878 fprintf(f, "00 1\n");
879 fprintf(f, "11 1\n");
880 } else if (si.type == G(ANDNOT)) {
881 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
882 fprintf(f, "10 1\n");
883 } else if (si.type == G(ORNOT)) {
884 fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
885 fprintf(f, "1- 1\n");
886 fprintf(f, "-0 1\n");
887 } else if (si.type == G(MUX)) {
888 fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
889 fprintf(f, "1-0 1\n");
890 fprintf(f, "-11 1\n");
891 } else if (si.type == G(NMUX)) {
892 fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
893 fprintf(f, "0-0 1\n");
894 fprintf(f, "-01 1\n");
895 } else if (si.type == G(AOI3)) {
896 fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
897 fprintf(f, "-00 1\n");
898 fprintf(f, "0-0 1\n");
899 } else if (si.type == G(OAI3)) {
900 fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
901 fprintf(f, "00- 1\n");
902 fprintf(f, "--0 1\n");
903 } else if (si.type == G(AOI4)) {
904 fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
905 fprintf(f, "-0-0 1\n");
906 fprintf(f, "-00- 1\n");
907 fprintf(f, "0--0 1\n");
908 fprintf(f, "0-0- 1\n");
909 } else if (si.type == G(OAI4)) {
910 fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
911 fprintf(f, "00-- 1\n");
912 fprintf(f, "--00 1\n");
913 } else if (si.type == G(FF)) {
914 if (si.init == State::S0 || si.init == State::S1) {
915 fprintf(f, ".latch ys__n%d ys__n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
916 recover_init = true;
917 } else
918 fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id);
919 } else if (si.type != G(NONE))
920 log_abort();
921 if (si.type != G(NONE))
922 count_gates++;
923 }
924
925 fprintf(f, ".end\n");
926 fclose(f);
927
928 log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
929 count_gates, GetSize(signal_list), count_input, count_output);
930 log_push();
931 if (count_output > 0)
932 {
933 log_header(design, "Executing ABC.\n");
934
935 auto &cell_cost = cmos_cost ? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
936
937 buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
938 f = fopen(buffer.c_str(), "wt");
939 if (f == NULL)
940 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
941 fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
942 fprintf(f, "GATE ONE 1 Y=CONST1;\n");
943 fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_BUF_)));
944 fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOT_)));
945 if (enabled_gates.count("AND"))
946 fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_AND_)));
947 if (enabled_gates.count("NAND"))
948 fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NAND_)));
949 if (enabled_gates.count("OR"))
950 fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost.at(ID($_OR_)));
951 if (enabled_gates.count("NOR"))
952 fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_NOR_)));
953 if (enabled_gates.count("XOR"))
954 fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XOR_)));
955 if (enabled_gates.count("XNOR"))
956 fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_XNOR_)));
957 if (enabled_gates.count("ANDNOT"))
958 fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ANDNOT_)));
959 if (enabled_gates.count("ORNOT"))
960 fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_ORNOT_)));
961 if (enabled_gates.count("AOI3"))
962 fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI3_)));
963 if (enabled_gates.count("OAI3"))
964 fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI3_)));
965 if (enabled_gates.count("AOI4"))
966 fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_AOI4_)));
967 if (enabled_gates.count("OAI4"))
968 fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost.at(ID($_OAI4_)));
969 if (enabled_gates.count("MUX"))
970 fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_MUX_)));
971 if (enabled_gates.count("NMUX"))
972 fprintf(f, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost.at(ID($_NMUX_)));
973 if (map_mux4)
974 fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost.at(ID($_MUX_)));
975 if (map_mux8)
976 fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost.at(ID($_MUX_)));
977 if (map_mux16)
978 fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost.at(ID($_MUX_)));
979 fclose(f);
980
981 if (!lut_costs.empty()) {
982 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
983 f = fopen(buffer.c_str(), "wt");
984 if (f == NULL)
985 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
986 for (int i = 0; i < GetSize(lut_costs); i++)
987 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
988 fclose(f);
989 }
990
991 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
992 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
993
994 #ifndef YOSYS_LINK_ABC
995 abc_output_filter filt(tempdir_name, show_tempdir);
996 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
997 #else
998 // These needs to be mutable, supposedly due to getopt
999 char *abc_argv[5];
1000 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
1001 abc_argv[0] = strdup(exe_file.c_str());
1002 abc_argv[1] = strdup("-s");
1003 abc_argv[2] = strdup("-f");
1004 abc_argv[3] = strdup(tmp_script_name.c_str());
1005 abc_argv[4] = 0;
1006 int ret = Abc_RealMain(4, abc_argv);
1007 free(abc_argv[0]);
1008 free(abc_argv[1]);
1009 free(abc_argv[2]);
1010 free(abc_argv[3]);
1011 #endif
1012 if (ret != 0)
1013 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
1014
1015 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
1016 std::ifstream ifs;
1017 ifs.open(buffer);
1018 if (ifs.fail())
1019 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
1020
1021 bool builtin_lib = liberty_file.empty();
1022 RTLIL::Design *mapped_design = new RTLIL::Design;
1023 parse_blif(mapped_design, ifs, builtin_lib ? ID(DFF) : ID(_dff_), false, sop_mode);
1024
1025 ifs.close();
1026
1027 log_header(design, "Re-integrating ABC results.\n");
1028 RTLIL::Module *mapped_mod = mapped_design->modules_[ID(netlist)];
1029 if (mapped_mod == NULL)
1030 log_error("ABC output file does not contain a module `netlist'.\n");
1031 for (auto &it : mapped_mod->wires_) {
1032 RTLIL::Wire *w = it.second;
1033 RTLIL::Wire *orig_wire = nullptr;
1034 RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
1035 if (orig_wire != nullptr && orig_wire->attributes.count(ID(src)))
1036 wire->attributes[ID(src)] = orig_wire->attributes[ID(src)];
1037 if (markgroups) wire->attributes[ID(abcgroup)] = map_autoidx;
1038 design->select(module, wire);
1039 }
1040
1041 std::map<std::string, int> cell_stats;
1042 for (auto c : mapped_mod->cells())
1043 {
1044 if (builtin_lib)
1045 {
1046 cell_stats[RTLIL::unescape_id(c->type)]++;
1047 if (c->type.in(ID(ZERO), ID(ONE))) {
1048 RTLIL::SigSig conn;
1049 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]);
1050 conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
1051 module->connect(conn);
1052 continue;
1053 }
1054 if (c->type == ID(BUF)) {
1055 RTLIL::SigSig conn;
1056 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]);
1057 conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]);
1058 module->connect(conn);
1059 continue;
1060 }
1061 if (c->type == ID(NOT)) {
1062 RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
1063 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1064 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1065 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1066 design->select(module, cell);
1067 continue;
1068 }
1069 if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
1070 RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
1071 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1072 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1073 cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
1074 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1075 design->select(module, cell);
1076 continue;
1077 }
1078 if (c->type.in(ID(MUX), ID(NMUX))) {
1079 RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
1080 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1081 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1082 cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
1083 cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
1084 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1085 design->select(module, cell);
1086 continue;
1087 }
1088 if (c->type == ID(MUX4)) {
1089 RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
1090 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1091 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1092 cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
1093 cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
1094 cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
1095 cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
1096 cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
1097 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1098 design->select(module, cell);
1099 continue;
1100 }
1101 if (c->type == ID(MUX8)) {
1102 RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
1103 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1104 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1105 cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
1106 cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
1107 cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
1108 cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
1109 cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
1110 cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
1111 cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
1112 cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
1113 cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
1114 cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
1115 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1116 design->select(module, cell);
1117 continue;
1118 }
1119 if (c->type == ID(MUX16)) {
1120 RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
1121 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1122 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1123 cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
1124 cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
1125 cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
1126 cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
1127 cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
1128 cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
1129 cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
1130 cell->setPort(ID(I), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(I)).as_wire()->name)]));
1131 cell->setPort(ID(J), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(J)).as_wire()->name)]));
1132 cell->setPort(ID(K), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(K)).as_wire()->name)]));
1133 cell->setPort(ID(L), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(L)).as_wire()->name)]));
1134 cell->setPort(ID(M), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(M)).as_wire()->name)]));
1135 cell->setPort(ID(N), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(N)).as_wire()->name)]));
1136 cell->setPort(ID(O), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(O)).as_wire()->name)]));
1137 cell->setPort(ID(P), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(P)).as_wire()->name)]));
1138 cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
1139 cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
1140 cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
1141 cell->setPort(ID(V), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(V)).as_wire()->name)]));
1142 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1143 design->select(module, cell);
1144 continue;
1145 }
1146 if (c->type.in(ID(AOI3), ID(OAI3))) {
1147 RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
1148 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1149 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1150 cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
1151 cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
1152 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1153 design->select(module, cell);
1154 continue;
1155 }
1156 if (c->type.in(ID(AOI4), ID(OAI4))) {
1157 RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
1158 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1159 cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
1160 cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
1161 cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
1162 cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
1163 cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
1164 design->select(module, cell);
1165 continue;
1166 }
1167 if (c->type == ID(DFF)) {
1168 log_assert(clk_sig.size() == 1);
1169 RTLIL::Cell *cell;
1170 if (en_sig.size() == 0) {
1171 cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
1172 } else {
1173 log_assert(en_sig.size() == 1);
1174 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
1175 cell->setPort(ID(E), en_sig);
1176 }
1177 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1178 cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
1179 cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
1180 cell->setPort(ID(C), clk_sig);
1181 design->select(module, cell);
1182 continue;
1183 }
1184 }
1185 else
1186 cell_stats[RTLIL::unescape_id(c->type)]++;
1187
1188 if (c->type.in(ID(_const0_), ID(_const1_))) {
1189 RTLIL::SigSig conn;
1190 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
1191 conn.second = RTLIL::SigSpec(c->type == ID(_const0_) ? 0 : 1, 1);
1192 module->connect(conn);
1193 continue;
1194 }
1195
1196 if (c->type == ID(_dff_)) {
1197 log_assert(clk_sig.size() == 1);
1198 RTLIL::Cell *cell;
1199 if (en_sig.size() == 0) {
1200 cell = module->addCell(remap_name(c->name), clk_polarity ? ID($_DFF_P_) : ID($_DFF_N_));
1201 } else {
1202 log_assert(en_sig.size() == 1);
1203 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
1204 cell->setPort(ID(E), en_sig);
1205 }
1206 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1207 cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
1208 cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
1209 cell->setPort(ID(C), clk_sig);
1210 design->select(module, cell);
1211 continue;
1212 }
1213
1214 if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)).as_int() == 2) {
1215 SigSpec my_a = module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)];
1216 SigSpec my_y = module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)];
1217 module->connect(my_y, my_a);
1218 continue;
1219 }
1220
1221 RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
1222 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
1223 cell->parameters = c->parameters;
1224 for (auto &conn : c->connections()) {
1225 RTLIL::SigSpec newsig;
1226 for (auto &c : conn.second.chunks()) {
1227 if (c.width == 0)
1228 continue;
1229 log_assert(c.width == 1);
1230 newsig.append(module->wires_[remap_name(c.wire->name)]);
1231 }
1232 cell->setPort(conn.first, newsig);
1233 }
1234 design->select(module, cell);
1235 }
1236
1237 for (auto conn : mapped_mod->connections()) {
1238 if (!conn.first.is_fully_const())
1239 conn.first = RTLIL::SigSpec(module->wires_[remap_name(conn.first.as_wire()->name)]);
1240 if (!conn.second.is_fully_const())
1241 conn.second = RTLIL::SigSpec(module->wires_[remap_name(conn.second.as_wire()->name)]);
1242 module->connect(conn);
1243 }
1244
1245 if (recover_init)
1246 for (auto wire : mapped_mod->wires()) {
1247 if (wire->attributes.count(ID(init))) {
1248 Wire *w = module->wires_[remap_name(wire->name)];
1249 log_assert(w->attributes.count(ID(init)) == 0);
1250 w->attributes[ID(init)] = wire->attributes.at(ID(init));
1251 }
1252 }
1253
1254 for (auto &it : cell_stats)
1255 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
1256 int in_wires = 0, out_wires = 0;
1257 for (auto &si : signal_list)
1258 if (si.is_port) {
1259 char buffer[100];
1260 snprintf(buffer, 100, "\\ys__n%d", si.id);
1261 RTLIL::SigSig conn;
1262 if (si.type != G(NONE)) {
1263 conn.first = si.bit;
1264 conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
1265 out_wires++;
1266 } else {
1267 conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
1268 conn.second = si.bit;
1269 in_wires++;
1270 }
1271 module->connect(conn);
1272 }
1273 log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
1274 log("ABC RESULTS: input signals: %8d\n", in_wires);
1275 log("ABC RESULTS: output signals: %8d\n", out_wires);
1276
1277 delete mapped_design;
1278 }
1279 else
1280 {
1281 log("Don't call ABC as there is nothing to map.\n");
1282 }
1283
1284 if (cleanup)
1285 {
1286 log("Removing temp directory.\n");
1287 remove_directory(tempdir_name);
1288 }
1289
1290 log_pop();
1291 }
1292
1293 struct AbcPass : public Pass {
1294 AbcPass() : Pass("abc", "use ABC for technology mapping") { }
1295 void help() YS_OVERRIDE
1296 {
1297 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1298 log("\n");
1299 log(" abc [options] [selection]\n");
1300 log("\n");
1301 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
1302 log("library to a target architecture.\n");
1303 log("\n");
1304 log(" -exe <command>\n");
1305 #ifdef ABCEXTERNAL
1306 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
1307 #else
1308 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
1309 #endif
1310 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
1311 log("\n");
1312 log(" -script <file>\n");
1313 log(" use the specified ABC script file instead of the default script.\n");
1314 log("\n");
1315 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
1316 log(" string is interpreted as the command string to be passed to ABC. The\n");
1317 log(" leading plus sign is removed and all commas (,) in the string are\n");
1318 log(" replaced with blanks before the string is passed to ABC.\n");
1319 log("\n");
1320 log(" if no -script parameter is given, the following scripts are used:\n");
1321 log("\n");
1322 log(" for -liberty without -constr:\n");
1323 log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
1324 log("\n");
1325 log(" for -liberty with -constr:\n");
1326 log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
1327 log("\n");
1328 log(" for -lut/-luts (only one LUT size):\n");
1329 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
1330 log("\n");
1331 log(" for -lut/-luts (different LUT sizes):\n");
1332 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
1333 log("\n");
1334 log(" for -sop:\n");
1335 log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
1336 log("\n");
1337 log(" otherwise:\n");
1338 log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
1339 log("\n");
1340 log(" -fast\n");
1341 log(" use different default scripts that are slightly faster (at the cost\n");
1342 log(" of output quality):\n");
1343 log("\n");
1344 log(" for -liberty without -constr:\n");
1345 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
1346 log("\n");
1347 log(" for -liberty with -constr:\n");
1348 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
1349 log("\n");
1350 log(" for -lut/-luts:\n");
1351 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
1352 log("\n");
1353 log(" for -sop:\n");
1354 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
1355 log("\n");
1356 log(" otherwise:\n");
1357 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
1358 log("\n");
1359 log(" -liberty <file>\n");
1360 log(" generate netlists for the specified cell library (using the liberty\n");
1361 log(" file format).\n");
1362 log("\n");
1363 log(" -constr <file>\n");
1364 log(" pass this file with timing constraints to ABC. use with -liberty.\n");
1365 log("\n");
1366 log(" a constr file contains two lines:\n");
1367 log(" set_driving_cell <cell_name>\n");
1368 log(" set_load <floating_point_number>\n");
1369 log("\n");
1370 log(" the set_driving_cell statement defines which cell type is assumed to\n");
1371 log(" drive the primary inputs and the set_load statement sets the load in\n");
1372 log(" femtofarads for each primary output.\n");
1373 log("\n");
1374 log(" -D <picoseconds>\n");
1375 log(" set delay target. the string {D} in the default scripts above is\n");
1376 log(" replaced by this option when used, and an empty string otherwise.\n");
1377 log(" this also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
1378 log(" default scripts above.\n");
1379 log("\n");
1380 log(" -I <num>\n");
1381 log(" maximum number of SOP inputs.\n");
1382 log(" (replaces {I} in the default scripts above)\n");
1383 log("\n");
1384 log(" -P <num>\n");
1385 log(" maximum number of SOP products.\n");
1386 log(" (replaces {P} in the default scripts above)\n");
1387 log("\n");
1388 log(" -S <num>\n");
1389 log(" maximum number of LUT inputs shared.\n");
1390 log(" (replaces {S} in the default scripts above, default: -S 1)\n");
1391 log("\n");
1392 log(" -lut <width>\n");
1393 log(" generate netlist using luts of (max) the specified width.\n");
1394 log("\n");
1395 log(" -lut <w1>:<w2>\n");
1396 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
1397 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
1398 log(" the area cost doubles with each additional input bit. the delay cost\n");
1399 log(" is still constant for all lut widths.\n");
1400 log("\n");
1401 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
1402 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
1403 log(" 2, 3, .. inputs.\n");
1404 log("\n");
1405 log(" -sop\n");
1406 log(" map to sum-of-product cells and inverters\n");
1407 log("\n");
1408 // log(" -mux4, -mux8, -mux16\n");
1409 // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
1410 // log(" (ignored when used with -liberty or -lut)\n");
1411 // log("\n");
1412 log(" -g type1,type2,...\n");
1413 log(" Map to the specified list of gate types. Supported gates types are:\n");
1414 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1415 log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,\n");
1416 log(" NMUX, AOI3, OAI3, AOI4, OAI4.\n");
1417 log(" (The NOT gate is always added to this list automatically.)\n");
1418 log("\n");
1419 log(" The following aliases can be used to reference common sets of gate types:\n");
1420 log(" simple: AND OR XOR MUX\n");
1421 log(" cmos2: NAND NOR\n");
1422 log(" cmos3: NAND NOR AOI3 OAI3\n");
1423 log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
1424 log(" cmos: NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR\n");
1425 log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
1426 log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
1427 log("\n");
1428 log(" The alias 'all' represent the full set of all gate types.\n");
1429 log("\n");
1430 log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
1431 log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
1432 log("\n");
1433 log(" The default is 'all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4'.\n");
1434 log("\n");
1435 log(" -dff\n");
1436 log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
1437 log(" clock domains are automatically partitioned in clock domains and each\n");
1438 log(" domain is passed through ABC independently.\n");
1439 log("\n");
1440 log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
1441 log(" use only the specified clock domain. this is like -dff, but only FF\n");
1442 log(" cells that belong to the specified clock domain are used.\n");
1443 log("\n");
1444 log(" -keepff\n");
1445 log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
1446 log(" them, for example for equivalence checking.)\n");
1447 log("\n");
1448 log(" -nocleanup\n");
1449 log(" when this option is used, the temporary files created by this pass\n");
1450 log(" are not removed. this is useful for debugging.\n");
1451 log("\n");
1452 log(" -showtmp\n");
1453 log(" print the temp dir name in log. usually this is suppressed so that the\n");
1454 log(" command output is identical across runs.\n");
1455 log("\n");
1456 log(" -markgroups\n");
1457 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
1458 log(" this attribute is a unique integer for each ABC process started. This\n");
1459 log(" is useful for debugging the partitioning of clock domains.\n");
1460 log("\n");
1461 log(" -dress\n");
1462 log(" run the 'dress' command after all other ABC commands. This aims to\n");
1463 log(" preserve naming by an equivalence check between the original and post-ABC\n");
1464 log(" netlists (experimental).\n");
1465 log("\n");
1466 log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
1467 log("loaded into ABC before the ABC script is executed.\n");
1468 log("\n");
1469 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
1470 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
1471 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
1472 log("output when passing an ABC script that writes a file. Instead write your full\n");
1473 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
1474 log("you want to use ABC to convert your design into another format.\n");
1475 log("\n");
1476 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
1477 log("\n");
1478 }
1479 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1480 {
1481 log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
1482 log_push();
1483
1484 assign_map.clear();
1485 signal_list.clear();
1486 signal_map.clear();
1487 signal_init.clear();
1488 pi_map.clear();
1489 po_map.clear();
1490
1491 #ifdef ABCEXTERNAL
1492 std::string exe_file = ABCEXTERNAL;
1493 #else
1494 std::string exe_file = proc_self_dirname() + "yosys-abc";
1495 #endif
1496 std::string script_file, liberty_file, constr_file, clk_str;
1497 std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
1498 bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
1499 bool show_tempdir = false, sop_mode = false;
1500 bool abc_dress = false;
1501 vector<int> lut_costs;
1502 markgroups = false;
1503
1504 map_mux4 = false;
1505 map_mux8 = false;
1506 map_mux16 = false;
1507 enabled_gates.clear();
1508 cmos_cost = false;
1509
1510 #ifdef _WIN32
1511 #ifndef ABCEXTERNAL
1512 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
1513 exe_file = proc_self_dirname() + "..\\yosys-abc";
1514 #endif
1515 #endif
1516
1517 // get arguments from scratchpad first, then override by command arguments
1518 std::string lut_arg, luts_arg, g_arg;
1519 exe_file = design->scratchpad_get_string("abc.exe", exe_file /* inherit default value if not set */);
1520 script_file = design->scratchpad_get_string("abc.script", script_file);
1521 liberty_file = design->scratchpad_get_string("abc.liberty", liberty_file);
1522 constr_file = design->scratchpad_get_string("abc.constr", constr_file);
1523 if (design->scratchpad.count("abc.D")) {
1524 delay_target = "-D " + design->scratchpad_get_string("abc.D");
1525 }
1526 if (design->scratchpad.count("abc.I")) {
1527 sop_inputs = "-I " + design->scratchpad_get_string("abc.I");
1528 }
1529 if (design->scratchpad.count("abc.P")) {
1530 sop_products = "-P " + design->scratchpad_get_string("abc.P");
1531 }
1532 if (design->scratchpad.count("abc.S")) {
1533 lutin_shared = "-S " + design->scratchpad_get_string("abc.S");
1534 }
1535 lut_arg = design->scratchpad_get_string("abc.lut", lut_arg);
1536 luts_arg = design->scratchpad_get_string("abc.luts", luts_arg);
1537 sop_mode = design->scratchpad_get_bool("abc.sop", sop_mode);
1538 map_mux4 = design->scratchpad_get_bool("abc.mux4", map_mux4);
1539 map_mux8 = design->scratchpad_get_bool("abc.mux8", map_mux8);
1540 map_mux16 = design->scratchpad_get_bool("abc.mux16", map_mux16);
1541 abc_dress = design->scratchpad_get_bool("abc.dress", abc_dress);
1542 g_arg = design->scratchpad_get_string("abc.g", g_arg);
1543
1544 fast_mode = design->scratchpad_get_bool("abc.fast", fast_mode);
1545 dff_mode = design->scratchpad_get_bool("abc.dff", dff_mode);
1546 if (design->scratchpad.count("abc.clk")) {
1547 clk_str = design->scratchpad_get_string("abc.clk");
1548 dff_mode = true;
1549 }
1550 keepff = design->scratchpad_get_bool("abc.keepff", keepff);
1551 cleanup = !design->scratchpad_get_bool("abc.nocleanup", !cleanup);
1552 keepff = design->scratchpad_get_bool("abc.keepff", keepff);
1553 show_tempdir = design->scratchpad_get_bool("abc.showtmp", show_tempdir);
1554 markgroups = design->scratchpad_get_bool("abc.markgroups", markgroups);
1555
1556 size_t argidx, g_argidx;
1557 bool g_arg_from_cmd = false;
1558 char pwd [PATH_MAX];
1559 if (!getcwd(pwd, sizeof(pwd))) {
1560 log_cmd_error("getcwd failed: %s\n", strerror(errno));
1561 log_abort();
1562 }
1563 for (argidx = 1; argidx < args.size(); argidx++) {
1564 std::string arg = args[argidx];
1565 if (arg == "-exe" && argidx+1 < args.size()) {
1566 exe_file = args[++argidx];
1567 continue;
1568 }
1569 if (arg == "-script" && argidx+1 < args.size()) {
1570 script_file = args[++argidx];
1571 continue;
1572 }
1573 if (arg == "-liberty" && argidx+1 < args.size()) {
1574 liberty_file = args[++argidx];
1575 continue;
1576 }
1577 if (arg == "-constr" && argidx+1 < args.size()) {
1578 constr_file = args[++argidx];
1579 continue;
1580 }
1581 if (arg == "-D" && argidx+1 < args.size()) {
1582 delay_target = "-D " + args[++argidx];
1583 continue;
1584 }
1585 if (arg == "-I" && argidx+1 < args.size()) {
1586 sop_inputs = "-I " + args[++argidx];
1587 continue;
1588 }
1589 if (arg == "-P" && argidx+1 < args.size()) {
1590 sop_products = "-P " + args[++argidx];
1591 continue;
1592 }
1593 if (arg == "-S" && argidx+1 < args.size()) {
1594 lutin_shared = "-S " + args[++argidx];
1595 continue;
1596 }
1597 if (arg == "-lut" && argidx+1 < args.size()) {
1598 lut_arg = args[++argidx];
1599 continue;
1600 }
1601 if (arg == "-luts" && argidx+1 < args.size()) {
1602 luts_arg = args[++argidx];
1603 continue;
1604 }
1605 if (arg == "-sop") {
1606 sop_mode = true;
1607 continue;
1608 }
1609 if (arg == "-mux4") {
1610 map_mux4 = true;
1611 continue;
1612 }
1613 if (arg == "-mux8") {
1614 map_mux8 = true;
1615 continue;
1616 }
1617 if (arg == "-mux16") {
1618 map_mux16 = true;
1619 continue;
1620 }
1621 if (arg == "-dress") {
1622 abc_dress = true;
1623 continue;
1624 }
1625 if (arg == "-g" && argidx+1 < args.size()) {
1626 if (g_arg_from_cmd)
1627 log_cmd_error("Can only use -g once. Please combine.");
1628 g_arg = args[++argidx];
1629 g_argidx = argidx;
1630 g_arg_from_cmd = true;
1631 continue;
1632 }
1633 if (arg == "-fast") {
1634 fast_mode = true;
1635 continue;
1636 }
1637 if (arg == "-dff") {
1638 dff_mode = true;
1639 continue;
1640 }
1641 if (arg == "-clk" && argidx+1 < args.size()) {
1642 clk_str = args[++argidx];
1643 dff_mode = true;
1644 continue;
1645 }
1646 if (arg == "-keepff") {
1647 keepff = true;
1648 continue;
1649 }
1650 if (arg == "-nocleanup") {
1651 cleanup = false;
1652 continue;
1653 }
1654 if (arg == "-showtmp") {
1655 show_tempdir = true;
1656 continue;
1657 }
1658 if (arg == "-markgroups") {
1659 markgroups = true;
1660 continue;
1661 }
1662 break;
1663 }
1664 extra_args(args, argidx, design);
1665
1666 rewrite_filename(script_file);
1667 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
1668 script_file = std::string(pwd) + "/" + script_file;
1669 rewrite_filename(liberty_file);
1670 if (!liberty_file.empty() && !is_absolute_path(liberty_file))
1671 liberty_file = std::string(pwd) + "/" + liberty_file;
1672 rewrite_filename(constr_file);
1673 if (!constr_file.empty() && !is_absolute_path(constr_file))
1674 constr_file = std::string(pwd) + "/" + constr_file;
1675
1676 // handle -lut argument
1677 if (!lut_arg.empty()) {
1678 size_t pos = lut_arg.find_first_of(':');
1679 int lut_mode = 0, lut_mode2 = 0;
1680 if (pos != string::npos) {
1681 lut_mode = atoi(lut_arg.substr(0, pos).c_str());
1682 lut_mode2 = atoi(lut_arg.substr(pos+1).c_str());
1683 } else {
1684 lut_mode = atoi(lut_arg.c_str());
1685 lut_mode2 = lut_mode;
1686 }
1687 lut_costs.clear();
1688 for (int i = 0; i < lut_mode; i++)
1689 lut_costs.push_back(1);
1690 for (int i = lut_mode; i < lut_mode2; i++)
1691 lut_costs.push_back(2 << (i - lut_mode));
1692 }
1693 //handle -luts argument
1694 if (!luts_arg.empty()){
1695 lut_costs.clear();
1696 for (auto &tok : split_tokens(luts_arg, ",")) {
1697 auto parts = split_tokens(tok, ":");
1698 if (GetSize(parts) == 0 && !lut_costs.empty())
1699 lut_costs.push_back(lut_costs.back());
1700 else if (GetSize(parts) == 1)
1701 lut_costs.push_back(atoi(parts.at(0).c_str()));
1702 else if (GetSize(parts) == 2)
1703 while (GetSize(lut_costs) < std::atoi(parts.at(0).c_str()))
1704 lut_costs.push_back(atoi(parts.at(1).c_str()));
1705 else
1706 log_cmd_error("Invalid -luts syntax.\n");
1707 }
1708 }
1709
1710 // handle -g argument
1711 if (!g_arg.empty()){
1712 for (auto g : split_tokens(g_arg, ",")) {
1713 vector<string> gate_list;
1714 bool remove_gates = false;
1715 if (GetSize(g) > 0 && g[0] == '-') {
1716 remove_gates = true;
1717 g = g.substr(1);
1718 }
1719 if (g == "AND") goto ok_gate;
1720 if (g == "NAND") goto ok_gate;
1721 if (g == "OR") goto ok_gate;
1722 if (g == "NOR") goto ok_gate;
1723 if (g == "XOR") goto ok_gate;
1724 if (g == "XNOR") goto ok_gate;
1725 if (g == "ANDNOT") goto ok_gate;
1726 if (g == "ORNOT") goto ok_gate;
1727 if (g == "MUX") goto ok_gate;
1728 if (g == "NMUX") goto ok_gate;
1729 if (g == "AOI3") goto ok_gate;
1730 if (g == "OAI3") goto ok_gate;
1731 if (g == "AOI4") goto ok_gate;
1732 if (g == "OAI4") goto ok_gate;
1733 if (g == "simple") {
1734 gate_list.push_back("AND");
1735 gate_list.push_back("OR");
1736 gate_list.push_back("XOR");
1737 gate_list.push_back("MUX");
1738 goto ok_alias;
1739 }
1740 if (g == "cmos2") {
1741 if (!remove_gates)
1742 cmos_cost = true;
1743 gate_list.push_back("NAND");
1744 gate_list.push_back("NOR");
1745 goto ok_alias;
1746 }
1747 if (g == "cmos3") {
1748 if (!remove_gates)
1749 cmos_cost = true;
1750 gate_list.push_back("NAND");
1751 gate_list.push_back("NOR");
1752 gate_list.push_back("AOI3");
1753 gate_list.push_back("OAI3");
1754 goto ok_alias;
1755 }
1756 if (g == "cmos4") {
1757 if (!remove_gates)
1758 cmos_cost = true;
1759 gate_list.push_back("NAND");
1760 gate_list.push_back("NOR");
1761 gate_list.push_back("AOI3");
1762 gate_list.push_back("OAI3");
1763 gate_list.push_back("AOI4");
1764 gate_list.push_back("OAI4");
1765 goto ok_alias;
1766 }
1767 if (g == "cmos") {
1768 if (!remove_gates)
1769 cmos_cost = true;
1770 gate_list.push_back("NAND");
1771 gate_list.push_back("NOR");
1772 gate_list.push_back("AOI3");
1773 gate_list.push_back("OAI3");
1774 gate_list.push_back("AOI4");
1775 gate_list.push_back("OAI4");
1776 gate_list.push_back("NMUX");
1777 gate_list.push_back("MUX");
1778 gate_list.push_back("XOR");
1779 gate_list.push_back("XNOR");
1780 goto ok_alias;
1781 }
1782 if (g == "gates") {
1783 gate_list.push_back("AND");
1784 gate_list.push_back("NAND");
1785 gate_list.push_back("OR");
1786 gate_list.push_back("NOR");
1787 gate_list.push_back("XOR");
1788 gate_list.push_back("XNOR");
1789 gate_list.push_back("ANDNOT");
1790 gate_list.push_back("ORNOT");
1791 goto ok_alias;
1792 }
1793 if (g == "aig") {
1794 gate_list.push_back("AND");
1795 gate_list.push_back("NAND");
1796 gate_list.push_back("OR");
1797 gate_list.push_back("NOR");
1798 gate_list.push_back("ANDNOT");
1799 gate_list.push_back("ORNOT");
1800 goto ok_alias;
1801 }
1802 if (g == "all") {
1803 gate_list.push_back("AND");
1804 gate_list.push_back("NAND");
1805 gate_list.push_back("OR");
1806 gate_list.push_back("NOR");
1807 gate_list.push_back("XOR");
1808 gate_list.push_back("XNOR");
1809 gate_list.push_back("ANDNOT");
1810 gate_list.push_back("ORNOT");
1811 gate_list.push_back("AOI3");
1812 gate_list.push_back("OAI3");
1813 gate_list.push_back("AOI4");
1814 gate_list.push_back("OAI4");
1815 gate_list.push_back("MUX");
1816 gate_list.push_back("NMUX");
1817 }
1818 if (g_arg_from_cmd)
1819 cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g.c_str()));
1820 else
1821 log_cmd_error("Unsupported gate type: %s", g.c_str());
1822 ok_gate:
1823 gate_list.push_back(g);
1824 ok_alias:
1825 for (auto gate : gate_list) {
1826 if (remove_gates)
1827 enabled_gates.erase(gate);
1828 else
1829 enabled_gates.insert(gate);
1830 }
1831 }
1832 }
1833
1834 if (!lut_costs.empty() && !liberty_file.empty())
1835 log_cmd_error("Got -lut and -liberty! These two options are exclusive.\n");
1836 if (!constr_file.empty() && liberty_file.empty())
1837 log_cmd_error("Got -constr but no -liberty!\n");
1838
1839 if (enabled_gates.empty()) {
1840 enabled_gates.insert("AND");
1841 enabled_gates.insert("NAND");
1842 enabled_gates.insert("OR");
1843 enabled_gates.insert("NOR");
1844 enabled_gates.insert("XOR");
1845 enabled_gates.insert("XNOR");
1846 enabled_gates.insert("ANDNOT");
1847 enabled_gates.insert("ORNOT");
1848 // enabled_gates.insert("AOI3");
1849 // enabled_gates.insert("OAI3");
1850 // enabled_gates.insert("AOI4");
1851 // enabled_gates.insert("OAI4");
1852 enabled_gates.insert("MUX");
1853 // enabled_gates.insert("NMUX");
1854 }
1855
1856 for (auto mod : design->selected_modules())
1857 {
1858 if (mod->processes.size() > 0) {
1859 log("Skipping module %s as it contains processes.\n", log_id(mod));
1860 continue;
1861 }
1862
1863 assign_map.set(mod);
1864 signal_init.clear();
1865
1866 for (Wire *wire : mod->wires())
1867 if (wire->attributes.count(ID(init))) {
1868 SigSpec initsig = assign_map(wire);
1869 Const initval = wire->attributes.at(ID(init));
1870 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
1871 switch (initval[i]) {
1872 case State::S0:
1873 signal_init[initsig[i]] = State::S0;
1874 break;
1875 case State::S1:
1876 signal_init[initsig[i]] = State::S1;
1877 break;
1878 default:
1879 break;
1880 }
1881 }
1882
1883 if (!dff_mode || !clk_str.empty()) {
1884 abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
1885 delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress);
1886 continue;
1887 }
1888
1889 CellTypes ct(design);
1890
1891 std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
1892 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1893
1894 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1895 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1896 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1897
1898 typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
1899 std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
1900 std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
1901
1902 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1903 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1904
1905 for (auto cell : all_cells)
1906 {
1907 clkdomain_t key;
1908
1909 for (auto &conn : cell->connections())
1910 for (auto bit : conn.second) {
1911 bit = assign_map(bit);
1912 if (bit.wire != nullptr) {
1913 cell_to_bit[cell].insert(bit);
1914 bit_to_cell[bit].insert(cell);
1915 if (ct.cell_input(cell->type, conn.first)) {
1916 cell_to_bit_up[cell].insert(bit);
1917 bit_to_cell_down[bit].insert(cell);
1918 }
1919 if (ct.cell_output(cell->type, conn.first)) {
1920 cell_to_bit_down[cell].insert(bit);
1921 bit_to_cell_up[bit].insert(cell);
1922 }
1923 }
1924 }
1925
1926 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1927 {
1928 key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
1929 }
1930 else
1931 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1932 {
1933 bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
1934 bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
1935 key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
1936 }
1937 else
1938 continue;
1939
1940 unassigned_cells.erase(cell);
1941 expand_queue.insert(cell);
1942 expand_queue_up.insert(cell);
1943 expand_queue_down.insert(cell);
1944
1945 assigned_cells[key].push_back(cell);
1946 assigned_cells_reverse[cell] = key;
1947 }
1948
1949 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1950 {
1951 if (!expand_queue_up.empty())
1952 {
1953 RTLIL::Cell *cell = *expand_queue_up.begin();
1954 clkdomain_t key = assigned_cells_reverse.at(cell);
1955 expand_queue_up.erase(cell);
1956
1957 for (auto bit : cell_to_bit_up[cell])
1958 for (auto c : bit_to_cell_up[bit])
1959 if (unassigned_cells.count(c)) {
1960 unassigned_cells.erase(c);
1961 next_expand_queue_up.insert(c);
1962 assigned_cells[key].push_back(c);
1963 assigned_cells_reverse[c] = key;
1964 expand_queue.insert(c);
1965 }
1966 }
1967
1968 if (!expand_queue_down.empty())
1969 {
1970 RTLIL::Cell *cell = *expand_queue_down.begin();
1971 clkdomain_t key = assigned_cells_reverse.at(cell);
1972 expand_queue_down.erase(cell);
1973
1974 for (auto bit : cell_to_bit_down[cell])
1975 for (auto c : bit_to_cell_down[bit])
1976 if (unassigned_cells.count(c)) {
1977 unassigned_cells.erase(c);
1978 next_expand_queue_up.insert(c);
1979 assigned_cells[key].push_back(c);
1980 assigned_cells_reverse[c] = key;
1981 expand_queue.insert(c);
1982 }
1983 }
1984
1985 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1986 expand_queue_up.swap(next_expand_queue_up);
1987 expand_queue_down.swap(next_expand_queue_down);
1988 }
1989 }
1990
1991 while (!expand_queue.empty())
1992 {
1993 RTLIL::Cell *cell = *expand_queue.begin();
1994 clkdomain_t key = assigned_cells_reverse.at(cell);
1995 expand_queue.erase(cell);
1996
1997 for (auto bit : cell_to_bit.at(cell)) {
1998 for (auto c : bit_to_cell[bit])
1999 if (unassigned_cells.count(c)) {
2000 unassigned_cells.erase(c);
2001 next_expand_queue.insert(c);
2002 assigned_cells[key].push_back(c);
2003 assigned_cells_reverse[c] = key;
2004 }
2005 bit_to_cell[bit].clear();
2006 }
2007
2008 if (expand_queue.empty())
2009 expand_queue.swap(next_expand_queue);
2010 }
2011
2012 clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
2013 for (auto cell : unassigned_cells) {
2014 assigned_cells[key].push_back(cell);
2015 assigned_cells_reverse[cell] = key;
2016 }
2017
2018 log_header(design, "Summary of detected clock domains:\n");
2019 for (auto &it : assigned_cells)
2020 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
2021 std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
2022 std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
2023
2024 for (auto &it : assigned_cells) {
2025 clk_polarity = std::get<0>(it.first);
2026 clk_sig = assign_map(std::get<1>(it.first));
2027 en_polarity = std::get<2>(it.first);
2028 en_sig = assign_map(std::get<3>(it.first));
2029 abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
2030 keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
2031 assign_map.set(mod);
2032 }
2033 }
2034
2035 assign_map.clear();
2036 signal_list.clear();
2037 signal_map.clear();
2038 signal_init.clear();
2039 pi_map.clear();
2040 po_map.clear();
2041
2042 log_pop();
2043 }
2044 } AbcPass;
2045
2046 PRIVATE_NAMESPACE_END