afde01cfa96e3d43f68ada2dab888013caea0d81
2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
22 // http://www.eecs.berkeley.edu/~alanmi/abc/
24 // [[CITE]] Berkeley Logic Interchange Format (BLIF)
25 // University of California. Berkeley. July 28, 1992
26 // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
28 // [[CITE]] Kahn's Topological sorting algorithm
29 // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
30 // http://en.wikipedia.org/wiki/Topological_sorting
32 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
33 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
34 #define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; if; mfs2"
35 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; cover {I} {P}"
36 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
38 #define ABC_FAST_COMMAND_LIB "strash; dretime; retime {D}; map {D}"
39 #define ABC_FAST_COMMAND_CTR "strash; dretime; retime {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
40 #define ABC_FAST_COMMAND_LUT "strash; dretime; retime {D}; if"
41 #define ABC_FAST_COMMAND_SOP "strash; dretime; retime {D}; cover -I {I} -P {P}"
42 #define ABC_FAST_COMMAND_DFL "strash; dretime; retime {D}; map"
44 #include "kernel/register.h"
45 #include "kernel/sigtools.h"
46 #include "kernel/celltypes.h"
47 #include "kernel/cost.h"
48 #include "kernel/log.h"
62 #include "frontends/blif/blifparse.h"
65 extern "C" int Abc_RealMain(int argc
, char *argv
[]);
69 PRIVATE_NAMESPACE_BEGIN
71 enum class gate_type_t
{
92 #define G(_name) gate_type_t::G_ ## _name
98 int in1
, in2
, in3
, in4
;
111 RTLIL::Module
*module
;
112 std::vector
<gate_t
> signal_list
;
113 std::map
<RTLIL::SigBit
, int> signal_map
;
114 std::map
<RTLIL::SigBit
, RTLIL::State
> signal_init
;
115 pool
<std::string
> enabled_gates
;
116 bool recover_init
, cmos_cost
;
118 bool clk_polarity
, en_polarity
;
119 RTLIL::SigSpec clk_sig
, en_sig
;
120 dict
<int, std::string
> pi_map
, po_map
;
122 int map_signal(RTLIL::SigBit bit
, gate_type_t gate_type
= G(NONE
), int in1
= -1, int in2
= -1, int in3
= -1, int in4
= -1)
124 assign_map
.apply(bit
);
126 if (signal_map
.count(bit
) == 0) {
128 gate
.id
= signal_list
.size();
134 gate
.is_port
= false;
136 if (signal_init
.count(bit
))
137 gate
.init
= signal_init
.at(bit
);
139 gate
.init
= State::Sx
;
140 signal_list
.push_back(gate
);
141 signal_map
[bit
] = gate
.id
;
144 gate_t
&gate
= signal_list
[signal_map
[bit
]];
146 if (gate_type
!= G(NONE
))
147 gate
.type
= gate_type
;
160 void mark_port(RTLIL::SigSpec sig
)
162 for (auto &bit
: assign_map(sig
))
163 if (bit
.wire
!= NULL
&& signal_map
.count(bit
) > 0)
164 signal_list
[signal_map
[bit
]].is_port
= true;
167 void extract_cell(RTLIL::Cell
*cell
, bool keepff
)
169 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
171 if (clk_polarity
!= (cell
->type
== ID($_DFF_P_
)))
173 if (clk_sig
!= assign_map(cell
->getPort("\\C")))
175 if (GetSize(en_sig
) != 0)
180 if (cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
182 if (clk_polarity
!= cell
->type
.in(ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
184 if (en_polarity
!= cell
->type
.in(ID($_DFFE_NP_
), ID($_DFFE_PP_
)))
186 if (clk_sig
!= assign_map(cell
->getPort("\\C")))
188 if (en_sig
!= assign_map(cell
->getPort("\\E")))
195 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
196 RTLIL::SigSpec sig_q
= cell
->getPort("\\Q");
199 for (auto &c
: sig_q
.chunks())
201 c
.wire
->attributes
["\\keep"] = 1;
203 assign_map
.apply(sig_d
);
204 assign_map
.apply(sig_q
);
206 map_signal(sig_q
, G(FF
), map_signal(sig_d
));
208 module
->remove(cell
);
212 if (cell
->type
.in(ID($_BUF_
), ID($_NOT_
)))
214 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
215 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
217 assign_map
.apply(sig_a
);
218 assign_map
.apply(sig_y
);
220 map_signal(sig_y
, cell
->type
== ID($_BUF_
) ? G(BUF
) : G(NOT
), map_signal(sig_a
));
222 module
->remove(cell
);
226 if (cell
->type
.in(ID($_AND_
), ID($_NAND_
), ID($_OR_
), ID($_NOR_
), ID($_XOR_
), ID($_XNOR_
), ID($_ANDNOT_
), ID($_ORNOT_
)))
228 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
229 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
230 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
232 assign_map
.apply(sig_a
);
233 assign_map
.apply(sig_b
);
234 assign_map
.apply(sig_y
);
236 int mapped_a
= map_signal(sig_a
);
237 int mapped_b
= map_signal(sig_b
);
239 if (cell
->type
== ID($_AND_
))
240 map_signal(sig_y
, G(AND
), mapped_a
, mapped_b
);
241 else if (cell
->type
== ID($_NAND_
))
242 map_signal(sig_y
, G(NAND
), mapped_a
, mapped_b
);
243 else if (cell
->type
== ID($_OR_
))
244 map_signal(sig_y
, G(OR
), mapped_a
, mapped_b
);
245 else if (cell
->type
== ID($_NOR_
))
246 map_signal(sig_y
, G(NOR
), mapped_a
, mapped_b
);
247 else if (cell
->type
== ID($_XOR_
))
248 map_signal(sig_y
, G(XOR
), mapped_a
, mapped_b
);
249 else if (cell
->type
== ID($_XNOR_
))
250 map_signal(sig_y
, G(XNOR
), mapped_a
, mapped_b
);
251 else if (cell
->type
== ID($_ANDNOT_
))
252 map_signal(sig_y
, G(ANDNOT
), mapped_a
, mapped_b
);
253 else if (cell
->type
== ID($_ORNOT_
))
254 map_signal(sig_y
, G(ORNOT
), mapped_a
, mapped_b
);
258 module
->remove(cell
);
262 if (cell
->type
.in(ID($_MUX_
), ID($_NMUX_
)))
264 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
265 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
266 RTLIL::SigSpec sig_s
= cell
->getPort("\\S");
267 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
269 assign_map
.apply(sig_a
);
270 assign_map
.apply(sig_b
);
271 assign_map
.apply(sig_s
);
272 assign_map
.apply(sig_y
);
274 int mapped_a
= map_signal(sig_a
);
275 int mapped_b
= map_signal(sig_b
);
276 int mapped_s
= map_signal(sig_s
);
278 map_signal(sig_y
, cell
->type
== ID($_MUX_
) ? G(MUX
) : G(NMUX
), mapped_a
, mapped_b
, mapped_s
);
280 module
->remove(cell
);
284 if (cell
->type
.in(ID($_AOI3_
), ID($_OAI3_
)))
286 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
287 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
288 RTLIL::SigSpec sig_c
= cell
->getPort("\\C");
289 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
291 assign_map
.apply(sig_a
);
292 assign_map
.apply(sig_b
);
293 assign_map
.apply(sig_c
);
294 assign_map
.apply(sig_y
);
296 int mapped_a
= map_signal(sig_a
);
297 int mapped_b
= map_signal(sig_b
);
298 int mapped_c
= map_signal(sig_c
);
300 map_signal(sig_y
, cell
->type
== ID($_AOI3_
) ? G(AOI3
) : G(OAI3
), mapped_a
, mapped_b
, mapped_c
);
302 module
->remove(cell
);
306 if (cell
->type
.in(ID($_AOI4_
), ID($_OAI4_
)))
308 RTLIL::SigSpec sig_a
= cell
->getPort("\\A");
309 RTLIL::SigSpec sig_b
= cell
->getPort("\\B");
310 RTLIL::SigSpec sig_c
= cell
->getPort("\\C");
311 RTLIL::SigSpec sig_d
= cell
->getPort("\\D");
312 RTLIL::SigSpec sig_y
= cell
->getPort("\\Y");
314 assign_map
.apply(sig_a
);
315 assign_map
.apply(sig_b
);
316 assign_map
.apply(sig_c
);
317 assign_map
.apply(sig_d
);
318 assign_map
.apply(sig_y
);
320 int mapped_a
= map_signal(sig_a
);
321 int mapped_b
= map_signal(sig_b
);
322 int mapped_c
= map_signal(sig_c
);
323 int mapped_d
= map_signal(sig_d
);
325 map_signal(sig_y
, cell
->type
== ID($_AOI4_
) ? G(AOI4
) : G(OAI4
), mapped_a
, mapped_b
, mapped_c
, mapped_d
);
327 module
->remove(cell
);
332 std::string
remap_name(RTLIL::IdString abc_name
, RTLIL::Wire
**orig_wire
= nullptr)
334 std::string abc_sname
= abc_name
.substr(1);
336 if (abc_sname
.compare(0, 4, "new_") == 0)
338 abc_sname
.erase(0, 4);
341 if (abc_sname
.compare(0, 5, "ys__n") == 0)
343 abc_sname
.erase(0, 5);
344 if (std::isdigit(abc_sname
.at(0)))
346 int sid
= std::atoi(abc_sname
.c_str());
347 size_t postfix_start
= abc_sname
.find_first_not_of("0123456789");
348 std::string postfix
= postfix_start
!= std::string::npos
? abc_sname
.substr(postfix_start
) : "";
350 if (sid
< GetSize(signal_list
))
352 auto sig
= signal_list
.at(sid
);
353 if (sig
.bit
.wire
!= nullptr)
355 std::string s
= stringf("$abc$%d$%s", map_autoidx
, sig
.bit
.wire
->name
.c_str()+1);
356 if (sig
.bit
.wire
->width
!= 1)
357 s
+= stringf("[%d]", sig
.bit
.offset
);
361 if (orig_wire
!= nullptr)
362 *orig_wire
= sig
.bit
.wire
;
368 return stringf("$abc$%d$%s", map_autoidx
, abc_name
.c_str()+1);
371 void dump_loop_graph(FILE *f
, int &nr
, std::map
<int, std::set
<int>> &edges
, std::set
<int> &workpool
, std::vector
<int> &in_counts
)
376 log("Dumping loop state graph to slide %d.\n", ++nr
);
378 fprintf(f
, "digraph \"slide%d\" {\n", nr
);
379 fprintf(f
, " label=\"slide%d\";\n", nr
);
380 fprintf(f
, " rankdir=\"TD\";\n");
383 for (auto &e
: edges
) {
384 nodes
.insert(e
.first
);
385 for (auto n
: e
.second
)
390 fprintf(f
, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n
, log_signal(signal_list
[n
].bit
),
391 n
, in_counts
[n
], workpool
.count(n
) ? ", shape=box" : "");
393 for (auto &e
: edges
)
394 for (auto n
: e
.second
)
395 fprintf(f
, " ys__n%d -> ys__n%d;\n", e
.first
, n
);
402 // http://en.wikipedia.org/wiki/Topological_sorting
403 // (Kahn, Arthur B. (1962), "Topological sorting of large networks")
405 std::map
<int, std::set
<int>> edges
;
406 std::vector
<int> in_edges_count(signal_list
.size());
407 std::set
<int> workpool
;
412 // uncomment for troubleshooting the loop detection code
413 // dot_f = fopen("test.dot", "w");
415 for (auto &g
: signal_list
) {
416 if (g
.type
== G(NONE
) || g
.type
== G(FF
)) {
417 workpool
.insert(g
.id
);
420 edges
[g
.in1
].insert(g
.id
);
421 in_edges_count
[g
.id
]++;
423 if (g
.in2
>= 0 && g
.in2
!= g
.in1
) {
424 edges
[g
.in2
].insert(g
.id
);
425 in_edges_count
[g
.id
]++;
427 if (g
.in3
>= 0 && g
.in3
!= g
.in2
&& g
.in3
!= g
.in1
) {
428 edges
[g
.in3
].insert(g
.id
);
429 in_edges_count
[g
.id
]++;
431 if (g
.in4
>= 0 && g
.in4
!= g
.in3
&& g
.in4
!= g
.in2
&& g
.in4
!= g
.in1
) {
432 edges
[g
.in4
].insert(g
.id
);
433 in_edges_count
[g
.id
]++;
438 dump_loop_graph(dot_f
, dot_nr
, edges
, workpool
, in_edges_count
);
440 while (workpool
.size() > 0)
442 int id
= *workpool
.begin();
445 // log("Removing non-loop node %d from graph: %s\n", id, log_signal(signal_list[id].bit));
447 for (int id2
: edges
[id
]) {
448 log_assert(in_edges_count
[id2
] > 0);
449 if (--in_edges_count
[id2
] == 0)
450 workpool
.insert(id2
);
454 dump_loop_graph(dot_f
, dot_nr
, edges
, workpool
, in_edges_count
);
456 while (workpool
.size() == 0)
458 if (edges
.size() == 0)
461 int id1
= edges
.begin()->first
;
463 for (auto &edge_it
: edges
) {
464 int id2
= edge_it
.first
;
465 RTLIL::Wire
*w1
= signal_list
[id1
].bit
.wire
;
466 RTLIL::Wire
*w2
= signal_list
[id2
].bit
.wire
;
471 else if (w1
->name
[0] == '$' && w2
->name
[0] == '\\')
473 else if (w1
->name
[0] == '\\' && w2
->name
[0] == '$')
475 else if (edges
[id1
].size() < edges
[id2
].size())
477 else if (edges
[id1
].size() > edges
[id2
].size())
479 else if (w2
->name
.str() < w1
->name
.str())
483 if (edges
[id1
].size() == 0) {
488 log_assert(signal_list
[id1
].bit
.wire
!= NULL
);
490 std::stringstream sstr
;
491 sstr
<< "$abcloop$" << (autoidx
++);
492 RTLIL::Wire
*wire
= module
->addWire(sstr
.str());
494 bool first_line
= true;
495 for (int id2
: edges
[id1
]) {
497 log("Breaking loop using new signal %s: %s -> %s\n", log_signal(RTLIL::SigSpec(wire
)),
498 log_signal(signal_list
[id1
].bit
), log_signal(signal_list
[id2
].bit
));
500 log(" %*s %s -> %s\n", int(strlen(log_signal(RTLIL::SigSpec(wire
)))), "",
501 log_signal(signal_list
[id1
].bit
), log_signal(signal_list
[id2
].bit
));
505 int id3
= map_signal(RTLIL::SigSpec(wire
));
506 signal_list
[id1
].is_port
= true;
507 signal_list
[id3
].is_port
= true;
508 log_assert(id3
== int(in_edges_count
.size()));
509 in_edges_count
.push_back(0);
510 workpool
.insert(id3
);
512 for (int id2
: edges
[id1
]) {
513 if (signal_list
[id2
].in1
== id1
)
514 signal_list
[id2
].in1
= id3
;
515 if (signal_list
[id2
].in2
== id1
)
516 signal_list
[id2
].in2
= id3
;
517 if (signal_list
[id2
].in3
== id1
)
518 signal_list
[id2
].in3
= id3
;
519 if (signal_list
[id2
].in4
== id1
)
520 signal_list
[id2
].in4
= id3
;
522 edges
[id1
].swap(edges
[id3
]);
524 module
->connect(RTLIL::SigSig(signal_list
[id3
].bit
, signal_list
[id1
].bit
));
525 dump_loop_graph(dot_f
, dot_nr
, edges
, workpool
, in_edges_count
);
533 std::string
add_echos_to_abc_cmd(std::string str
)
535 std::string new_str
, token
;
536 for (size_t i
= 0; i
< str
.size(); i
++) {
539 while (i
+1 < str
.size() && str
[i
+1] == ' ')
541 new_str
+= "echo + " + token
+ " " + token
+ " ";
546 if (!token
.empty()) {
547 if (!new_str
.empty())
548 new_str
+= "echo + " + token
+ "; ";
555 std::string
fold_abc_cmd(std::string str
)
557 std::string token
, new_str
= " ";
558 int char_counter
= 10;
560 for (size_t i
= 0; i
<= str
.size(); i
++) {
563 if (i
== str
.size() || str
[i
] == ';') {
564 if (char_counter
+ token
.size() > 75)
565 new_str
+= "\n ", char_counter
= 14;
566 new_str
+= token
, char_counter
+= token
.size();
574 std::string
replace_tempdir(std::string text
, std::string tempdir_name
, bool show_tempdir
)
580 size_t pos
= text
.find(tempdir_name
);
581 if (pos
== std::string::npos
)
583 text
= text
.substr(0, pos
) + "<abc-temp-dir>" + text
.substr(pos
+ GetSize(tempdir_name
));
586 std::string selfdir_name
= proc_self_dirname();
587 if (selfdir_name
!= "/") {
589 size_t pos
= text
.find(selfdir_name
);
590 if (pos
== std::string::npos
)
592 text
= text
.substr(0, pos
) + "<yosys-exe-dir>/" + text
.substr(pos
+ GetSize(selfdir_name
));
599 struct abc_output_filter
602 int escape_seq_state
;
604 std::string tempdir_name
;
607 abc_output_filter(std::string tempdir_name
, bool show_tempdir
) : tempdir_name(tempdir_name
), show_tempdir(show_tempdir
)
610 escape_seq_state
= 0;
613 void next_char(char ch
)
615 if (escape_seq_state
== 0 && ch
== '\033') {
616 escape_seq_state
= 1;
619 if (escape_seq_state
== 1) {
620 escape_seq_state
= ch
== '[' ? 2 : 0;
623 if (escape_seq_state
== 2) {
624 if ((ch
< '0' || '9' < ch
) && ch
!= ';')
625 escape_seq_state
= 0;
628 escape_seq_state
= 0;
634 log("ABC: %s\n", replace_tempdir(linebuf
, tempdir_name
, show_tempdir
).c_str());
635 got_cr
= false, linebuf
.clear();
639 got_cr
= false, linebuf
.clear();
643 void next_line(const std::string
&line
)
646 if (sscanf(line
.c_str(), "Start-point = pi%d. End-point = po%d.", &pi
, &po
) == 2) {
647 log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
648 pi
, pi_map
.count(pi
) ? pi_map
.at(pi
).c_str() : "???",
649 po
, po_map
.count(po
) ? po_map
.at(po
).c_str() : "???");
658 void abc_module(RTLIL::Design
*design
, RTLIL::Module
*current_module
, std::string script_file
, std::string exe_file
,
659 std::string liberty_file
, std::string constr_file
, bool cleanup
, vector
<int> lut_costs
, bool dff_mode
, std::string clk_str
,
660 bool keepff
, std::string delay_target
, std::string sop_inputs
, std::string sop_products
, std::string lutin_shared
, bool fast_mode
,
661 const std::vector
<RTLIL::Cell
*> &cells
, bool show_tempdir
, bool sop_mode
, bool abc_dress
)
663 module
= current_module
;
664 map_autoidx
= autoidx
++;
670 recover_init
= false;
675 clk_sig
= RTLIL::SigSpec();
678 en_sig
= RTLIL::SigSpec();
681 if (!clk_str
.empty() && clk_str
!= "$")
683 if (clk_str
.find(',') != std::string::npos
) {
684 int pos
= clk_str
.find(',');
685 std::string en_str
= clk_str
.substr(pos
+1);
686 clk_str
= clk_str
.substr(0, pos
);
687 if (en_str
[0] == '!') {
689 en_str
= en_str
.substr(1);
691 if (module
->wires_
.count(RTLIL::escape_id(en_str
)) != 0)
692 en_sig
= assign_map(RTLIL::SigSpec(module
->wires_
.at(RTLIL::escape_id(en_str
)), 0));
694 if (clk_str
[0] == '!') {
695 clk_polarity
= false;
696 clk_str
= clk_str
.substr(1);
698 if (module
->wires_
.count(RTLIL::escape_id(clk_str
)) != 0)
699 clk_sig
= assign_map(RTLIL::SigSpec(module
->wires_
.at(RTLIL::escape_id(clk_str
)), 0));
702 if (dff_mode
&& clk_sig
.empty())
703 log_cmd_error("Clock domain %s not found.\n", clk_str
.c_str());
705 std::string tempdir_name
= "/tmp/yosys-abc-XXXXXX";
707 tempdir_name
[0] = tempdir_name
[4] = '_';
708 tempdir_name
= make_temp_dir(tempdir_name
);
709 log_header(design
, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
710 module
->name
.c_str(), replace_tempdir(tempdir_name
, tempdir_name
, show_tempdir
).c_str());
712 std::string abc_script
= stringf("read_blif %s/input.blif; ", tempdir_name
.c_str());
714 if (!liberty_file
.empty()) {
715 abc_script
+= stringf("read_lib -w %s; ", liberty_file
.c_str());
716 if (!constr_file
.empty())
717 abc_script
+= stringf("read_constr -v %s; ", constr_file
.c_str());
719 if (!lut_costs
.empty())
720 abc_script
+= stringf("read_lut %s/lutdefs.txt; ", tempdir_name
.c_str());
722 abc_script
+= stringf("read_library %s/stdcells.genlib; ", tempdir_name
.c_str());
724 if (!script_file
.empty()) {
725 if (script_file
[0] == '+') {
726 for (size_t i
= 1; i
< script_file
.size(); i
++)
727 if (script_file
[i
] == '\'')
728 abc_script
+= "'\\''";
729 else if (script_file
[i
] == ',')
732 abc_script
+= script_file
[i
];
734 abc_script
+= stringf("source %s", script_file
.c_str());
735 } else if (!lut_costs
.empty()) {
736 bool all_luts_cost_same
= true;
737 for (int this_cost
: lut_costs
)
738 if (this_cost
!= lut_costs
.front())
739 all_luts_cost_same
= false;
740 abc_script
+= fast_mode
? ABC_FAST_COMMAND_LUT
: ABC_COMMAND_LUT
;
741 if (all_luts_cost_same
&& !fast_mode
)
742 abc_script
+= "; lutpack {S}";
743 } else if (!liberty_file
.empty())
744 abc_script
+= constr_file
.empty() ? (fast_mode
? ABC_FAST_COMMAND_LIB
: ABC_COMMAND_LIB
) : (fast_mode
? ABC_FAST_COMMAND_CTR
: ABC_COMMAND_CTR
);
746 abc_script
+= fast_mode
? ABC_FAST_COMMAND_SOP
: ABC_COMMAND_SOP
;
748 abc_script
+= fast_mode
? ABC_FAST_COMMAND_DFL
: ABC_COMMAND_DFL
;
750 for (size_t pos
= abc_script
.find("{D}"); pos
!= std::string::npos
; pos
= abc_script
.find("{D}", pos
))
751 abc_script
= abc_script
.substr(0, pos
) + delay_target
+ abc_script
.substr(pos
+3);
753 for (size_t pos
= abc_script
.find("{I}"); pos
!= std::string::npos
; pos
= abc_script
.find("{D}", pos
))
754 abc_script
= abc_script
.substr(0, pos
) + sop_inputs
+ abc_script
.substr(pos
+3);
756 for (size_t pos
= abc_script
.find("{P}"); pos
!= std::string::npos
; pos
= abc_script
.find("{D}", pos
))
757 abc_script
= abc_script
.substr(0, pos
) + sop_products
+ abc_script
.substr(pos
+3);
759 for (size_t pos
= abc_script
.find("{S}"); pos
!= std::string::npos
; pos
= abc_script
.find("{S}", pos
))
760 abc_script
= abc_script
.substr(0, pos
) + lutin_shared
+ abc_script
.substr(pos
+3);
762 abc_script
+= "; dress";
763 abc_script
+= stringf("; write_blif %s/output.blif", tempdir_name
.c_str());
764 abc_script
= add_echos_to_abc_cmd(abc_script
);
766 for (size_t i
= 0; i
+1 < abc_script
.size(); i
++)
767 if (abc_script
[i
] == ';' && abc_script
[i
+1] == ' ')
768 abc_script
[i
+1] = '\n';
770 FILE *f
= fopen(stringf("%s/abc.script", tempdir_name
.c_str()).c_str(), "wt");
771 fprintf(f
, "%s\n", abc_script
.c_str());
774 if (dff_mode
|| !clk_str
.empty())
776 if (clk_sig
.size() == 0)
777 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str
.empty() ? "" : " matching");
779 log("Found%s %s clock domain: %s", clk_str
.empty() ? "" : " matching", clk_polarity
? "posedge" : "negedge", log_signal(clk_sig
));
780 if (en_sig
.size() != 0)
781 log(", enabled by %s%s", en_polarity
? "" : "!", log_signal(en_sig
));
787 extract_cell(c
, keepff
);
789 for (auto &wire_it
: module
->wires_
) {
790 if (wire_it
.second
->port_id
> 0 || wire_it
.second
->get_bool_attribute("\\keep"))
791 mark_port(RTLIL::SigSpec(wire_it
.second
));
794 for (auto &cell_it
: module
->cells_
)
795 for (auto &port_it
: cell_it
.second
->connections())
796 mark_port(port_it
.second
);
798 if (clk_sig
.size() != 0)
801 if (en_sig
.size() != 0)
806 std::string buffer
= stringf("%s/input.blif", tempdir_name
.c_str());
807 f
= fopen(buffer
.c_str(), "wt");
809 log_error("Opening %s for writing failed: %s\n", buffer
.c_str(), strerror(errno
));
811 fprintf(f
, ".model netlist\n");
814 fprintf(f
, ".inputs");
815 for (auto &si
: signal_list
) {
816 if (!si
.is_port
|| si
.type
!= G(NONE
))
818 fprintf(f
, " ys__n%d", si
.id
);
819 pi_map
[count_input
++] = log_signal(si
.bit
);
821 if (count_input
== 0)
822 fprintf(f
, " dummy_input\n");
825 int count_output
= 0;
826 fprintf(f
, ".outputs");
827 for (auto &si
: signal_list
) {
828 if (!si
.is_port
|| si
.type
== G(NONE
))
830 fprintf(f
, " ys__n%d", si
.id
);
831 po_map
[count_output
++] = log_signal(si
.bit
);
835 for (auto &si
: signal_list
)
836 fprintf(f
, "# ys__n%-5d %s\n", si
.id
, log_signal(si
.bit
));
838 for (auto &si
: signal_list
) {
839 if (si
.bit
.wire
== NULL
) {
840 fprintf(f
, ".names ys__n%d\n", si
.id
);
841 if (si
.bit
== RTLIL::State::S1
)
847 for (auto &si
: signal_list
) {
848 if (si
.type
== G(BUF
)) {
849 fprintf(f
, ".names ys__n%d ys__n%d\n", si
.in1
, si
.id
);
851 } else if (si
.type
== G(NOT
)) {
852 fprintf(f
, ".names ys__n%d ys__n%d\n", si
.in1
, si
.id
);
854 } else if (si
.type
== G(AND
)) {
855 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
856 fprintf(f
, "11 1\n");
857 } else if (si
.type
== G(NAND
)) {
858 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
859 fprintf(f
, "0- 1\n");
860 fprintf(f
, "-0 1\n");
861 } else if (si
.type
== G(OR
)) {
862 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
863 fprintf(f
, "-1 1\n");
864 fprintf(f
, "1- 1\n");
865 } else if (si
.type
== G(NOR
)) {
866 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
867 fprintf(f
, "00 1\n");
868 } else if (si
.type
== G(XOR
)) {
869 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
870 fprintf(f
, "01 1\n");
871 fprintf(f
, "10 1\n");
872 } else if (si
.type
== G(XNOR
)) {
873 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
874 fprintf(f
, "00 1\n");
875 fprintf(f
, "11 1\n");
876 } else if (si
.type
== G(ANDNOT
)) {
877 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
878 fprintf(f
, "10 1\n");
879 } else if (si
.type
== G(ORNOT
)) {
880 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.id
);
881 fprintf(f
, "1- 1\n");
882 fprintf(f
, "-0 1\n");
883 } else if (si
.type
== G(MUX
)) {
884 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.in3
, si
.id
);
885 fprintf(f
, "1-0 1\n");
886 fprintf(f
, "-11 1\n");
887 } else if (si
.type
== G(NMUX
)) {
888 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.in3
, si
.id
);
889 fprintf(f
, "0-0 1\n");
890 fprintf(f
, "-01 1\n");
891 } else if (si
.type
== G(AOI3
)) {
892 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.in3
, si
.id
);
893 fprintf(f
, "-00 1\n");
894 fprintf(f
, "0-0 1\n");
895 } else if (si
.type
== G(OAI3
)) {
896 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.in3
, si
.id
);
897 fprintf(f
, "00- 1\n");
898 fprintf(f
, "--0 1\n");
899 } else if (si
.type
== G(AOI4
)) {
900 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.in3
, si
.in4
, si
.id
);
901 fprintf(f
, "-0-0 1\n");
902 fprintf(f
, "-00- 1\n");
903 fprintf(f
, "0--0 1\n");
904 fprintf(f
, "0-0- 1\n");
905 } else if (si
.type
== G(OAI4
)) {
906 fprintf(f
, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si
.in1
, si
.in2
, si
.in3
, si
.in4
, si
.id
);
907 fprintf(f
, "00-- 1\n");
908 fprintf(f
, "--00 1\n");
909 } else if (si
.type
== G(FF
)) {
910 if (si
.init
== State::S0
|| si
.init
== State::S1
) {
911 fprintf(f
, ".latch ys__n%d ys__n%d %d\n", si
.in1
, si
.id
, si
.init
== State::S1
? 1 : 0);
914 fprintf(f
, ".latch ys__n%d ys__n%d 2\n", si
.in1
, si
.id
);
915 } else if (si
.type
!= G(NONE
))
917 if (si
.type
!= G(NONE
))
921 fprintf(f
, ".end\n");
924 log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
925 count_gates
, GetSize(signal_list
), count_input
, count_output
);
927 if (count_output
> 0)
929 log_header(design
, "Executing ABC.\n");
931 auto &cell_cost
= cmos_cost
? CellCosts::cmos_gate_cost() : CellCosts::default_gate_cost();
933 buffer
= stringf("%s/stdcells.genlib", tempdir_name
.c_str());
934 f
= fopen(buffer
.c_str(), "wt");
936 log_error("Opening %s for writing failed: %s\n", buffer
.c_str(), strerror(errno
));
937 fprintf(f
, "GATE ZERO 1 Y=CONST0;\n");
938 fprintf(f
, "GATE ONE 1 Y=CONST1;\n");
939 fprintf(f
, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", cell_cost
.at(ID($_BUF_
)));
940 fprintf(f
, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", cell_cost
.at(ID($_NOT_
)));
941 if (enabled_gates
.count("AND"))
942 fprintf(f
, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost
.at(ID($_AND_
)));
943 if (enabled_gates
.count("NAND"))
944 fprintf(f
, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", cell_cost
.at(ID($_NAND_
)));
945 if (enabled_gates
.count("OR"))
946 fprintf(f
, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", cell_cost
.at(ID($_OR_
)));
947 if (enabled_gates
.count("NOR"))
948 fprintf(f
, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", cell_cost
.at(ID($_NOR_
)));
949 if (enabled_gates
.count("XOR"))
950 fprintf(f
, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost
.at(ID($_XOR_
)));
951 if (enabled_gates
.count("XNOR"))
952 fprintf(f
, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost
.at(ID($_XNOR_
)));
953 if (enabled_gates
.count("ANDNOT"))
954 fprintf(f
, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost
.at(ID($_ANDNOT_
)));
955 if (enabled_gates
.count("ORNOT"))
956 fprintf(f
, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost
.at(ID($_ORNOT_
)));
957 if (enabled_gates
.count("AOI3"))
958 fprintf(f
, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", cell_cost
.at(ID($_AOI3_
)));
959 if (enabled_gates
.count("OAI3"))
960 fprintf(f
, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", cell_cost
.at(ID($_OAI3_
)));
961 if (enabled_gates
.count("AOI4"))
962 fprintf(f
, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", cell_cost
.at(ID($_AOI4_
)));
963 if (enabled_gates
.count("OAI4"))
964 fprintf(f
, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", cell_cost
.at(ID($_OAI4_
)));
965 if (enabled_gates
.count("MUX"))
966 fprintf(f
, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost
.at(ID($_MUX_
)));
967 if (enabled_gates
.count("NMUX"))
968 fprintf(f
, "GATE NMUX %d Y=!((A*B)+(S*B)+(!S*A)); PIN * UNKNOWN 1 999 1 0 1 0\n", cell_cost
.at(ID($_NMUX_
)));
970 fprintf(f
, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*cell_cost
.at(ID($_MUX_
)));
972 fprintf(f
, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*cell_cost
.at(ID($_MUX_
)));
974 fprintf(f
, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*cell_cost
.at(ID($_MUX_
)));
977 if (!lut_costs
.empty()) {
978 buffer
= stringf("%s/lutdefs.txt", tempdir_name
.c_str());
979 f
= fopen(buffer
.c_str(), "wt");
981 log_error("Opening %s for writing failed: %s\n", buffer
.c_str(), strerror(errno
));
982 for (int i
= 0; i
< GetSize(lut_costs
); i
++)
983 fprintf(f
, "%d %d.00 1.00\n", i
+1, lut_costs
.at(i
));
987 buffer
= stringf("%s -s -f %s/abc.script 2>&1", exe_file
.c_str(), tempdir_name
.c_str());
988 log("Running ABC command: %s\n", replace_tempdir(buffer
, tempdir_name
, show_tempdir
).c_str());
990 #ifndef YOSYS_LINK_ABC
991 abc_output_filter
filt(tempdir_name
, show_tempdir
);
992 int ret
= run_command(buffer
, std::bind(&abc_output_filter::next_line
, filt
, std::placeholders::_1
));
994 // These needs to be mutable, supposedly due to getopt
996 string tmp_script_name
= stringf("%s/abc.script", tempdir_name
.c_str());
997 abc_argv
[0] = strdup(exe_file
.c_str());
998 abc_argv
[1] = strdup("-s");
999 abc_argv
[2] = strdup("-f");
1000 abc_argv
[3] = strdup(tmp_script_name
.c_str());
1002 int ret
= Abc_RealMain(4, abc_argv
);
1009 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer
.c_str(), ret
);
1011 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "output.blif");
1015 log_error("Can't open ABC output file `%s'.\n", buffer
.c_str());
1017 bool builtin_lib
= liberty_file
.empty();
1018 RTLIL::Design
*mapped_design
= new RTLIL::Design
;
1019 parse_blif(mapped_design
, ifs
, builtin_lib
? "\\DFF" : "\\_dff_", false, sop_mode
);
1023 log_header(design
, "Re-integrating ABC results.\n");
1024 RTLIL::Module
*mapped_mod
= mapped_design
->modules_
["\\netlist"];
1025 if (mapped_mod
== NULL
)
1026 log_error("ABC output file does not contain a module `netlist'.\n");
1027 for (auto &it
: mapped_mod
->wires_
) {
1028 RTLIL::Wire
*w
= it
.second
;
1029 RTLIL::Wire
*orig_wire
= nullptr;
1030 RTLIL::Wire
*wire
= module
->addWire(remap_name(w
->name
, &orig_wire
));
1031 if (orig_wire
!= nullptr && orig_wire
->attributes
.count("\\src"))
1032 wire
->attributes
["\\src"] = orig_wire
->attributes
["\\src"];
1033 if (markgroups
) wire
->attributes
["\\abcgroup"] = map_autoidx
;
1034 design
->select(module
, wire
);
1037 std::map
<std::string
, int> cell_stats
;
1038 for (auto c
: mapped_mod
->cells())
1042 cell_stats
[RTLIL::unescape_id(c
->type
)]++;
1043 if (c
->type
.in("\\ZERO", "\\ONE")) {
1045 conn
.first
= RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]);
1046 conn
.second
= RTLIL::SigSpec(c
->type
== "\\ZERO" ? 0 : 1, 1);
1047 module
->connect(conn
);
1050 if (c
->type
== "\\BUF") {
1052 conn
.first
= RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]);
1053 conn
.second
= RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]);
1054 module
->connect(conn
);
1057 if (c
->type
== "\\NOT") {
1058 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), ID($_NOT_
));
1059 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1060 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1061 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1062 design
->select(module
, cell
);
1065 if (c
->type
.in("\\AND", "\\OR", "\\XOR", "\\NAND", "\\NOR", "\\XNOR", "\\ANDNOT", "\\ORNOT")) {
1066 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), stringf("$_%s_", c
->type
.c_str()+1));
1067 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1068 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1069 cell
->setPort("\\B", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\B").as_wire()->name
)]));
1070 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1071 design
->select(module
, cell
);
1074 if (c
->type
.in("\\MUX", "\\NMUX")) {
1075 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), stringf("$_%s_", c
->type
.c_str()+1));
1076 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1077 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1078 cell
->setPort("\\B", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\B").as_wire()->name
)]));
1079 cell
->setPort("\\S", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\S").as_wire()->name
)]));
1080 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1081 design
->select(module
, cell
);
1084 if (c
->type
== "\\MUX4") {
1085 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), ID($_MUX4_
));
1086 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1087 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1088 cell
->setPort("\\B", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\B").as_wire()->name
)]));
1089 cell
->setPort("\\C", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\C").as_wire()->name
)]));
1090 cell
->setPort("\\D", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\D").as_wire()->name
)]));
1091 cell
->setPort("\\S", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\S").as_wire()->name
)]));
1092 cell
->setPort("\\T", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\T").as_wire()->name
)]));
1093 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1094 design
->select(module
, cell
);
1097 if (c
->type
== "\\MUX8") {
1098 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), ID($_MUX8_
));
1099 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1100 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1101 cell
->setPort("\\B", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\B").as_wire()->name
)]));
1102 cell
->setPort("\\C", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\C").as_wire()->name
)]));
1103 cell
->setPort("\\D", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\D").as_wire()->name
)]));
1104 cell
->setPort("\\E", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\E").as_wire()->name
)]));
1105 cell
->setPort("\\F", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\F").as_wire()->name
)]));
1106 cell
->setPort("\\G", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\G").as_wire()->name
)]));
1107 cell
->setPort("\\H", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\H").as_wire()->name
)]));
1108 cell
->setPort("\\S", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\S").as_wire()->name
)]));
1109 cell
->setPort("\\T", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\T").as_wire()->name
)]));
1110 cell
->setPort("\\U", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\U").as_wire()->name
)]));
1111 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1112 design
->select(module
, cell
);
1115 if (c
->type
== "\\MUX16") {
1116 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), ID($_MUX16_
));
1117 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1118 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1119 cell
->setPort("\\B", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\B").as_wire()->name
)]));
1120 cell
->setPort("\\C", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\C").as_wire()->name
)]));
1121 cell
->setPort("\\D", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\D").as_wire()->name
)]));
1122 cell
->setPort("\\E", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\E").as_wire()->name
)]));
1123 cell
->setPort("\\F", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\F").as_wire()->name
)]));
1124 cell
->setPort("\\G", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\G").as_wire()->name
)]));
1125 cell
->setPort("\\H", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\H").as_wire()->name
)]));
1126 cell
->setPort("\\I", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\I").as_wire()->name
)]));
1127 cell
->setPort("\\J", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\J").as_wire()->name
)]));
1128 cell
->setPort("\\K", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\K").as_wire()->name
)]));
1129 cell
->setPort("\\L", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\L").as_wire()->name
)]));
1130 cell
->setPort("\\M", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\M").as_wire()->name
)]));
1131 cell
->setPort("\\N", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\N").as_wire()->name
)]));
1132 cell
->setPort("\\O", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\O").as_wire()->name
)]));
1133 cell
->setPort("\\P", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\P").as_wire()->name
)]));
1134 cell
->setPort("\\S", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\S").as_wire()->name
)]));
1135 cell
->setPort("\\T", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\T").as_wire()->name
)]));
1136 cell
->setPort("\\U", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\U").as_wire()->name
)]));
1137 cell
->setPort("\\V", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\V").as_wire()->name
)]));
1138 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1139 design
->select(module
, cell
);
1142 if (c
->type
.in("\\AOI3", "\\OAI3")) {
1143 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), stringf("$_%s_", c
->type
.c_str()+1));
1144 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1145 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1146 cell
->setPort("\\B", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\B").as_wire()->name
)]));
1147 cell
->setPort("\\C", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\C").as_wire()->name
)]));
1148 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1149 design
->select(module
, cell
);
1152 if (c
->type
.in("\\AOI4", "\\OAI4")) {
1153 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), stringf("$_%s_", c
->type
.c_str()+1));
1154 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1155 cell
->setPort("\\A", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)]));
1156 cell
->setPort("\\B", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\B").as_wire()->name
)]));
1157 cell
->setPort("\\C", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\C").as_wire()->name
)]));
1158 cell
->setPort("\\D", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\D").as_wire()->name
)]));
1159 cell
->setPort("\\Y", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)]));
1160 design
->select(module
, cell
);
1163 if (c
->type
== "\\DFF") {
1164 log_assert(clk_sig
.size() == 1);
1166 if (en_sig
.size() == 0) {
1167 cell
= module
->addCell(remap_name(c
->name
), clk_polarity
? ID($_DFF_P_
) : ID($_DFF_N_
));
1169 log_assert(en_sig
.size() == 1);
1170 cell
= module
->addCell(remap_name(c
->name
), stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
1171 cell
->setPort("\\E", en_sig
);
1173 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1174 cell
->setPort("\\D", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\D").as_wire()->name
)]));
1175 cell
->setPort("\\Q", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Q").as_wire()->name
)]));
1176 cell
->setPort("\\C", clk_sig
);
1177 design
->select(module
, cell
);
1182 cell_stats
[RTLIL::unescape_id(c
->type
)]++;
1184 if (c
->type
.in("\\_const0_", "\\_const1_")) {
1186 conn
.first
= RTLIL::SigSpec(module
->wires_
[remap_name(c
->connections().begin()->second
.as_wire()->name
)]);
1187 conn
.second
= RTLIL::SigSpec(c
->type
== "\\_const0_" ? 0 : 1, 1);
1188 module
->connect(conn
);
1192 if (c
->type
== "\\_dff_") {
1193 log_assert(clk_sig
.size() == 1);
1195 if (en_sig
.size() == 0) {
1196 cell
= module
->addCell(remap_name(c
->name
), clk_polarity
? ID($_DFF_P_
) : ID($_DFF_N_
));
1198 log_assert(en_sig
.size() == 1);
1199 cell
= module
->addCell(remap_name(c
->name
), stringf("$_DFFE_%c%c_", clk_polarity
? 'P' : 'N', en_polarity
? 'P' : 'N'));
1200 cell
->setPort("\\E", en_sig
);
1202 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1203 cell
->setPort("\\D", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\D").as_wire()->name
)]));
1204 cell
->setPort("\\Q", RTLIL::SigSpec(module
->wires_
[remap_name(c
->getPort("\\Q").as_wire()->name
)]));
1205 cell
->setPort("\\C", clk_sig
);
1206 design
->select(module
, cell
);
1210 if (c
->type
== ID($lut
) && GetSize(c
->getPort("\\A")) == 1 && c
->getParam("\\LUT").as_int() == 2) {
1211 SigSpec my_a
= module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)];
1212 SigSpec my_y
= module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)];
1213 module
->connect(my_y
, my_a
);
1217 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), c
->type
);
1218 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
1219 cell
->parameters
= c
->parameters
;
1220 for (auto &conn
: c
->connections()) {
1221 RTLIL::SigSpec newsig
;
1222 for (auto &c
: conn
.second
.chunks()) {
1225 log_assert(c
.width
== 1);
1226 newsig
.append(module
->wires_
[remap_name(c
.wire
->name
)]);
1228 cell
->setPort(conn
.first
, newsig
);
1230 design
->select(module
, cell
);
1233 for (auto conn
: mapped_mod
->connections()) {
1234 if (!conn
.first
.is_fully_const())
1235 conn
.first
= RTLIL::SigSpec(module
->wires_
[remap_name(conn
.first
.as_wire()->name
)]);
1236 if (!conn
.second
.is_fully_const())
1237 conn
.second
= RTLIL::SigSpec(module
->wires_
[remap_name(conn
.second
.as_wire()->name
)]);
1238 module
->connect(conn
);
1242 for (auto wire
: mapped_mod
->wires()) {
1243 if (wire
->attributes
.count("\\init")) {
1244 Wire
*w
= module
->wires_
[remap_name(wire
->name
)];
1245 log_assert(w
->attributes
.count("\\init") == 0);
1246 w
->attributes
["\\init"] = wire
->attributes
.at("\\init");
1250 for (auto &it
: cell_stats
)
1251 log("ABC RESULTS: %15s cells: %8d\n", it
.first
.c_str(), it
.second
);
1252 int in_wires
= 0, out_wires
= 0;
1253 for (auto &si
: signal_list
)
1256 snprintf(buffer
, 100, "\\ys__n%d", si
.id
);
1258 if (si
.type
!= G(NONE
)) {
1259 conn
.first
= si
.bit
;
1260 conn
.second
= RTLIL::SigSpec(module
->wires_
[remap_name(buffer
)]);
1263 conn
.first
= RTLIL::SigSpec(module
->wires_
[remap_name(buffer
)]);
1264 conn
.second
= si
.bit
;
1267 module
->connect(conn
);
1269 log("ABC RESULTS: internal signals: %8d\n", int(signal_list
.size()) - in_wires
- out_wires
);
1270 log("ABC RESULTS: input signals: %8d\n", in_wires
);
1271 log("ABC RESULTS: output signals: %8d\n", out_wires
);
1273 delete mapped_design
;
1277 log("Don't call ABC as there is nothing to map.\n");
1282 log("Removing temp directory.\n");
1283 remove_directory(tempdir_name
);
1289 struct AbcPass
: public Pass
{
1290 AbcPass() : Pass("abc", "use ABC for technology mapping") { }
1291 void help() YS_OVERRIDE
1293 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1295 log(" abc [options] [selection]\n");
1297 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
1298 log("library to a target architecture.\n");
1300 log(" -exe <command>\n");
1302 log(" use the specified command instead of \"" ABCEXTERNAL
"\" to execute ABC.\n");
1304 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
1306 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
1308 log(" -script <file>\n");
1309 log(" use the specified ABC script file instead of the default script.\n");
1311 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
1312 log(" string is interpreted as the command string to be passed to ABC. The\n");
1313 log(" leading plus sign is removed and all commas (,) in the string are\n");
1314 log(" replaced with blanks before the string is passed to ABC.\n");
1316 log(" if no -script parameter is given, the following scripts are used:\n");
1318 log(" for -liberty without -constr:\n");
1319 log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB
).c_str());
1321 log(" for -liberty with -constr:\n");
1322 log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR
).c_str());
1324 log(" for -lut/-luts (only one LUT size):\n");
1325 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT
"; lutpack {S}").c_str());
1327 log(" for -lut/-luts (different LUT sizes):\n");
1328 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT
).c_str());
1330 log(" for -sop:\n");
1331 log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP
).c_str());
1333 log(" otherwise:\n");
1334 log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL
).c_str());
1337 log(" use different default scripts that are slightly faster (at the cost\n");
1338 log(" of output quality):\n");
1340 log(" for -liberty without -constr:\n");
1341 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB
).c_str());
1343 log(" for -liberty with -constr:\n");
1344 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR
).c_str());
1346 log(" for -lut/-luts:\n");
1347 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT
).c_str());
1349 log(" for -sop:\n");
1350 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP
).c_str());
1352 log(" otherwise:\n");
1353 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL
).c_str());
1355 log(" -liberty <file>\n");
1356 log(" generate netlists for the specified cell library (using the liberty\n");
1357 log(" file format).\n");
1359 log(" -constr <file>\n");
1360 log(" pass this file with timing constraints to ABC. use with -liberty.\n");
1362 log(" a constr file contains two lines:\n");
1363 log(" set_driving_cell <cell_name>\n");
1364 log(" set_load <floating_point_number>\n");
1366 log(" the set_driving_cell statement defines which cell type is assumed to\n");
1367 log(" drive the primary inputs and the set_load statement sets the load in\n");
1368 log(" femtofarads for each primary output.\n");
1370 log(" -D <picoseconds>\n");
1371 log(" set delay target. the string {D} in the default scripts above is\n");
1372 log(" replaced by this option when used, and an empty string otherwise.\n");
1373 log(" this also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
1374 log(" default scripts above.\n");
1377 log(" maximum number of SOP inputs.\n");
1378 log(" (replaces {I} in the default scripts above)\n");
1381 log(" maximum number of SOP products.\n");
1382 log(" (replaces {P} in the default scripts above)\n");
1385 log(" maximum number of LUT inputs shared.\n");
1386 log(" (replaces {S} in the default scripts above, default: -S 1)\n");
1388 log(" -lut <width>\n");
1389 log(" generate netlist using luts of (max) the specified width.\n");
1391 log(" -lut <w1>:<w2>\n");
1392 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
1393 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
1394 log(" the area cost doubles with each additional input bit. the delay cost\n");
1395 log(" is still constant for all lut widths.\n");
1397 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
1398 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
1399 log(" 2, 3, .. inputs.\n");
1402 log(" map to sum-of-product cells and inverters\n");
1404 // log(" -mux4, -mux8, -mux16\n");
1405 // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
1406 // log(" (ignored when used with -liberty or -lut)\n");
1408 log(" -g type1,type2,...\n");
1409 log(" Map to the specified list of gate types. Supported gates types are:\n");
1410 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1411 log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,\n");
1412 log(" NMUX, AOI3, OAI3, AOI4, OAI4.\n");
1413 log(" (The NOT gate is always added to this list automatically.)\n");
1415 log(" The following aliases can be used to reference common sets of gate types:\n");
1416 log(" simple: AND OR XOR MUX\n");
1417 log(" cmos2: NAND NOR\n");
1418 log(" cmos3: NAND NOR AOI3 OAI3\n");
1419 log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
1420 log(" cmos: NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR\n");
1421 log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
1422 log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
1424 log(" The alias 'all' represent the full set of all gate types.\n");
1426 log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
1427 log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
1429 log(" The default is 'all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4'.\n");
1432 log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
1433 log(" clock domains are automatically partitioned in clock domains and each\n");
1434 log(" domain is passed through ABC independently.\n");
1436 log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
1437 log(" use only the specified clock domain. this is like -dff, but only FF\n");
1438 log(" cells that belong to the specified clock domain are used.\n");
1441 log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
1442 log(" them, for example for equivalence checking.)\n");
1444 log(" -nocleanup\n");
1445 log(" when this option is used, the temporary files created by this pass\n");
1446 log(" are not removed. this is useful for debugging.\n");
1449 log(" print the temp dir name in log. usually this is suppressed so that the\n");
1450 log(" command output is identical across runs.\n");
1452 log(" -markgroups\n");
1453 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
1454 log(" this attribute is a unique integer for each ABC process started. This\n");
1455 log(" is useful for debugging the partitioning of clock domains.\n");
1458 log(" run the 'dress' command after all other ABC commands. This aims to\n");
1459 log(" preserve naming by an equivalence check between the original and post-ABC\n");
1460 log(" netlists (experimental).\n");
1462 log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
1463 log("loaded into ABC before the ABC script is executed.\n");
1465 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
1466 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
1467 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
1468 log("output when passing an ABC script that writes a file. Instead write your full\n");
1469 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
1470 log("you want to use ABC to convert your design into another format.\n");
1472 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
1475 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1477 log_header(design
, "Executing ABC pass (technology mapping using ABC).\n");
1481 signal_list
.clear();
1483 signal_init
.clear();
1488 std::string exe_file
= ABCEXTERNAL
;
1490 std::string exe_file
= proc_self_dirname() + "yosys-abc";
1492 std::string script_file
, liberty_file
, constr_file
, clk_str
;
1493 std::string delay_target
, sop_inputs
, sop_products
, lutin_shared
= "-S 1";
1494 bool fast_mode
= false, dff_mode
= false, keepff
= false, cleanup
= true;
1495 bool show_tempdir
= false, sop_mode
= false;
1496 bool abc_dress
= false;
1497 vector
<int> lut_costs
;
1503 enabled_gates
.clear();
1508 if (!check_file_exists(exe_file
+ ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
1509 exe_file
= proc_self_dirname() + "..\\yosys-abc";
1514 char pwd
[PATH_MAX
];
1515 if (!getcwd(pwd
, sizeof(pwd
))) {
1516 log_cmd_error("getcwd failed: %s\n", strerror(errno
));
1519 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
1520 std::string arg
= args
[argidx
];
1521 if (arg
== "-exe" && argidx
+1 < args
.size()) {
1522 exe_file
= args
[++argidx
];
1525 if (arg
== "-script" && argidx
+1 < args
.size()) {
1526 script_file
= args
[++argidx
];
1527 rewrite_filename(script_file
);
1528 if (!script_file
.empty() && !is_absolute_path(script_file
) && script_file
[0] != '+')
1529 script_file
= std::string(pwd
) + "/" + script_file
;
1532 if (arg
== "-liberty" && argidx
+1 < args
.size()) {
1533 liberty_file
= args
[++argidx
];
1534 rewrite_filename(liberty_file
);
1535 if (!liberty_file
.empty() && !is_absolute_path(liberty_file
))
1536 liberty_file
= std::string(pwd
) + "/" + liberty_file
;
1539 if (arg
== "-constr" && argidx
+1 < args
.size()) {
1540 rewrite_filename(constr_file
);
1541 constr_file
= args
[++argidx
];
1542 if (!constr_file
.empty() && !is_absolute_path(constr_file
))
1543 constr_file
= std::string(pwd
) + "/" + constr_file
;
1546 if (arg
== "-D" && argidx
+1 < args
.size()) {
1547 delay_target
= "-D " + args
[++argidx
];
1550 if (arg
== "-I" && argidx
+1 < args
.size()) {
1551 sop_inputs
= "-I " + args
[++argidx
];
1554 if (arg
== "-P" && argidx
+1 < args
.size()) {
1555 sop_products
= "-P " + args
[++argidx
];
1558 if (arg
== "-S" && argidx
+1 < args
.size()) {
1559 lutin_shared
= "-S " + args
[++argidx
];
1562 if (arg
== "-lut" && argidx
+1 < args
.size()) {
1563 string arg
= args
[++argidx
];
1564 size_t pos
= arg
.find_first_of(':');
1565 int lut_mode
= 0, lut_mode2
= 0;
1566 if (pos
!= string::npos
) {
1567 lut_mode
= atoi(arg
.substr(0, pos
).c_str());
1568 lut_mode2
= atoi(arg
.substr(pos
+1).c_str());
1570 lut_mode
= atoi(arg
.c_str());
1571 lut_mode2
= lut_mode
;
1574 for (int i
= 0; i
< lut_mode
; i
++)
1575 lut_costs
.push_back(1);
1576 for (int i
= lut_mode
; i
< lut_mode2
; i
++)
1577 lut_costs
.push_back(2 << (i
- lut_mode
));
1580 if (arg
== "-luts" && argidx
+1 < args
.size()) {
1582 for (auto &tok
: split_tokens(args
[++argidx
], ",")) {
1583 auto parts
= split_tokens(tok
, ":");
1584 if (GetSize(parts
) == 0 && !lut_costs
.empty())
1585 lut_costs
.push_back(lut_costs
.back());
1586 else if (GetSize(parts
) == 1)
1587 lut_costs
.push_back(atoi(parts
.at(0).c_str()));
1588 else if (GetSize(parts
) == 2)
1589 while (GetSize(lut_costs
) < std::atoi(parts
.at(0).c_str()))
1590 lut_costs
.push_back(atoi(parts
.at(1).c_str()));
1592 log_cmd_error("Invalid -luts syntax.\n");
1596 if (arg
== "-sop") {
1600 if (arg
== "-mux4") {
1604 if (arg
== "-mux8") {
1608 if (arg
== "-mux16") {
1612 if (arg
== "-dress") {
1616 if (arg
== "-g" && argidx
+1 < args
.size()) {
1617 for (auto g
: split_tokens(args
[++argidx
], ",")) {
1618 vector
<string
> gate_list
;
1619 bool remove_gates
= false;
1620 if (GetSize(g
) > 0 && g
[0] == '-') {
1621 remove_gates
= true;
1624 if (g
== "AND") goto ok_gate
;
1625 if (g
== "NAND") goto ok_gate
;
1626 if (g
== "OR") goto ok_gate
;
1627 if (g
== "NOR") goto ok_gate
;
1628 if (g
== "XOR") goto ok_gate
;
1629 if (g
== "XNOR") goto ok_gate
;
1630 if (g
== "ANDNOT") goto ok_gate
;
1631 if (g
== "ORNOT") goto ok_gate
;
1632 if (g
== "MUX") goto ok_gate
;
1633 if (g
== "AOI3") goto ok_gate
;
1634 if (g
== "OAI3") goto ok_gate
;
1635 if (g
== "AOI4") goto ok_gate
;
1636 if (g
== "OAI4") goto ok_gate
;
1637 if (g
== "simple") {
1638 gate_list
.push_back("AND");
1639 gate_list
.push_back("OR");
1640 gate_list
.push_back("XOR");
1641 gate_list
.push_back("MUX");
1647 gate_list
.push_back("NAND");
1648 gate_list
.push_back("NOR");
1654 gate_list
.push_back("NAND");
1655 gate_list
.push_back("NOR");
1656 gate_list
.push_back("AOI3");
1657 gate_list
.push_back("OAI3");
1663 gate_list
.push_back("NAND");
1664 gate_list
.push_back("NOR");
1665 gate_list
.push_back("AOI3");
1666 gate_list
.push_back("OAI3");
1667 gate_list
.push_back("AOI4");
1668 gate_list
.push_back("OAI4");
1674 gate_list
.push_back("NAND");
1675 gate_list
.push_back("NOR");
1676 gate_list
.push_back("AOI3");
1677 gate_list
.push_back("OAI3");
1678 gate_list
.push_back("AOI4");
1679 gate_list
.push_back("OAI4");
1680 gate_list
.push_back("NMUX");
1681 gate_list
.push_back("MUX");
1682 gate_list
.push_back("XOR");
1683 gate_list
.push_back("XNOR");
1687 gate_list
.push_back("AND");
1688 gate_list
.push_back("NAND");
1689 gate_list
.push_back("OR");
1690 gate_list
.push_back("NOR");
1691 gate_list
.push_back("XOR");
1692 gate_list
.push_back("XNOR");
1693 gate_list
.push_back("ANDNOT");
1694 gate_list
.push_back("ORNOT");
1698 gate_list
.push_back("AND");
1699 gate_list
.push_back("NAND");
1700 gate_list
.push_back("OR");
1701 gate_list
.push_back("NOR");
1702 gate_list
.push_back("ANDNOT");
1703 gate_list
.push_back("ORNOT");
1707 gate_list
.push_back("AND");
1708 gate_list
.push_back("NAND");
1709 gate_list
.push_back("OR");
1710 gate_list
.push_back("NOR");
1711 gate_list
.push_back("XOR");
1712 gate_list
.push_back("XNOR");
1713 gate_list
.push_back("ANDNOT");
1714 gate_list
.push_back("ORNOT");
1715 gate_list
.push_back("AOI3");
1716 gate_list
.push_back("OAI3");
1717 gate_list
.push_back("AOI4");
1718 gate_list
.push_back("OAI4");
1719 gate_list
.push_back("MUX");
1720 gate_list
.push_back("NMUX");
1722 cmd_error(args
, argidx
, stringf("Unsupported gate type: %s", g
.c_str()));
1724 gate_list
.push_back(g
);
1726 for (auto gate
: gate_list
) {
1728 enabled_gates
.erase(gate
);
1730 enabled_gates
.insert(gate
);
1735 if (arg
== "-fast") {
1739 if (arg
== "-dff") {
1743 if (arg
== "-clk" && argidx
+1 < args
.size()) {
1744 clk_str
= args
[++argidx
];
1748 if (arg
== "-keepff") {
1752 if (arg
== "-nocleanup") {
1756 if (arg
== "-showtmp") {
1757 show_tempdir
= true;
1760 if (arg
== "-markgroups") {
1766 extra_args(args
, argidx
, design
);
1768 if (!lut_costs
.empty() && !liberty_file
.empty())
1769 log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
1770 if (!constr_file
.empty() && liberty_file
.empty())
1771 log_cmd_error("Got -constr but no -liberty!\n");
1773 if (enabled_gates
.empty()) {
1774 enabled_gates
.insert("AND");
1775 enabled_gates
.insert("NAND");
1776 enabled_gates
.insert("OR");
1777 enabled_gates
.insert("NOR");
1778 enabled_gates
.insert("XOR");
1779 enabled_gates
.insert("XNOR");
1780 enabled_gates
.insert("ANDNOT");
1781 enabled_gates
.insert("ORNOT");
1782 // enabled_gates.insert("AOI3");
1783 // enabled_gates.insert("OAI3");
1784 // enabled_gates.insert("AOI4");
1785 // enabled_gates.insert("OAI4");
1786 enabled_gates
.insert("MUX");
1787 // enabled_gates.insert("NMUX");
1790 for (auto mod
: design
->selected_modules())
1792 if (mod
->processes
.size() > 0) {
1793 log("Skipping module %s as it contains processes.\n", log_id(mod
));
1797 assign_map
.set(mod
);
1798 signal_init
.clear();
1800 for (Wire
*wire
: mod
->wires())
1801 if (wire
->attributes
.count("\\init")) {
1802 SigSpec initsig
= assign_map(wire
);
1803 Const initval
= wire
->attributes
.at("\\init");
1804 for (int i
= 0; i
< GetSize(initsig
) && i
< GetSize(initval
); i
++)
1805 switch (initval
[i
]) {
1807 signal_init
[initsig
[i
]] = State::S0
;
1810 signal_init
[initsig
[i
]] = State::S1
;
1817 if (!dff_mode
|| !clk_str
.empty()) {
1818 abc_module(design
, mod
, script_file
, exe_file
, liberty_file
, constr_file
, cleanup
, lut_costs
, dff_mode
, clk_str
, keepff
,
1819 delay_target
, sop_inputs
, sop_products
, lutin_shared
, fast_mode
, mod
->selected_cells(), show_tempdir
, sop_mode
, abc_dress
);
1823 CellTypes
ct(design
);
1825 std::vector
<RTLIL::Cell
*> all_cells
= mod
->selected_cells();
1826 std::set
<RTLIL::Cell
*> unassigned_cells(all_cells
.begin(), all_cells
.end());
1828 std::set
<RTLIL::Cell
*> expand_queue
, next_expand_queue
;
1829 std::set
<RTLIL::Cell
*> expand_queue_up
, next_expand_queue_up
;
1830 std::set
<RTLIL::Cell
*> expand_queue_down
, next_expand_queue_down
;
1832 typedef tuple
<bool, RTLIL::SigSpec
, bool, RTLIL::SigSpec
> clkdomain_t
;
1833 std::map
<clkdomain_t
, std::vector
<RTLIL::Cell
*>> assigned_cells
;
1834 std::map
<RTLIL::Cell
*, clkdomain_t
> assigned_cells_reverse
;
1836 std::map
<RTLIL::Cell
*, std::set
<RTLIL::SigBit
>> cell_to_bit
, cell_to_bit_up
, cell_to_bit_down
;
1837 std::map
<RTLIL::SigBit
, std::set
<RTLIL::Cell
*>> bit_to_cell
, bit_to_cell_up
, bit_to_cell_down
;
1839 for (auto cell
: all_cells
)
1843 for (auto &conn
: cell
->connections())
1844 for (auto bit
: conn
.second
) {
1845 bit
= assign_map(bit
);
1846 if (bit
.wire
!= nullptr) {
1847 cell_to_bit
[cell
].insert(bit
);
1848 bit_to_cell
[bit
].insert(cell
);
1849 if (ct
.cell_input(cell
->type
, conn
.first
)) {
1850 cell_to_bit_up
[cell
].insert(bit
);
1851 bit_to_cell_down
[bit
].insert(cell
);
1853 if (ct
.cell_output(cell
->type
, conn
.first
)) {
1854 cell_to_bit_down
[cell
].insert(bit
);
1855 bit_to_cell_up
[bit
].insert(cell
);
1860 if (cell
->type
.in(ID($_DFF_N_
), ID($_DFF_P_
)))
1862 key
= clkdomain_t(cell
->type
== ID($_DFF_P_
), assign_map(cell
->getPort("\\C")), true, RTLIL::SigSpec());
1865 if (cell
->type
.in(ID($_DFFE_NN_
), ID($_DFFE_NP_
), ID($_DFFE_PN_
), ID($_DFFE_PP_
)))
1867 bool this_clk_pol
= cell
->type
.in(ID($_DFFE_PN_
), ID($_DFFE_PP_
));
1868 bool this_en_pol
= cell
->type
.in(ID($_DFFE_NP_
), ID($_DFFE_PP_
));
1869 key
= clkdomain_t(this_clk_pol
, assign_map(cell
->getPort("\\C")), this_en_pol
, assign_map(cell
->getPort("\\E")));
1874 unassigned_cells
.erase(cell
);
1875 expand_queue
.insert(cell
);
1876 expand_queue_up
.insert(cell
);
1877 expand_queue_down
.insert(cell
);
1879 assigned_cells
[key
].push_back(cell
);
1880 assigned_cells_reverse
[cell
] = key
;
1883 while (!expand_queue_up
.empty() || !expand_queue_down
.empty())
1885 if (!expand_queue_up
.empty())
1887 RTLIL::Cell
*cell
= *expand_queue_up
.begin();
1888 clkdomain_t key
= assigned_cells_reverse
.at(cell
);
1889 expand_queue_up
.erase(cell
);
1891 for (auto bit
: cell_to_bit_up
[cell
])
1892 for (auto c
: bit_to_cell_up
[bit
])
1893 if (unassigned_cells
.count(c
)) {
1894 unassigned_cells
.erase(c
);
1895 next_expand_queue_up
.insert(c
);
1896 assigned_cells
[key
].push_back(c
);
1897 assigned_cells_reverse
[c
] = key
;
1898 expand_queue
.insert(c
);
1902 if (!expand_queue_down
.empty())
1904 RTLIL::Cell
*cell
= *expand_queue_down
.begin();
1905 clkdomain_t key
= assigned_cells_reverse
.at(cell
);
1906 expand_queue_down
.erase(cell
);
1908 for (auto bit
: cell_to_bit_down
[cell
])
1909 for (auto c
: bit_to_cell_down
[bit
])
1910 if (unassigned_cells
.count(c
)) {
1911 unassigned_cells
.erase(c
);
1912 next_expand_queue_up
.insert(c
);
1913 assigned_cells
[key
].push_back(c
);
1914 assigned_cells_reverse
[c
] = key
;
1915 expand_queue
.insert(c
);
1919 if (expand_queue_up
.empty() && expand_queue_down
.empty()) {
1920 expand_queue_up
.swap(next_expand_queue_up
);
1921 expand_queue_down
.swap(next_expand_queue_down
);
1925 while (!expand_queue
.empty())
1927 RTLIL::Cell
*cell
= *expand_queue
.begin();
1928 clkdomain_t key
= assigned_cells_reverse
.at(cell
);
1929 expand_queue
.erase(cell
);
1931 for (auto bit
: cell_to_bit
.at(cell
)) {
1932 for (auto c
: bit_to_cell
[bit
])
1933 if (unassigned_cells
.count(c
)) {
1934 unassigned_cells
.erase(c
);
1935 next_expand_queue
.insert(c
);
1936 assigned_cells
[key
].push_back(c
);
1937 assigned_cells_reverse
[c
] = key
;
1939 bit_to_cell
[bit
].clear();
1942 if (expand_queue
.empty())
1943 expand_queue
.swap(next_expand_queue
);
1946 clkdomain_t
key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1947 for (auto cell
: unassigned_cells
) {
1948 assigned_cells
[key
].push_back(cell
);
1949 assigned_cells_reverse
[cell
] = key
;
1952 log_header(design
, "Summary of detected clock domains:\n");
1953 for (auto &it
: assigned_cells
)
1954 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it
.second
),
1955 std::get
<0>(it
.first
) ? "" : "!", log_signal(std::get
<1>(it
.first
)),
1956 std::get
<2>(it
.first
) ? "" : "!", log_signal(std::get
<3>(it
.first
)));
1958 for (auto &it
: assigned_cells
) {
1959 clk_polarity
= std::get
<0>(it
.first
);
1960 clk_sig
= assign_map(std::get
<1>(it
.first
));
1961 en_polarity
= std::get
<2>(it
.first
);
1962 en_sig
= assign_map(std::get
<3>(it
.first
));
1963 abc_module(design
, mod
, script_file
, exe_file
, liberty_file
, constr_file
, cleanup
, lut_costs
, !clk_sig
.empty(), "$",
1964 keepff
, delay_target
, sop_inputs
, sop_products
, lutin_shared
, fast_mode
, it
.second
, show_tempdir
, sop_mode
, abc_dress
);
1965 assign_map
.set(mod
);
1970 signal_list
.clear();
1972 signal_init
.clear();
1980 PRIVATE_NAMESPACE_END