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7715fb291baecf2aa71d1c9c18c6c8f403f4d071
[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #if 0
26 // Based on &flow3 - better QoR but more experimental
27 #define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
28 "&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
29 "&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
30 "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
31 "&mfs; &ps -l"
32 #else
33 #define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v -w; &mfs; &ps -l"
34 #endif
35
36
37 #define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
38
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
44 #include <stdlib.h>
45 #include <stdio.h>
46 #include <string.h>
47 #include <cerrno>
48 #include <sstream>
49 #include <climits>
50
51 #ifndef _WIN32
52 # include <unistd.h>
53 # include <dirent.h>
54 #endif
55
56 #include "frontends/aiger/aigerparse.h"
57 #include "kernel/utils.h"
58
59 #ifdef YOSYS_LINK_ABC
60 extern "C" int Abc_RealMain(int argc, char *argv[]);
61 #endif
62
63 USING_YOSYS_NAMESPACE
64 PRIVATE_NAMESPACE_BEGIN
65
66 bool markgroups;
67 int map_autoidx;
68 SigMap assign_map;
69 RTLIL::Module *module;
70
71 bool clk_polarity, en_polarity;
72 RTLIL::SigSpec clk_sig, en_sig;
73
74 inline std::string remap_name(RTLIL::IdString abc_name)
75 {
76 return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
77 }
78
79 void handle_loops(RTLIL::Design *design)
80 {
81 Pass::call(design, "scc -set_attr abc_scc_id {}");
82
83 // For every unique SCC found, (arbitrarily) find the first
84 // cell in the component, and select (and mark) all its output
85 // wires
86 pool<RTLIL::Const> ids_seen;
87 for (auto cell : module->cells()) {
88 auto it = cell->attributes.find(ID(abc_scc_id));
89 if (it != cell->attributes.end()) {
90 auto r = ids_seen.insert(it->second);
91 if (r.second) {
92 for (auto &c : cell->connections_) {
93 if (c.second.is_fully_const()) continue;
94 if (cell->output(c.first)) {
95 SigBit b = c.second.as_bit();
96 Wire *w = b.wire;
97 log_assert(!w->port_input);
98 w->port_input = true;
99 w = module->wire(stringf("%s.abci", w->name.c_str()));
100 if (!w) {
101 w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
102 w->port_output = true;
103 }
104 else {
105 log_assert(w->port_input);
106 log_assert(b.offset < GetSize(w));
107 }
108 w->set_bool_attribute(ID(abc_scc_break));
109 module->swap_names(b.wire, w);
110 c.second = RTLIL::SigBit(w, b.offset);
111 }
112 }
113 }
114 cell->attributes.erase(it);
115 }
116 }
117
118 module->fixup_ports();
119 }
120
121 std::string add_echos_to_abc_cmd(std::string str)
122 {
123 std::string new_str, token;
124 for (size_t i = 0; i < str.size(); i++) {
125 token += str[i];
126 if (str[i] == ';') {
127 while (i+1 < str.size() && str[i+1] == ' ')
128 i++;
129 new_str += "echo + " + token + " " + token + " ";
130 token.clear();
131 }
132 }
133
134 if (!token.empty()) {
135 if (!new_str.empty())
136 new_str += "echo + " + token + "; ";
137 new_str += token;
138 }
139
140 return new_str;
141 }
142
143 std::string fold_abc_cmd(std::string str)
144 {
145 std::string token, new_str = " ";
146 int char_counter = 10;
147
148 for (size_t i = 0; i <= str.size(); i++) {
149 if (i < str.size())
150 token += str[i];
151 if (i == str.size() || str[i] == ';') {
152 if (char_counter + token.size() > 75)
153 new_str += "\n ", char_counter = 14;
154 new_str += token, char_counter += token.size();
155 token.clear();
156 }
157 }
158
159 return new_str;
160 }
161
162 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
163 {
164 if (show_tempdir)
165 return text;
166
167 while (1) {
168 size_t pos = text.find(tempdir_name);
169 if (pos == std::string::npos)
170 break;
171 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
172 }
173
174 std::string selfdir_name = proc_self_dirname();
175 if (selfdir_name != "/") {
176 while (1) {
177 size_t pos = text.find(selfdir_name);
178 if (pos == std::string::npos)
179 break;
180 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
181 }
182 }
183
184 return text;
185 }
186
187 struct abc_output_filter
188 {
189 bool got_cr;
190 int escape_seq_state;
191 std::string linebuf;
192 std::string tempdir_name;
193 bool show_tempdir;
194
195 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
196 {
197 got_cr = false;
198 escape_seq_state = 0;
199 }
200
201 void next_char(char ch)
202 {
203 if (escape_seq_state == 0 && ch == '\033') {
204 escape_seq_state = 1;
205 return;
206 }
207 if (escape_seq_state == 1) {
208 escape_seq_state = ch == '[' ? 2 : 0;
209 return;
210 }
211 if (escape_seq_state == 2) {
212 if ((ch < '0' || '9' < ch) && ch != ';')
213 escape_seq_state = 0;
214 return;
215 }
216 escape_seq_state = 0;
217 if (ch == '\r') {
218 got_cr = true;
219 return;
220 }
221 if (ch == '\n') {
222 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
223 got_cr = false, linebuf.clear();
224 return;
225 }
226 if (got_cr)
227 got_cr = false, linebuf.clear();
228 linebuf += ch;
229 }
230
231 void next_line(const std::string &line)
232 {
233 //int pi, po;
234 //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
235 // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
236 // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
237 // po, po_map.count(po) ? po_map.at(po).c_str() : "???");
238 // return;
239 //}
240
241 for (char ch : line)
242 next_char(ch);
243 }
244 };
245
246 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
247 bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
248 bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
249 bool show_tempdir, std::string box_file, std::string lut_file,
250 std::string wire_delay, const dict<int,IdString> &box_lookup
251 )
252 {
253 module = current_module;
254 map_autoidx = autoidx++;
255
256 if (clk_str != "$")
257 {
258 clk_polarity = true;
259 clk_sig = RTLIL::SigSpec();
260
261 en_polarity = true;
262 en_sig = RTLIL::SigSpec();
263 }
264
265 if (!clk_str.empty() && clk_str != "$")
266 {
267 if (clk_str.find(',') != std::string::npos) {
268 int pos = clk_str.find(',');
269 std::string en_str = clk_str.substr(pos+1);
270 clk_str = clk_str.substr(0, pos);
271 if (en_str[0] == '!') {
272 en_polarity = false;
273 en_str = en_str.substr(1);
274 }
275 if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
276 en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
277 }
278 if (clk_str[0] == '!') {
279 clk_polarity = false;
280 clk_str = clk_str.substr(1);
281 }
282 if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
283 clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
284 }
285
286 if (dff_mode && clk_sig.empty())
287 log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
288
289 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
290 if (!cleanup)
291 tempdir_name[0] = tempdir_name[4] = '_';
292 tempdir_name = make_temp_dir(tempdir_name);
293 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
294 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
295
296 std::string abc_script;
297
298 if (!lut_costs.empty()) {
299 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
300 if (!box_file.empty())
301 abc_script += stringf("read_box -v %s; ", box_file.c_str());
302 }
303 else
304 if (!lut_file.empty()) {
305 abc_script += stringf("read_lut %s; ", lut_file.c_str());
306 if (!box_file.empty())
307 abc_script += stringf("read_box -v %s; ", box_file.c_str());
308 }
309 else
310 log_abort();
311
312 abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
313
314 if (!script_file.empty()) {
315 if (script_file[0] == '+') {
316 for (size_t i = 1; i < script_file.size(); i++)
317 if (script_file[i] == '\'')
318 abc_script += "'\\''";
319 else if (script_file[i] == ',')
320 abc_script += " ";
321 else
322 abc_script += script_file[i];
323 } else
324 abc_script += stringf("source %s", script_file.c_str());
325 } else if (!lut_costs.empty() || !lut_file.empty()) {
326 //bool all_luts_cost_same = true;
327 //for (int this_cost : lut_costs)
328 // if (this_cost != lut_costs.front())
329 // all_luts_cost_same = false;
330 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
331 //if (all_luts_cost_same && !fast_mode)
332 // abc_script += "; lutpack {S}";
333 } else
334 log_abort();
335
336 //if (script_file.empty() && !delay_target.empty())
337 // for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
338 // abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
339
340 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
341 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
342
343 //for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
344 // abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
345
346 for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
347 abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
348
349 abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
350 abc_script = add_echos_to_abc_cmd(abc_script);
351
352 for (size_t i = 0; i+1 < abc_script.size(); i++)
353 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
354 abc_script[i+1] = '\n';
355
356 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
357 fprintf(f, "%s\n", abc_script.c_str());
358 fclose(f);
359
360 if (dff_mode || !clk_str.empty())
361 {
362 if (clk_sig.size() == 0)
363 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
364 else {
365 log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
366 if (en_sig.size() != 0)
367 log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
368 log("\n");
369 }
370 }
371
372 bool count_output = false;
373 for (auto port_name : module->ports) {
374 RTLIL::Wire *port_wire = module->wire(port_name);
375 log_assert(port_wire);
376 if (port_wire->port_output) {
377 count_output = true;
378 break;
379 }
380 }
381
382 log_push();
383
384 if (count_output)
385 {
386 design->selection_stack.emplace_back(false);
387 RTLIL::Selection& sel = design->selection_stack.back();
388 sel.select(module);
389
390 handle_loops(design);
391
392 Pass::call(design, "aigmap");
393
394 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
395 // count_gates, GetSize(signal_list), count_input, count_output);
396
397 Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
398
399 std::string buffer;
400 std::ifstream ifs;
401 #if 0
402 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
403 ifs.open(buffer);
404 if (ifs.fail())
405 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
406 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
407 log_assert(!design->module(ID($__abc9__)));
408 {
409 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
410 reader.parse_xaiger();
411 }
412 ifs.close();
413 Pass::call(design, stringf("write_verilog -noexpr -norename"));
414 design->remove(design->module(ID($__abc9__)));
415 #endif
416
417 design->selection_stack.pop_back();
418
419 // Now 'unexpose' those wires by undoing
420 // the expose operation -- remove them from PO/PI
421 // and re-connecting them back together
422 for (auto wire : module->wires()) {
423 auto it = wire->attributes.find(ID(abc_scc_break));
424 if (it != wire->attributes.end()) {
425 wire->attributes.erase(it);
426 log_assert(wire->port_output);
427 wire->port_output = false;
428 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
429 log_assert(i_wire);
430 log_assert(i_wire->port_input);
431 i_wire->port_input = false;
432 module->connect(i_wire, wire);
433 }
434 }
435 module->fixup_ports();
436
437 log_header(design, "Executing ABC9.\n");
438
439 if (!lut_costs.empty()) {
440 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
441 f = fopen(buffer.c_str(), "wt");
442 if (f == NULL)
443 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
444 for (int i = 0; i < GetSize(lut_costs); i++)
445 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
446 fclose(f);
447 }
448
449 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
450 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
451
452 #ifndef YOSYS_LINK_ABC
453 abc_output_filter filt(tempdir_name, show_tempdir);
454 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
455 #else
456 // These needs to be mutable, supposedly due to getopt
457 char *abc_argv[5];
458 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
459 abc_argv[0] = strdup(exe_file.c_str());
460 abc_argv[1] = strdup("-s");
461 abc_argv[2] = strdup("-f");
462 abc_argv[3] = strdup(tmp_script_name.c_str());
463 abc_argv[4] = 0;
464 int ret = Abc_RealMain(4, abc_argv);
465 free(abc_argv[0]);
466 free(abc_argv[1]);
467 free(abc_argv[2]);
468 free(abc_argv[3]);
469 #endif
470 if (ret != 0)
471 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
472
473 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
474 ifs.open(buffer);
475 if (ifs.fail())
476 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
477
478 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
479 log_assert(!design->module(ID($__abc9__)));
480
481 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
482 reader.parse_xaiger(box_lookup);
483 ifs.close();
484
485 #if 0
486 Pass::call(design, stringf("write_verilog -noexpr -norename"));
487 #endif
488
489 log_header(design, "Re-integrating ABC9 results.\n");
490 RTLIL::Module *mapped_mod = design->module(ID($__abc9__));
491 if (mapped_mod == NULL)
492 log_error("ABC output file does not contain a module `$__abc9__'.\n");
493
494 pool<RTLIL::SigBit> output_bits;
495 for (auto &it : mapped_mod->wires_) {
496 RTLIL::Wire *w = it.second;
497 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
498 if (markgroups) remap_wire->attributes[ID(abcgroup)] = map_autoidx;
499 if (w->port_output) {
500 RTLIL::Wire *wire = module->wire(w->name);
501 log_assert(wire);
502 for (int i = 0; i < GetSize(w); i++)
503 output_bits.insert({wire, i});
504 }
505 }
506
507 for (auto &it : module->connections_) {
508 auto &signal = it.first;
509 auto bits = signal.bits();
510 for (auto &b : bits)
511 if (output_bits.count(b))
512 b = module->addWire(NEW_ID);
513 signal = std::move(bits);
514 }
515
516 dict<IdString, bool> abc_box;
517 vector<RTLIL::Cell*> boxes;
518 for (const auto &it : module->cells_) {
519 auto cell = it.second;
520 if (cell->type.in(ID($_AND_), ID($_NOT_))) {
521 module->remove(cell);
522 continue;
523 }
524 auto jt = abc_box.find(cell->type);
525 if (jt == abc_box.end()) {
526 RTLIL::Module* box_module = design->module(cell->type);
527 jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first;
528 }
529 if (jt->second)
530 boxes.emplace_back(cell);
531 }
532
533 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
534 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
535 dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
536 dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
537
538 std::map<IdString, int> cell_stats;
539 for (auto c : mapped_mod->cells())
540 {
541 toposort.node(c->name);
542
543 RTLIL::Cell *cell = nullptr;
544 if (c->type == ID($_NOT_)) {
545 RTLIL::SigBit a_bit = c->getPort(ID::A);
546 RTLIL::SigBit y_bit = c->getPort(ID::Y);
547 bit_users[a_bit].insert(c->name);
548 bit_drivers[y_bit].insert(c->name);
549
550 if (!a_bit.wire) {
551 c->setPort(ID::Y, module->addWire(NEW_ID));
552 RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
553 log_assert(wire);
554 module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
555 }
556 else if (!lut_costs.empty() || !lut_file.empty()) {
557 RTLIL::Cell* driver_lut = nullptr;
558 // ABC can return NOT gates that drive POs
559 if (!a_bit.wire->port_input) {
560 // If it's not a NOT gate that that comes from a PI directly,
561 // find the driver LUT and clone that to guarantee that we won't
562 // increase the max logic depth
563 // (TODO: Optimise by not cloning unless will increase depth)
564 RTLIL::IdString driver_name;
565 if (GetSize(a_bit.wire) == 1)
566 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
567 else
568 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
569 driver_lut = mapped_mod->cell(driver_name);
570 }
571
572 if (!driver_lut) {
573 // If a driver couldn't be found (could be from PI or box CI)
574 // then implement using a LUT
575 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
576 RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
577 RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
578 RTLIL::Const::from_string("01"));
579 bit2sinks[cell->getPort(ID::A)].push_back(cell);
580 cell_stats[ID($lut)]++;
581 }
582 else
583 not2drivers[c] = driver_lut;
584 continue;
585 }
586 else
587 log_abort();
588 if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
589 continue;
590 }
591 cell_stats[c->type]++;
592
593 RTLIL::Cell *existing_cell = nullptr;
594 if (c->type == ID($lut)) {
595 if (GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
596 SigSpec my_a = module->wires_.at(remap_name(c->getPort(ID::A).as_wire()->name));
597 SigSpec my_y = module->wires_.at(remap_name(c->getPort(ID::Y).as_wire()->name));
598 module->connect(my_y, my_a);
599 if (markgroups) c->attributes[ID(abcgroup)] = map_autoidx;
600 log_abort();
601 continue;
602 }
603 cell = module->addCell(remap_name(c->name), c->type);
604 }
605 else {
606 existing_cell = module->cell(c->name);
607 log_assert(existing_cell);
608 cell = module->addCell(remap_name(c->name), c->type);
609 module->swap_names(cell, existing_cell);
610 }
611
612 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
613 if (existing_cell) {
614 cell->parameters = existing_cell->parameters;
615 cell->attributes = existing_cell->attributes;
616 }
617 else {
618 cell->parameters = c->parameters;
619 cell->attributes = c->attributes;
620 }
621 for (auto &conn : c->connections()) {
622 RTLIL::SigSpec newsig;
623 for (auto c : conn.second.chunks()) {
624 if (c.width == 0)
625 continue;
626 //log_assert(c.width == 1);
627 if (c.wire)
628 c.wire = module->wires_.at(remap_name(c.wire->name));
629 newsig.append(c);
630 }
631 cell->setPort(conn.first, newsig);
632
633 if (cell->input(conn.first)) {
634 for (auto i : newsig)
635 bit2sinks[i].push_back(cell);
636 for (auto i : conn.second)
637 bit_users[i].insert(c->name);
638 }
639 if (cell->output(conn.first))
640 for (auto i : conn.second)
641 bit_drivers[i].insert(c->name);
642 }
643 }
644
645 for (auto cell : boxes)
646 module->remove(cell);
647
648 // Copy connections (and rename) from mapped_mod to module
649 for (auto conn : mapped_mod->connections()) {
650 if (!conn.first.is_fully_const()) {
651 auto chunks = conn.first.chunks();
652 for (auto &c : chunks)
653 c.wire = module->wires_.at(remap_name(c.wire->name));
654 conn.first = std::move(chunks);
655 }
656 if (!conn.second.is_fully_const()) {
657 auto chunks = conn.second.chunks();
658 for (auto &c : chunks)
659 if (c.wire)
660 c.wire = module->wires_.at(remap_name(c.wire->name));
661 conn.second = std::move(chunks);
662 }
663 module->connect(conn);
664 }
665
666 for (auto &it : cell_stats)
667 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
668 int in_wires = 0, out_wires = 0;
669
670 // Stitch in mapped_mod's inputs/outputs into module
671 for (auto port : mapped_mod->ports) {
672 RTLIL::Wire *w = mapped_mod->wire(port);
673 RTLIL::Wire *wire = module->wire(port);
674 log_assert(wire);
675 RTLIL::Wire *remap_wire = module->wire(remap_name(port));
676 RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
677 log_assert(GetSize(signal) >= GetSize(remap_wire));
678
679 RTLIL::SigSig conn;
680 if (w->port_output) {
681 conn.first = signal;
682 conn.second = remap_wire;
683 out_wires++;
684 module->connect(conn);
685 }
686 else if (w->port_input) {
687 conn.first = remap_wire;
688 conn.second = signal;
689 in_wires++;
690 module->connect(conn);
691 }
692 }
693
694 for (auto &it : bit_users)
695 if (bit_drivers.count(it.first))
696 for (auto driver_cell : bit_drivers.at(it.first))
697 for (auto user_cell : it.second)
698 toposort.edge(driver_cell, user_cell);
699 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
700 log_assert(no_loops);
701
702 for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
703 RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
704 log_assert(not_cell);
705 if (not_cell->type != ID($_NOT_))
706 continue;
707 auto it = not2drivers.find(not_cell);
708 if (it == not2drivers.end())
709 continue;
710 RTLIL::Cell *driver_lut = it->second;
711 RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
712 RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
713 RTLIL::Const driver_mask;
714
715 a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
716 y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
717
718 auto jt = bit2sinks.find(a_bit);
719 if (jt == bit2sinks.end())
720 goto clone_lut;
721
722 for (auto sink_cell : jt->second)
723 if (sink_cell->type != ID($lut))
724 goto clone_lut;
725
726 // Push downstream LUTs past inverter
727 for (auto sink_cell : jt->second) {
728 SigSpec A = sink_cell->getPort(ID::A);
729 RTLIL::Const mask = sink_cell->getParam(ID(LUT));
730 int index = 0;
731 for (; index < GetSize(A); index++)
732 if (A[index] == a_bit)
733 break;
734 log_assert(index < GetSize(A));
735 int i = 0;
736 while (i < GetSize(mask)) {
737 for (int j = 0; j < (1 << index); j++)
738 std::swap(mask[i+j], mask[i+j+(1 << index)]);
739 i += 1 << (index+1);
740 }
741 A[index] = y_bit;
742 sink_cell->setPort(ID::A, A);
743 sink_cell->setParam(ID(LUT), mask);
744 }
745
746 // Since we have rewritten all sinks (which we know
747 // to be only LUTs) to be after the inverter, we can
748 // go ahead and clone the LUT with the expectation
749 // that the original driving LUT will become dangling
750 // and get cleaned away
751 clone_lut:
752 driver_mask = driver_lut->getParam(ID(LUT));
753 for (auto &b : driver_mask.bits) {
754 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
755 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
756 }
757 auto cell = module->addLut(NEW_ID,
758 driver_lut->getPort(ID::A),
759 y_bit,
760 driver_mask);
761 for (auto &bit : cell->connections_.at(ID::A)) {
762 bit.wire = module->wires_.at(remap_name(bit.wire->name));
763 bit2sinks[bit].push_back(cell);
764 }
765 }
766
767 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
768 log("ABC RESULTS: input signals: %8d\n", in_wires);
769 log("ABC RESULTS: output signals: %8d\n", out_wires);
770
771 design->remove(mapped_mod);
772 }
773 else
774 {
775 log("Don't call ABC as there is nothing to map.\n");
776 }
777
778 if (cleanup)
779 {
780 log("Removing temp directory.\n");
781 remove_directory(tempdir_name);
782 }
783
784 log_pop();
785 }
786
787 struct Abc9Pass : public Pass {
788 Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
789 void help() YS_OVERRIDE
790 {
791 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
792 log("\n");
793 log(" abc9 [options] [selection]\n");
794 log("\n");
795 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
796 log("library to a target architecture.\n");
797 log("\n");
798 log(" -exe <command>\n");
799 #ifdef ABCEXTERNAL
800 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
801 #else
802 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
803 #endif
804 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
805 log("\n");
806 log(" -script <file>\n");
807 log(" use the specified ABC script file instead of the default script.\n");
808 log("\n");
809 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
810 log(" string is interpreted as the command string to be passed to ABC. The\n");
811 log(" leading plus sign is removed and all commas (,) in the string are\n");
812 log(" replaced with blanks before the string is passed to ABC.\n");
813 log("\n");
814 log(" if no -script parameter is given, the following scripts are used:\n");
815 log("\n");
816 log(" for -lut/-luts (only one LUT size):\n");
817 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
818 log("\n");
819 log(" for -lut/-luts (different LUT sizes):\n");
820 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
821 log("\n");
822 log(" -fast\n");
823 log(" use different default scripts that are slightly faster (at the cost\n");
824 log(" of output quality):\n");
825 log("\n");
826 log(" for -lut/-luts:\n");
827 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
828 log("\n");
829 log(" -D <picoseconds>\n");
830 log(" set delay target. the string {D} in the default scripts above is\n");
831 log(" replaced by this option when used, and an empty string otherwise\n");
832 log(" (indicating best possible delay).\n");
833 // log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
834 // log(" default scripts above.\n");
835 log("\n");
836 // log(" -S <num>\n");
837 // log(" maximum number of LUT inputs shared.\n");
838 // log(" (replaces {S} in the default scripts above, default: -S 1)\n");
839 // log("\n");
840 log(" -lut <width>\n");
841 log(" generate netlist using luts of (max) the specified width.\n");
842 log("\n");
843 log(" -lut <w1>:<w2>\n");
844 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
845 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
846 log(" the area cost doubles with each additional input bit. the delay cost\n");
847 log(" is still constant for all lut widths.\n");
848 log("\n");
849 log(" -lut <file>\n");
850 log(" pass this file with lut library to ABC.\n");
851 log("\n");
852 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
853 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
854 log(" 2, 3, .. inputs.\n");
855 log("\n");
856 // log(" -dff\n");
857 // log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
858 // log(" clock domains are automatically partitioned in clock domains and each\n");
859 // log(" domain is passed through ABC independently.\n");
860 // log("\n");
861 // log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
862 // log(" use only the specified clock domain. this is like -dff, but only FF\n");
863 // log(" cells that belong to the specified clock domain are used.\n");
864 // log("\n");
865 // log(" -keepff\n");
866 // log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
867 // log(" them, for example for equivalence checking.)\n");
868 // log("\n");
869 log(" -nocleanup\n");
870 log(" when this option is used, the temporary files created by this pass\n");
871 log(" are not removed. this is useful for debugging.\n");
872 log("\n");
873 log(" -showtmp\n");
874 log(" print the temp dir name in log. usually this is suppressed so that the\n");
875 log(" command output is identical across runs.\n");
876 log("\n");
877 log(" -markgroups\n");
878 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
879 log(" this attribute is a unique integer for each ABC process started. This\n");
880 log(" is useful for debugging the partitioning of clock domains.\n");
881 log("\n");
882 log(" -box <file>\n");
883 log(" pass this file with box library to ABC. Use with -lut.\n");
884 log("\n");
885 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
886 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
887 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
888 log("output when passing an ABC script that writes a file. Instead write your full\n");
889 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
890 log("you want to use ABC to convert your design into another format.\n");
891 log("\n");
892 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
893 log("\n");
894 }
895 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
896 {
897 log_header(design, "Executing ABC9 pass (technology mapping using ABC9).\n");
898 log_push();
899
900 assign_map.clear();
901
902 #ifdef ABCEXTERNAL
903 std::string exe_file = ABCEXTERNAL;
904 #else
905 std::string exe_file = proc_self_dirname() + "yosys-abc";
906 #endif
907 std::string script_file, clk_str, box_file, lut_file;
908 std::string delay_target, lutin_shared = "-S 1", wire_delay;
909 bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
910 bool show_tempdir = false;
911 vector<int> lut_costs;
912 markgroups = false;
913
914 #if 0
915 cleanup = false;
916 show_tempdir = true;
917 #endif
918
919 #ifdef _WIN32
920 #ifndef ABCEXTERNAL
921 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
922 exe_file = proc_self_dirname() + "..\\yosys-abc";
923 #endif
924 #endif
925
926 size_t argidx;
927 char pwd [PATH_MAX];
928 if (!getcwd(pwd, sizeof(pwd))) {
929 log_cmd_error("getcwd failed: %s\n", strerror(errno));
930 log_abort();
931 }
932 for (argidx = 1; argidx < args.size(); argidx++) {
933 std::string arg = args[argidx];
934 if (arg == "-exe" && argidx+1 < args.size()) {
935 exe_file = args[++argidx];
936 continue;
937 }
938 if (arg == "-script" && argidx+1 < args.size()) {
939 script_file = args[++argidx];
940 rewrite_filename(script_file);
941 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
942 script_file = std::string(pwd) + "/" + script_file;
943 continue;
944 }
945 if (arg == "-D" && argidx+1 < args.size()) {
946 delay_target = "-D " + args[++argidx];
947 continue;
948 }
949 //if (arg == "-S" && argidx+1 < args.size()) {
950 // lutin_shared = "-S " + args[++argidx];
951 // continue;
952 //}
953 if (arg == "-lut" && argidx+1 < args.size()) {
954 string arg = args[++argidx];
955 size_t pos = arg.find_first_of(':');
956 int lut_mode = 0, lut_mode2 = 0;
957 if (pos != string::npos) {
958 lut_mode = atoi(arg.substr(0, pos).c_str());
959 lut_mode2 = atoi(arg.substr(pos+1).c_str());
960 } else {
961 pos = arg.find_first_of('.');
962 if (pos != string::npos) {
963 lut_file = arg;
964 rewrite_filename(lut_file);
965 if (!lut_file.empty() && !is_absolute_path(lut_file))
966 lut_file = std::string(pwd) + "/" + lut_file;
967 }
968 else {
969 lut_mode = atoi(arg.c_str());
970 lut_mode2 = lut_mode;
971 }
972 }
973 lut_costs.clear();
974 for (int i = 0; i < lut_mode; i++)
975 lut_costs.push_back(1);
976 for (int i = lut_mode; i < lut_mode2; i++)
977 lut_costs.push_back(2 << (i - lut_mode));
978 continue;
979 }
980 if (arg == "-luts" && argidx+1 < args.size()) {
981 lut_costs.clear();
982 for (auto &tok : split_tokens(args[++argidx], ",")) {
983 auto parts = split_tokens(tok, ":");
984 if (GetSize(parts) == 0 && !lut_costs.empty())
985 lut_costs.push_back(lut_costs.back());
986 else if (GetSize(parts) == 1)
987 lut_costs.push_back(atoi(parts.at(0).c_str()));
988 else if (GetSize(parts) == 2)
989 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
990 lut_costs.push_back(atoi(parts.at(1).c_str()));
991 else
992 log_cmd_error("Invalid -luts syntax.\n");
993 }
994 continue;
995 }
996 if (arg == "-fast") {
997 fast_mode = true;
998 continue;
999 }
1000 //if (arg == "-dff") {
1001 // dff_mode = true;
1002 // continue;
1003 //}
1004 //if (arg == "-clk" && argidx+1 < args.size()) {
1005 // clk_str = args[++argidx];
1006 // dff_mode = true;
1007 // continue;
1008 //}
1009 //if (arg == "-keepff") {
1010 // keepff = true;
1011 // continue;
1012 //}
1013 if (arg == "-nocleanup") {
1014 cleanup = false;
1015 continue;
1016 }
1017 if (arg == "-showtmp") {
1018 show_tempdir = true;
1019 continue;
1020 }
1021 if (arg == "-markgroups") {
1022 markgroups = true;
1023 continue;
1024 }
1025 if (arg == "-box" && argidx+1 < args.size()) {
1026 box_file = args[++argidx];
1027 continue;
1028 }
1029 if (arg == "-W" && argidx+1 < args.size()) {
1030 wire_delay = "-W " + args[++argidx];
1031 continue;
1032 }
1033 break;
1034 }
1035 extra_args(args, argidx, design);
1036
1037 // ABC expects a box file for XAIG
1038 if (box_file.empty())
1039 box_file = "+/dummy.box";
1040
1041 rewrite_filename(box_file);
1042 if (!box_file.empty() && !is_absolute_path(box_file))
1043 box_file = std::string(pwd) + "/" + box_file;
1044
1045 dict<int,IdString> box_lookup;
1046 for (auto m : design->modules()) {
1047 auto it = m->attributes.find(ID(abc_box_id));
1048 if (it == m->attributes.end())
1049 continue;
1050 if (m->name.begins_with("$paramod"))
1051 continue;
1052 auto id = it->second.as_int();
1053 auto r = box_lookup.insert(std::make_pair(id, m->name));
1054 if (!r.second)
1055 log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
1056 log_id(m), id, log_id(r.first->second));
1057 log_assert(r.second);
1058
1059 RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
1060 for (auto p : m->ports) {
1061 auto w = m->wire(p);
1062 log_assert(w);
1063 if (w->attributes.count(ID(abc_carry))) {
1064 if (w->port_input) {
1065 if (carry_in)
1066 log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
1067 carry_in = w;
1068 }
1069 else if (w->port_output) {
1070 if (carry_out)
1071 log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
1072 carry_out = w;
1073 }
1074 }
1075 }
1076 if (carry_in || carry_out) {
1077 if (carry_in && !carry_out)
1078 log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m));
1079 if (!carry_in && carry_out)
1080 log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m));
1081 // Make carry_in the last PI, and carry_out the last PO
1082 // since ABC requires it this way
1083 auto &ports = m->ports;
1084 for (auto it = ports.begin(); it != ports.end(); ) {
1085 RTLIL::Wire* w = m->wire(*it);
1086 log_assert(w);
1087 if (w == carry_in || w == carry_out) {
1088 it = ports.erase(it);
1089 continue;
1090 }
1091 if (w->port_id > carry_in->port_id)
1092 --w->port_id;
1093 if (w->port_id > carry_out->port_id)
1094 --w->port_id;
1095 log_assert(w->port_input || w->port_output);
1096 log_assert(ports[w->port_id-1] == w->name);
1097 ++it;
1098 }
1099 ports.push_back(carry_in->name);
1100 carry_in->port_id = ports.size();
1101 ports.push_back(carry_out->name);
1102 carry_out->port_id = ports.size();
1103 }
1104 }
1105
1106 for (auto mod : design->selected_modules())
1107 {
1108 if (mod->attributes.count(ID(abc_box_id)))
1109 continue;
1110
1111 if (mod->processes.size() > 0) {
1112 log("Skipping module %s as it contains processes.\n", log_id(mod));
1113 continue;
1114 }
1115
1116 assign_map.set(mod);
1117
1118 if (!dff_mode || !clk_str.empty()) {
1119 abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
1120 delay_target, lutin_shared, fast_mode, show_tempdir,
1121 box_file, lut_file, wire_delay, box_lookup);
1122 continue;
1123 }
1124
1125 CellTypes ct(design);
1126
1127 std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
1128 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1129
1130 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1131 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1132 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1133
1134 typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
1135 std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
1136 std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
1137
1138 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1139 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1140
1141 for (auto cell : all_cells)
1142 {
1143 clkdomain_t key;
1144
1145 for (auto &conn : cell->connections())
1146 for (auto bit : conn.second) {
1147 bit = assign_map(bit);
1148 if (bit.wire != nullptr) {
1149 cell_to_bit[cell].insert(bit);
1150 bit_to_cell[bit].insert(cell);
1151 if (ct.cell_input(cell->type, conn.first)) {
1152 cell_to_bit_up[cell].insert(bit);
1153 bit_to_cell_down[bit].insert(cell);
1154 }
1155 if (ct.cell_output(cell->type, conn.first)) {
1156 cell_to_bit_down[cell].insert(bit);
1157 bit_to_cell_up[bit].insert(cell);
1158 }
1159 }
1160 }
1161
1162 if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
1163 {
1164 key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
1165 }
1166 else
1167 if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
1168 {
1169 bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
1170 bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
1171 key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
1172 }
1173 else
1174 continue;
1175
1176 unassigned_cells.erase(cell);
1177 expand_queue.insert(cell);
1178 expand_queue_up.insert(cell);
1179 expand_queue_down.insert(cell);
1180
1181 assigned_cells[key].push_back(cell);
1182 assigned_cells_reverse[cell] = key;
1183 }
1184
1185 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1186 {
1187 if (!expand_queue_up.empty())
1188 {
1189 RTLIL::Cell *cell = *expand_queue_up.begin();
1190 clkdomain_t key = assigned_cells_reverse.at(cell);
1191 expand_queue_up.erase(cell);
1192
1193 for (auto bit : cell_to_bit_up[cell])
1194 for (auto c : bit_to_cell_up[bit])
1195 if (unassigned_cells.count(c)) {
1196 unassigned_cells.erase(c);
1197 next_expand_queue_up.insert(c);
1198 assigned_cells[key].push_back(c);
1199 assigned_cells_reverse[c] = key;
1200 expand_queue.insert(c);
1201 }
1202 }
1203
1204 if (!expand_queue_down.empty())
1205 {
1206 RTLIL::Cell *cell = *expand_queue_down.begin();
1207 clkdomain_t key = assigned_cells_reverse.at(cell);
1208 expand_queue_down.erase(cell);
1209
1210 for (auto bit : cell_to_bit_down[cell])
1211 for (auto c : bit_to_cell_down[bit])
1212 if (unassigned_cells.count(c)) {
1213 unassigned_cells.erase(c);
1214 next_expand_queue_up.insert(c);
1215 assigned_cells[key].push_back(c);
1216 assigned_cells_reverse[c] = key;
1217 expand_queue.insert(c);
1218 }
1219 }
1220
1221 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1222 expand_queue_up.swap(next_expand_queue_up);
1223 expand_queue_down.swap(next_expand_queue_down);
1224 }
1225 }
1226
1227 while (!expand_queue.empty())
1228 {
1229 RTLIL::Cell *cell = *expand_queue.begin();
1230 clkdomain_t key = assigned_cells_reverse.at(cell);
1231 expand_queue.erase(cell);
1232
1233 for (auto bit : cell_to_bit.at(cell)) {
1234 for (auto c : bit_to_cell[bit])
1235 if (unassigned_cells.count(c)) {
1236 unassigned_cells.erase(c);
1237 next_expand_queue.insert(c);
1238 assigned_cells[key].push_back(c);
1239 assigned_cells_reverse[c] = key;
1240 }
1241 bit_to_cell[bit].clear();
1242 }
1243
1244 if (expand_queue.empty())
1245 expand_queue.swap(next_expand_queue);
1246 }
1247
1248 clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1249 for (auto cell : unassigned_cells) {
1250 assigned_cells[key].push_back(cell);
1251 assigned_cells_reverse[cell] = key;
1252 }
1253
1254 log_header(design, "Summary of detected clock domains:\n");
1255 for (auto &it : assigned_cells)
1256 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
1257 std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
1258 std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
1259
1260 for (auto &it : assigned_cells) {
1261 clk_polarity = std::get<0>(it.first);
1262 clk_sig = assign_map(std::get<1>(it.first));
1263 en_polarity = std::get<2>(it.first);
1264 en_sig = assign_map(std::get<3>(it.first));
1265 abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
1266 keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
1267 box_file, lut_file, wire_delay, box_lookup);
1268 assign_map.set(mod);
1269 }
1270 }
1271
1272 assign_map.clear();
1273
1274 log_pop();
1275 }
1276 } Abc9Pass;
1277
1278 PRIVATE_NAMESPACE_END