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[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #if 0
26 // Based on &flow3 - better QoR but more experimental
27 #define ABC_COMMAND_LUT "&st; &ps -l; &sweep -v; &scorr; " \
28 "&st; &if {W}; &save; &st; &syn2; &if {W} -v; &save; &load; "\
29 "&st; &if -g -K 6; &dch -f; &if {W} -v; &save; &load; "\
30 "&st; &if -g -K 6; &synch2; &if {W} -v; &save; &load; "\
31 "&mfs; &ps -l"
32 #else
33 #define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps; &if {W} {D} -v; &mfs; &ps -l"
34 #endif
35
36
37 #define ABC_FAST_COMMAND_LUT "&st; &if {W} {D}"
38
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
44 #include <stdlib.h>
45 #include <stdio.h>
46 #include <string.h>
47 #include <cerrno>
48 #include <sstream>
49 #include <climits>
50
51 #ifndef _WIN32
52 # include <unistd.h>
53 # include <dirent.h>
54 #endif
55
56 #include "frontends/aiger/aigerparse.h"
57 #include "kernel/utils.h"
58
59 #ifdef YOSYS_LINK_ABC
60 extern "C" int Abc_RealMain(int argc, char *argv[]);
61 #endif
62
63 USING_YOSYS_NAMESPACE
64 PRIVATE_NAMESPACE_BEGIN
65
66 bool markgroups;
67 int map_autoidx;
68
69 inline std::string remap_name(RTLIL::IdString abc_name)
70 {
71 return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
72 }
73
74 void handle_loops(RTLIL::Design *design, RTLIL::Module *module)
75 {
76 // FIXME: Do not run on all modules in design!?!
77 Pass::call(design, "scc -set_attr abc_scc_id {} % w:*");
78
79 // For every unique SCC found, (arbitrarily) find the first
80 // cell in the component, and select (and mark) all its output
81 // wires
82 pool<RTLIL::Const> ids_seen;
83 for (auto cell : module->cells()) {
84 auto it = cell->attributes.find(ID(abc_scc_id));
85 if (it != cell->attributes.end()) {
86 auto r = ids_seen.insert(it->second);
87 if (r.second) {
88 for (auto &c : cell->connections_) {
89 if (c.second.is_fully_const()) continue;
90 if (cell->output(c.first)) {
91 SigBit b = c.second.as_bit();
92 Wire *w = b.wire;
93 log_assert(!w->port_input);
94 w->port_input = true;
95 w = module->wire(stringf("%s.abci", w->name.c_str()));
96 if (!w) {
97 w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
98 w->port_output = true;
99 }
100 else {
101 log_assert(w->port_input);
102 log_assert(b.offset < GetSize(w));
103 }
104 w->set_bool_attribute(ID(abc_scc_break));
105 module->swap_names(b.wire, w);
106 c.second = RTLIL::SigBit(w, b.offset);
107 }
108 }
109 }
110 cell->attributes.erase(it);
111 }
112 }
113
114 module->fixup_ports();
115 }
116
117 std::string add_echos_to_abc_cmd(std::string str)
118 {
119 std::string new_str, token;
120 for (size_t i = 0; i < str.size(); i++) {
121 token += str[i];
122 if (str[i] == ';') {
123 while (i+1 < str.size() && str[i+1] == ' ')
124 i++;
125 new_str += "echo + " + token + " " + token + " ";
126 token.clear();
127 }
128 }
129
130 if (!token.empty()) {
131 if (!new_str.empty())
132 new_str += "echo + " + token + "; ";
133 new_str += token;
134 }
135
136 return new_str;
137 }
138
139 std::string fold_abc_cmd(std::string str)
140 {
141 std::string token, new_str = " ";
142 int char_counter = 10;
143
144 for (size_t i = 0; i <= str.size(); i++) {
145 if (i < str.size())
146 token += str[i];
147 if (i == str.size() || str[i] == ';') {
148 if (char_counter + token.size() > 75)
149 new_str += "\n ", char_counter = 14;
150 new_str += token, char_counter += token.size();
151 token.clear();
152 }
153 }
154
155 return new_str;
156 }
157
158 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
159 {
160 if (show_tempdir)
161 return text;
162
163 while (1) {
164 size_t pos = text.find(tempdir_name);
165 if (pos == std::string::npos)
166 break;
167 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
168 }
169
170 std::string selfdir_name = proc_self_dirname();
171 if (selfdir_name != "/") {
172 while (1) {
173 size_t pos = text.find(selfdir_name);
174 if (pos == std::string::npos)
175 break;
176 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
177 }
178 }
179
180 return text;
181 }
182
183 struct abc_output_filter
184 {
185 bool got_cr;
186 int escape_seq_state;
187 std::string linebuf;
188 std::string tempdir_name;
189 bool show_tempdir;
190
191 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
192 {
193 got_cr = false;
194 escape_seq_state = 0;
195 }
196
197 void next_char(char ch)
198 {
199 if (escape_seq_state == 0 && ch == '\033') {
200 escape_seq_state = 1;
201 return;
202 }
203 if (escape_seq_state == 1) {
204 escape_seq_state = ch == '[' ? 2 : 0;
205 return;
206 }
207 if (escape_seq_state == 2) {
208 if ((ch < '0' || '9' < ch) && ch != ';')
209 escape_seq_state = 0;
210 return;
211 }
212 escape_seq_state = 0;
213 if (ch == '\r') {
214 got_cr = true;
215 return;
216 }
217 if (ch == '\n') {
218 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
219 got_cr = false, linebuf.clear();
220 return;
221 }
222 if (got_cr)
223 got_cr = false, linebuf.clear();
224 linebuf += ch;
225 }
226
227 void next_line(const std::string &line)
228 {
229 //int pi, po;
230 //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
231 // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
232 // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
233 // po, po_map.count(po) ? po_map.at(po).c_str() : "???");
234 // return;
235 //}
236
237 for (char ch : line)
238 next_char(ch);
239 }
240 };
241
242 void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
243 bool cleanup, vector<int> lut_costs, bool /*dff_mode*/, std::string /*clk_str*/,
244 bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
245 bool show_tempdir, std::string box_file, std::string lut_file,
246 std::string wire_delay, const dict<int,IdString> &box_lookup
247 )
248 {
249 map_autoidx = autoidx++;
250
251 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
252 if (!cleanup)
253 tempdir_name[0] = tempdir_name[4] = '_';
254 tempdir_name = make_temp_dir(tempdir_name);
255 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
256 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
257
258 std::string abc_script;
259
260 if (!lut_costs.empty()) {
261 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
262 if (!box_file.empty())
263 abc_script += stringf("read_box -v %s; ", box_file.c_str());
264 }
265 else
266 if (!lut_file.empty()) {
267 abc_script += stringf("read_lut %s; ", lut_file.c_str());
268 if (!box_file.empty())
269 abc_script += stringf("read_box -v %s; ", box_file.c_str());
270 }
271 else
272 log_abort();
273
274 abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
275
276 if (!script_file.empty()) {
277 if (script_file[0] == '+') {
278 for (size_t i = 1; i < script_file.size(); i++)
279 if (script_file[i] == '\'')
280 abc_script += "'\\''";
281 else if (script_file[i] == ',')
282 abc_script += " ";
283 else
284 abc_script += script_file[i];
285 } else
286 abc_script += stringf("source %s", script_file.c_str());
287 } else if (!lut_costs.empty() || !lut_file.empty()) {
288 //bool all_luts_cost_same = true;
289 //for (int this_cost : lut_costs)
290 // if (this_cost != lut_costs.front())
291 // all_luts_cost_same = false;
292 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
293 //if (all_luts_cost_same && !fast_mode)
294 // abc_script += "; lutpack {S}";
295 } else
296 log_abort();
297
298 //if (script_file.empty() && !delay_target.empty())
299 // for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
300 // abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
301
302 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
303 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
304
305 //for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
306 // abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
307
308 for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
309 abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
310
311 abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
312 abc_script = add_echos_to_abc_cmd(abc_script);
313
314 for (size_t i = 0; i+1 < abc_script.size(); i++)
315 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
316 abc_script[i+1] = '\n';
317
318 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
319 fprintf(f, "%s\n", abc_script.c_str());
320 fclose(f);
321
322 bool count_output = false;
323 for (auto port_name : module->ports) {
324 RTLIL::Wire *port_wire = module->wire(port_name);
325 log_assert(port_wire);
326 if (port_wire->port_output) {
327 count_output = true;
328 break;
329 }
330 }
331
332 log_push();
333
334 if (count_output)
335 {
336 handle_loops(design, module);
337
338 Pass::call(design, "aigmap -select");
339
340 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
341 // count_gates, GetSize(signal_list), count_input, count_output);
342
343 Pass::call(design, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name.c_str(), tempdir_name.c_str()));
344
345 std::string buffer;
346 std::ifstream ifs;
347 #if 0
348 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
349 ifs.open(buffer);
350 if (ifs.fail())
351 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
352 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
353 log_assert(!design->module(ID($__abc9__)));
354 {
355 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
356 reader.parse_xaiger();
357 }
358 ifs.close();
359 Pass::call(design, stringf("write_verilog -noexpr -norename"));
360 design->remove(design->module(ID($__abc9__)));
361 #endif
362
363 // Now 'unexpose' those wires by undoing
364 // the expose operation -- remove them from PO/PI
365 // and re-connecting them back together
366 for (auto wire : module->wires()) {
367 auto it = wire->attributes.find(ID(abc_scc_break));
368 if (it != wire->attributes.end()) {
369 wire->attributes.erase(it);
370 log_assert(wire->port_output);
371 wire->port_output = false;
372 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
373 log_assert(i_wire);
374 log_assert(i_wire->port_input);
375 i_wire->port_input = false;
376 module->connect(i_wire, wire);
377 }
378 }
379 module->fixup_ports();
380
381 log_header(design, "Executing ABC9.\n");
382
383 if (!lut_costs.empty()) {
384 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
385 f = fopen(buffer.c_str(), "wt");
386 if (f == NULL)
387 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
388 for (int i = 0; i < GetSize(lut_costs); i++)
389 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
390 fclose(f);
391 }
392
393 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
394 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
395
396 #ifndef YOSYS_LINK_ABC
397 abc_output_filter filt(tempdir_name, show_tempdir);
398 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
399 #else
400 // These needs to be mutable, supposedly due to getopt
401 char *abc_argv[5];
402 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
403 abc_argv[0] = strdup(exe_file.c_str());
404 abc_argv[1] = strdup("-s");
405 abc_argv[2] = strdup("-f");
406 abc_argv[3] = strdup(tmp_script_name.c_str());
407 abc_argv[4] = 0;
408 int ret = Abc_RealMain(4, abc_argv);
409 free(abc_argv[0]);
410 free(abc_argv[1]);
411 free(abc_argv[2]);
412 free(abc_argv[3]);
413 #endif
414 if (ret != 0)
415 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
416
417 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
418 ifs.open(buffer, std::ifstream::binary);
419 if (ifs.fail())
420 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
421
422 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
423 log_assert(!design->module(ID($__abc9__)));
424
425 AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
426 reader.parse_xaiger(box_lookup);
427 ifs.close();
428
429 #if 0
430 Pass::call(design, stringf("write_verilog -noexpr -norename"));
431 #endif
432
433 log_header(design, "Re-integrating ABC9 results.\n");
434 RTLIL::Module *mapped_mod = design->module(ID($__abc9__));
435 if (mapped_mod == NULL)
436 log_error("ABC output file does not contain a module `$__abc9__'.\n");
437
438 pool<RTLIL::SigBit> output_bits;
439 for (auto &it : mapped_mod->wires_) {
440 RTLIL::Wire *w = it.second;
441 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
442 if (markgroups) remap_wire->attributes[ID(abcgroup)] = map_autoidx;
443 if (w->port_output) {
444 RTLIL::Wire *wire = module->wire(w->name);
445 log_assert(wire);
446 for (int i = 0; i < GetSize(w); i++)
447 output_bits.insert({wire, i});
448 }
449 }
450
451 for (auto &it : module->connections_) {
452 auto &signal = it.first;
453 auto bits = signal.bits();
454 for (auto &b : bits)
455 if (output_bits.count(b))
456 b = module->addWire(NEW_ID);
457 signal = std::move(bits);
458 }
459
460 dict<IdString, bool> abc_box;
461 vector<RTLIL::Cell*> boxes;
462 for (auto cell : module->selected_cells()) {
463 if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC_FF_))) {
464 module->remove(cell);
465 continue;
466 }
467 auto jt = abc_box.find(cell->type);
468 if (jt == abc_box.end()) {
469 RTLIL::Module* box_module = design->module(cell->type);
470 jt = abc_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc_box_id)))).first;
471 }
472 if (jt->second)
473 boxes.emplace_back(cell);
474 }
475
476 dict<SigBit, pool<IdString>> bit_drivers, bit_users;
477 TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
478 dict<RTLIL::Cell*,RTLIL::Cell*> not2drivers;
479 dict<SigBit, std::vector<RTLIL::Cell*>> bit2sinks;
480
481 std::map<IdString, int> cell_stats;
482 for (auto mapped_cell : mapped_mod->cells())
483 {
484 toposort.node(mapped_cell->name);
485
486 RTLIL::Cell *cell = nullptr;
487 if (mapped_cell->type == ID($_NOT_)) {
488 RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
489 RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
490 bit_users[a_bit].insert(mapped_cell->name);
491 bit_drivers[y_bit].insert(mapped_cell->name);
492
493 if (!a_bit.wire) {
494 mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
495 RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
496 log_assert(wire);
497 module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
498 }
499 else if (!lut_costs.empty() || !lut_file.empty()) {
500 RTLIL::Cell* driver_lut = nullptr;
501 // ABC can return NOT gates that drive POs
502 if (!a_bit.wire->port_input) {
503 // If it's not a NOT gate that that comes from a PI directly,
504 // find the driver LUT and clone that to guarantee that we won't
505 // increase the max logic depth
506 // (TODO: Optimise by not cloning unless will increase depth)
507 RTLIL::IdString driver_name;
508 if (GetSize(a_bit.wire) == 1)
509 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
510 else
511 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
512 driver_lut = mapped_mod->cell(driver_name);
513 }
514
515 if (!driver_lut) {
516 // If a driver couldn't be found (could be from PI or box CI)
517 // then implement using a LUT
518 cell = module->addLut(remap_name(stringf("%s$lut", mapped_cell->name.c_str())),
519 RTLIL::SigBit(module->wires_.at(remap_name(a_bit.wire->name)), a_bit.offset),
520 RTLIL::SigBit(module->wires_.at(remap_name(y_bit.wire->name)), y_bit.offset),
521 RTLIL::Const::from_string("01"));
522 bit2sinks[cell->getPort(ID::A)].push_back(cell);
523 cell_stats[ID($lut)]++;
524 }
525 else
526 not2drivers[mapped_cell] = driver_lut;
527 continue;
528 }
529 else
530 log_abort();
531 if (cell && markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
532 continue;
533 }
534 cell_stats[mapped_cell->type]++;
535
536 RTLIL::Cell *existing_cell = nullptr;
537 if (mapped_cell->type.in(ID($lut), ID($__ABC_FF_))) {
538 if (mapped_cell->type == ID($lut) &&
539 GetSize(mapped_cell->getPort(ID::A)) == 1 &&
540 mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {
541 SigSpec my_a = module->wires_.at(remap_name(mapped_cell->getPort(ID::A).as_wire()->name));
542 SigSpec my_y = module->wires_.at(remap_name(mapped_cell->getPort(ID::Y).as_wire()->name));
543 module->connect(my_y, my_a);
544 if (markgroups) mapped_cell->attributes[ID(abcgroup)] = map_autoidx;
545 log_abort();
546 continue;
547 }
548 cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
549 }
550 else {
551 existing_cell = module->cell(mapped_cell->name);
552 log_assert(existing_cell);
553 cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
554 }
555
556 if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
557 if (existing_cell) {
558 cell->parameters = existing_cell->parameters;
559 cell->attributes = existing_cell->attributes;
560 }
561 else {
562 cell->parameters = mapped_cell->parameters;
563 cell->attributes = mapped_cell->attributes;
564 }
565
566 RTLIL::Module* box_module = design->module(mapped_cell->type);
567 auto abc_flop = box_module && box_module->attributes.count("\\abc9_flop");
568 for (auto &conn : mapped_cell->connections()) {
569 RTLIL::SigSpec newsig;
570 for (auto c : conn.second.chunks()) {
571 if (c.width == 0)
572 continue;
573 //log_assert(c.width == 1);
574 if (c.wire)
575 c.wire = module->wires_.at(remap_name(c.wire->name));
576 newsig.append(c);
577 }
578 cell->setPort(conn.first, newsig);
579
580 if (!abc_flop) {
581 if (cell->input(conn.first)) {
582 for (auto i : newsig)
583 bit2sinks[i].push_back(cell);
584 for (auto i : conn.second)
585 bit_users[i].insert(mapped_cell->name);
586 }
587 if (cell->output(conn.first))
588 for (auto i : conn.second)
589 bit_drivers[i].insert(mapped_cell->name);
590 }
591 }
592 }
593
594 for (auto existing_cell : boxes) {
595 Cell *cell = module->cell(remap_name(existing_cell->name));
596 if (cell) {
597 for (auto &conn : existing_cell->connections()) {
598 if (!conn.second.is_wire())
599 continue;
600 Wire *wire = conn.second.as_wire();
601 if (!wire->get_bool_attribute(ID(abc_padding)))
602 continue;
603 cell->unsetPort(conn.first);
604 log_debug("Dropping padded port connection for %s (%s) .%s (%s )\n", log_id(cell), cell->type.c_str(), log_id(conn.first), log_signal(conn.second));
605 }
606 module->swap_names(cell, existing_cell);
607 }
608 module->remove(existing_cell);
609 }
610
611 // Copy connections (and rename) from mapped_mod to module
612 for (auto conn : mapped_mod->connections()) {
613 if (!conn.first.is_fully_const()) {
614 auto chunks = conn.first.chunks();
615 for (auto &c : chunks)
616 c.wire = module->wires_.at(remap_name(c.wire->name));
617 conn.first = std::move(chunks);
618 }
619 if (!conn.second.is_fully_const()) {
620 auto chunks = conn.second.chunks();
621 for (auto &c : chunks)
622 if (c.wire)
623 c.wire = module->wires_.at(remap_name(c.wire->name));
624 conn.second = std::move(chunks);
625 }
626 module->connect(conn);
627 }
628
629 for (auto &it : cell_stats)
630 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
631 int in_wires = 0, out_wires = 0;
632
633 // Stitch in mapped_mod's inputs/outputs into module
634 for (auto port : mapped_mod->ports) {
635 RTLIL::Wire *w = mapped_mod->wire(port);
636 RTLIL::Wire *wire = module->wire(port);
637 log_assert(wire);
638 RTLIL::Wire *remap_wire = module->wire(remap_name(port));
639 RTLIL::SigSpec signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
640 log_assert(GetSize(signal) >= GetSize(remap_wire));
641
642 RTLIL::SigSig conn;
643 if (w->port_output) {
644 conn.first = signal;
645 conn.second = remap_wire;
646 out_wires++;
647 module->connect(conn);
648 }
649 else if (w->port_input) {
650 conn.first = remap_wire;
651 conn.second = signal;
652 in_wires++;
653 module->connect(conn);
654 }
655 }
656
657 for (auto &it : bit_users)
658 if (bit_drivers.count(it.first))
659 for (auto driver_cell : bit_drivers.at(it.first))
660 for (auto user_cell : it.second)
661 toposort.edge(driver_cell, user_cell);
662 bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
663 log_assert(no_loops);
664
665 for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {
666 RTLIL::Cell *not_cell = mapped_mod->cell(*ii);
667 log_assert(not_cell);
668 if (not_cell->type != ID($_NOT_))
669 continue;
670 auto it = not2drivers.find(not_cell);
671 if (it == not2drivers.end())
672 continue;
673 RTLIL::Cell *driver_lut = it->second;
674 RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
675 RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
676 RTLIL::Const driver_mask;
677
678 a_bit.wire = module->wires_.at(remap_name(a_bit.wire->name));
679 y_bit.wire = module->wires_.at(remap_name(y_bit.wire->name));
680
681 auto jt = bit2sinks.find(a_bit);
682 if (jt == bit2sinks.end())
683 goto clone_lut;
684
685 for (auto sink_cell : jt->second)
686 if (sink_cell->type != ID($lut))
687 goto clone_lut;
688
689 // Push downstream LUTs past inverter
690 for (auto sink_cell : jt->second) {
691 SigSpec A = sink_cell->getPort(ID::A);
692 RTLIL::Const mask = sink_cell->getParam(ID(LUT));
693 int index = 0;
694 for (; index < GetSize(A); index++)
695 if (A[index] == a_bit)
696 break;
697 log_assert(index < GetSize(A));
698 int i = 0;
699 while (i < GetSize(mask)) {
700 for (int j = 0; j < (1 << index); j++)
701 std::swap(mask[i+j], mask[i+j+(1 << index)]);
702 i += 1 << (index+1);
703 }
704 A[index] = y_bit;
705 sink_cell->setPort(ID::A, A);
706 sink_cell->setParam(ID(LUT), mask);
707 }
708
709 // Since we have rewritten all sinks (which we know
710 // to be only LUTs) to be after the inverter, we can
711 // go ahead and clone the LUT with the expectation
712 // that the original driving LUT will become dangling
713 // and get cleaned away
714 clone_lut:
715 driver_mask = driver_lut->getParam(ID(LUT));
716 for (auto &b : driver_mask.bits) {
717 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
718 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
719 }
720 auto cell = module->addLut(NEW_ID,
721 driver_lut->getPort(ID::A),
722 y_bit,
723 driver_mask);
724 for (auto &bit : cell->connections_.at(ID::A)) {
725 bit.wire = module->wires_.at(remap_name(bit.wire->name));
726 bit2sinks[bit].push_back(cell);
727 }
728 }
729
730 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
731 log("ABC RESULTS: input signals: %8d\n", in_wires);
732 log("ABC RESULTS: output signals: %8d\n", out_wires);
733
734 design->remove(mapped_mod);
735 }
736 else
737 {
738 log("Don't call ABC as there is nothing to map.\n");
739 }
740
741 if (cleanup)
742 {
743 log("Removing temp directory.\n");
744 remove_directory(tempdir_name);
745 }
746
747 log_pop();
748 }
749
750 struct Abc9Pass : public Pass {
751 Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
752 void help() YS_OVERRIDE
753 {
754 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
755 log("\n");
756 log(" abc9 [options] [selection]\n");
757 log("\n");
758 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
759 log("library to a target architecture.\n");
760 log("\n");
761 log(" -exe <command>\n");
762 #ifdef ABCEXTERNAL
763 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
764 #else
765 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
766 #endif
767 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
768 log("\n");
769 log(" -script <file>\n");
770 log(" use the specified ABC script file instead of the default script.\n");
771 log("\n");
772 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
773 log(" string is interpreted as the command string to be passed to ABC. The\n");
774 log(" leading plus sign is removed and all commas (,) in the string are\n");
775 log(" replaced with blanks before the string is passed to ABC.\n");
776 log("\n");
777 log(" if no -script parameter is given, the following scripts are used:\n");
778 log("\n");
779 log(" for -lut/-luts (only one LUT size):\n");
780 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT /*"; lutpack {S}"*/).c_str());
781 log("\n");
782 log(" for -lut/-luts (different LUT sizes):\n");
783 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
784 log("\n");
785 log(" -fast\n");
786 log(" use different default scripts that are slightly faster (at the cost\n");
787 log(" of output quality):\n");
788 log("\n");
789 log(" for -lut/-luts:\n");
790 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
791 log("\n");
792 log(" -D <picoseconds>\n");
793 log(" set delay target. the string {D} in the default scripts above is\n");
794 log(" replaced by this option when used, and an empty string otherwise\n");
795 log(" (indicating best possible delay).\n");
796 // log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
797 // log(" default scripts above.\n");
798 log("\n");
799 // log(" -S <num>\n");
800 // log(" maximum number of LUT inputs shared.\n");
801 // log(" (replaces {S} in the default scripts above, default: -S 1)\n");
802 // log("\n");
803 log(" -lut <width>\n");
804 log(" generate netlist using luts of (max) the specified width.\n");
805 log("\n");
806 log(" -lut <w1>:<w2>\n");
807 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
808 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
809 log(" the area cost doubles with each additional input bit. the delay cost\n");
810 log(" is still constant for all lut widths.\n");
811 log("\n");
812 log(" -lut <file>\n");
813 log(" pass this file with lut library to ABC.\n");
814 log("\n");
815 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
816 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
817 log(" 2, 3, .. inputs.\n");
818 log("\n");
819 // log(" -dff\n");
820 // log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
821 // log(" clock domains are automatically partitioned in clock domains and each\n");
822 // log(" domain is passed through ABC independently.\n");
823 // log("\n");
824 // log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
825 // log(" use only the specified clock domain. this is like -dff, but only FF\n");
826 // log(" cells that belong to the specified clock domain are used.\n");
827 // log("\n");
828 // log(" -keepff\n");
829 // log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
830 // log(" them, for example for equivalence checking.)\n");
831 // log("\n");
832 log(" -nocleanup\n");
833 log(" when this option is used, the temporary files created by this pass\n");
834 log(" are not removed. this is useful for debugging.\n");
835 log("\n");
836 log(" -showtmp\n");
837 log(" print the temp dir name in log. usually this is suppressed so that the\n");
838 log(" command output is identical across runs.\n");
839 log("\n");
840 log(" -markgroups\n");
841 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
842 log(" this attribute is a unique integer for each ABC process started. This\n");
843 log(" is useful for debugging the partitioning of clock domains.\n");
844 log("\n");
845 log(" -box <file>\n");
846 log(" pass this file with box library to ABC. Use with -lut.\n");
847 log("\n");
848 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
849 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
850 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
851 log("output when passing an ABC script that writes a file. Instead write your full\n");
852 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
853 log("you want to use ABC to convert your design into another format.\n");
854 log("\n");
855 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
856 log("\n");
857 }
858 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
859 {
860 log_header(design, "Executing ABC9 pass (technology mapping using ABC9).\n");
861 log_push();
862
863 #ifdef ABCEXTERNAL
864 std::string exe_file = ABCEXTERNAL;
865 #else
866 std::string exe_file = proc_self_dirname() + "yosys-abc";
867 #endif
868 std::string script_file, clk_str, box_file, lut_file;
869 std::string delay_target, lutin_shared = "-S 1", wire_delay;
870 bool fast_mode = false, /*dff_mode = false,*/ keepff = false, cleanup = true;
871 bool show_tempdir = false;
872 vector<int> lut_costs;
873 markgroups = false;
874
875 #if 0
876 cleanup = false;
877 show_tempdir = true;
878 #endif
879
880 #ifdef _WIN32
881 #ifndef ABCEXTERNAL
882 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
883 exe_file = proc_self_dirname() + "..\\yosys-abc";
884 #endif
885 #endif
886
887 size_t argidx;
888 char pwd [PATH_MAX];
889 if (!getcwd(pwd, sizeof(pwd))) {
890 log_cmd_error("getcwd failed: %s\n", strerror(errno));
891 log_abort();
892 }
893 for (argidx = 1; argidx < args.size(); argidx++) {
894 std::string arg = args[argidx];
895 if (arg == "-exe" && argidx+1 < args.size()) {
896 exe_file = args[++argidx];
897 continue;
898 }
899 if (arg == "-script" && argidx+1 < args.size()) {
900 script_file = args[++argidx];
901 rewrite_filename(script_file);
902 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
903 script_file = std::string(pwd) + "/" + script_file;
904 continue;
905 }
906 if (arg == "-D" && argidx+1 < args.size()) {
907 delay_target = "-D " + args[++argidx];
908 continue;
909 }
910 //if (arg == "-S" && argidx+1 < args.size()) {
911 // lutin_shared = "-S " + args[++argidx];
912 // continue;
913 //}
914 if (arg == "-lut" && argidx+1 < args.size()) {
915 string arg = args[++argidx];
916 size_t pos = arg.find_first_of(':');
917 int lut_mode = 0, lut_mode2 = 0;
918 if (pos != string::npos) {
919 lut_mode = atoi(arg.substr(0, pos).c_str());
920 lut_mode2 = atoi(arg.substr(pos+1).c_str());
921 } else {
922 pos = arg.find_first_of('.');
923 if (pos != string::npos) {
924 lut_file = arg;
925 rewrite_filename(lut_file);
926 if (!lut_file.empty() && !is_absolute_path(lut_file))
927 lut_file = std::string(pwd) + "/" + lut_file;
928 }
929 else {
930 lut_mode = atoi(arg.c_str());
931 lut_mode2 = lut_mode;
932 }
933 }
934 lut_costs.clear();
935 for (int i = 0; i < lut_mode; i++)
936 lut_costs.push_back(1);
937 for (int i = lut_mode; i < lut_mode2; i++)
938 lut_costs.push_back(2 << (i - lut_mode));
939 continue;
940 }
941 if (arg == "-luts" && argidx+1 < args.size()) {
942 lut_costs.clear();
943 for (auto &tok : split_tokens(args[++argidx], ",")) {
944 auto parts = split_tokens(tok, ":");
945 if (GetSize(parts) == 0 && !lut_costs.empty())
946 lut_costs.push_back(lut_costs.back());
947 else if (GetSize(parts) == 1)
948 lut_costs.push_back(atoi(parts.at(0).c_str()));
949 else if (GetSize(parts) == 2)
950 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
951 lut_costs.push_back(atoi(parts.at(1).c_str()));
952 else
953 log_cmd_error("Invalid -luts syntax.\n");
954 }
955 continue;
956 }
957 if (arg == "-fast") {
958 fast_mode = true;
959 continue;
960 }
961 //if (arg == "-dff") {
962 // dff_mode = true;
963 // continue;
964 //}
965 //if (arg == "-clk" && argidx+1 < args.size()) {
966 // clk_str = args[++argidx];
967 // dff_mode = true;
968 // continue;
969 //}
970 //if (arg == "-keepff") {
971 // keepff = true;
972 // continue;
973 //}
974 if (arg == "-nocleanup") {
975 cleanup = false;
976 continue;
977 }
978 if (arg == "-showtmp") {
979 show_tempdir = true;
980 continue;
981 }
982 if (arg == "-markgroups") {
983 markgroups = true;
984 continue;
985 }
986 if (arg == "-box" && argidx+1 < args.size()) {
987 box_file = args[++argidx];
988 continue;
989 }
990 if (arg == "-W" && argidx+1 < args.size()) {
991 wire_delay = "-W " + args[++argidx];
992 continue;
993 }
994 break;
995 }
996 extra_args(args, argidx, design);
997
998 // ABC expects a box file for XAIG
999 if (box_file.empty())
1000 box_file = "+/dummy.box";
1001
1002 rewrite_filename(box_file);
1003 if (!box_file.empty() && !is_absolute_path(box_file))
1004 box_file = std::string(pwd) + "/" + box_file;
1005
1006 dict<int,IdString> box_lookup;
1007 for (auto m : design->modules()) {
1008 auto it = m->attributes.find(ID(abc_box_id));
1009 if (it == m->attributes.end())
1010 continue;
1011 if (m->name.begins_with("$paramod"))
1012 continue;
1013 auto id = it->second.as_int();
1014 auto r = box_lookup.insert(std::make_pair(id, m->name));
1015 if (!r.second)
1016 log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
1017 log_id(m), id, log_id(r.first->second));
1018 log_assert(r.second);
1019
1020 RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
1021 for (auto p : m->ports) {
1022 auto w = m->wire(p);
1023 log_assert(w);
1024 if (w->attributes.count(ID(abc_carry))) {
1025 if (w->port_input) {
1026 if (carry_in)
1027 log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
1028 carry_in = w;
1029 }
1030 else if (w->port_output) {
1031 if (carry_out)
1032 log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
1033 carry_out = w;
1034 }
1035 }
1036 }
1037 if (carry_in || carry_out) {
1038 if (carry_in && !carry_out)
1039 log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m));
1040 if (!carry_in && carry_out)
1041 log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m));
1042 // Make carry_in the last PI, and carry_out the last PO
1043 // since ABC requires it this way
1044 auto &ports = m->ports;
1045 for (auto it = ports.begin(); it != ports.end(); ) {
1046 RTLIL::Wire* w = m->wire(*it);
1047 log_assert(w);
1048 if (w == carry_in || w == carry_out) {
1049 it = ports.erase(it);
1050 continue;
1051 }
1052 if (w->port_id > carry_in->port_id)
1053 --w->port_id;
1054 if (w->port_id > carry_out->port_id)
1055 --w->port_id;
1056 log_assert(w->port_input || w->port_output);
1057 log_assert(ports[w->port_id-1] == w->name);
1058 ++it;
1059 }
1060 ports.push_back(carry_in->name);
1061 carry_in->port_id = ports.size();
1062 ports.push_back(carry_out->name);
1063 carry_out->port_id = ports.size();
1064 }
1065 }
1066
1067 for (auto module : design->selected_modules())
1068 {
1069 if (module->attributes.count(ID(abc_box_id)))
1070 continue;
1071
1072 if (module->processes.size() > 0) {
1073 log("Skipping module %s as it contains processes.\n", log_id(module));
1074 continue;
1075 }
1076
1077 SigMap assign_map(module);
1078
1079 CellTypes ct(design);
1080
1081 std::vector<RTLIL::Cell*> all_cells = module->selected_cells();
1082 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1083
1084 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1085 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1086 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1087
1088 std::map<SigSpec, pool<RTLIL::IdString>> assigned_cells;
1089 std::map<RTLIL::Cell*, SigSpec> assigned_cells_reverse;
1090
1091 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1092 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1093
1094 typedef std::pair<IdString, SigSpec> endomain_t;
1095 std::map<endomain_t, int> mergeability_class;
1096
1097 for (auto cell : all_cells) {
1098 for (auto &conn : cell->connections())
1099 for (auto bit : assign_map(conn.second))
1100 if (bit.wire != nullptr) {
1101 cell_to_bit[cell].insert(bit);
1102 bit_to_cell[bit].insert(cell);
1103 if (ct.cell_input(cell->type, conn.first)) {
1104 cell_to_bit_up[cell].insert(bit);
1105 bit_to_cell_down[bit].insert(cell);
1106 }
1107 if (ct.cell_output(cell->type, conn.first)) {
1108 cell_to_bit_down[cell].insert(bit);
1109 bit_to_cell_up[bit].insert(cell);
1110 }
1111 }
1112
1113 auto inst_module = design->module(cell->type);
1114 if (!inst_module || !inst_module->attributes.count("\\abc9_flop"))
1115 continue;
1116
1117 auto derived_name = inst_module->derive(design, cell->parameters);
1118 auto derived_module = design->module(derived_name);
1119 log_assert(derived_module);
1120 if (derived_module->has_processes())
1121 Pass::call_on_module(design, derived_module, "proc");
1122 SigMap derived_sigmap(derived_module);
1123
1124 SigSpec pattern;
1125 SigSpec with;
1126 for (auto &conn : cell->connections()) {
1127 Wire *first = derived_module->wire(conn.first);
1128 log_assert(first);
1129 SigSpec second = assign_map(conn.second);
1130 log_assert(GetSize(first) == GetSize(second));
1131 pattern.append(first);
1132 with.append(second);
1133 }
1134
1135 Wire *abc9_clock_wire = derived_module->wire("\\$abc9_clock");
1136 if (abc9_clock_wire == NULL)
1137 log_error("'\\$abc9_clock' is not a wire present in module '%s'.\n", log_id(cell->type));
1138 SigSpec abc9_clock = derived_sigmap(abc9_clock_wire);
1139 abc9_clock.replace(pattern, with);
1140 for (const auto &c : abc9_clock.chunks())
1141 log_assert(!c.wire || c.wire->module == module);
1142
1143 Wire *abc9_control_wire = derived_module->wire("\\$abc9_control");
1144 if (abc9_control_wire == NULL)
1145 log_error("'\\$abc9_control' is not a wire present in module '%s'.\n", log_id(cell->type));
1146 SigSpec abc9_control = derived_sigmap(abc9_control_wire);
1147 abc9_control.replace(pattern, with);
1148 for (const auto &c : abc9_control.chunks())
1149 log_assert(!c.wire || c.wire->module == module);
1150
1151 unassigned_cells.erase(cell);
1152 expand_queue.insert(cell);
1153 expand_queue_up.insert(cell);
1154 expand_queue_down.insert(cell);
1155
1156 assigned_cells[abc9_clock].insert(cell->name);
1157 assigned_cells_reverse[cell] = abc9_clock;
1158
1159 endomain_t key(cell->type, abc9_control);
1160 auto r = mergeability_class.emplace(key, mergeability_class.size() + 1);
1161 auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
1162 log_assert(r2.second);
1163 }
1164
1165 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1166 {
1167 if (!expand_queue_up.empty())
1168 {
1169 RTLIL::Cell *cell = *expand_queue_up.begin();
1170 SigSpec key = assigned_cells_reverse.at(cell);
1171 expand_queue_up.erase(cell);
1172
1173 for (auto bit : cell_to_bit_up[cell])
1174 for (auto c : bit_to_cell_up[bit])
1175 if (unassigned_cells.count(c)) {
1176 unassigned_cells.erase(c);
1177 next_expand_queue_up.insert(c);
1178 assigned_cells[key].insert(c->name);
1179 assigned_cells_reverse[c] = key;
1180 expand_queue.insert(c);
1181 }
1182 }
1183
1184 if (!expand_queue_down.empty())
1185 {
1186 RTLIL::Cell *cell = *expand_queue_down.begin();
1187 SigSpec key = assigned_cells_reverse.at(cell);
1188 expand_queue_down.erase(cell);
1189
1190 for (auto bit : cell_to_bit_down[cell])
1191 for (auto c : bit_to_cell_down[bit])
1192 if (unassigned_cells.count(c)) {
1193 unassigned_cells.erase(c);
1194 next_expand_queue_up.insert(c);
1195 assigned_cells[key].insert(c->name);
1196 assigned_cells_reverse[c] = key;
1197 expand_queue.insert(c);
1198 }
1199 }
1200
1201 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1202 expand_queue_up.swap(next_expand_queue_up);
1203 expand_queue_down.swap(next_expand_queue_down);
1204 }
1205 }
1206
1207 while (!expand_queue.empty())
1208 {
1209 RTLIL::Cell *cell = *expand_queue.begin();
1210 SigSpec key = assigned_cells_reverse.at(cell);
1211 expand_queue.erase(cell);
1212
1213 for (auto bit : cell_to_bit.at(cell)) {
1214 for (auto c : bit_to_cell[bit])
1215 if (unassigned_cells.count(c)) {
1216 unassigned_cells.erase(c);
1217 next_expand_queue.insert(c);
1218 assigned_cells[key].insert(c->name);
1219 assigned_cells_reverse[c] = key;
1220 }
1221 bit_to_cell[bit].clear();
1222 }
1223
1224 if (expand_queue.empty())
1225 expand_queue.swap(next_expand_queue);
1226 }
1227
1228 SigSpec key;
1229 for (auto cell : unassigned_cells) {
1230 assigned_cells[key].insert(cell->name);
1231 assigned_cells_reverse[cell] = key;
1232 }
1233
1234 log_header(design, "Summary of detected clock domains:\n");
1235 for (auto &it : assigned_cells)
1236 log(" %d cells in clk=%s\n", GetSize(it.second), log_signal(it.first));
1237
1238 design->selection_stack.emplace_back(false);
1239 design->selected_active_module = module->name.str();
1240 for (auto &it : assigned_cells) {
1241 RTLIL::Selection& sel = design->selection_stack.back();
1242 sel.selected_members[module->name] = std::move(it.second);
1243 abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, false, "$",
1244 keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
1245 box_file, lut_file, wire_delay, box_lookup);
1246 }
1247 design->selection_stack.pop_back();
1248 design->selected_active_module.clear();
1249 }
1250
1251 log_pop();
1252 }
1253 } Abc9Pass;
1254
1255 PRIVATE_NAMESPACE_END