2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * 2019 Eddie Hung <eddie@fpgeh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
26 // Based on &flow3 - better QoR but more experimental
27 #define ABC_COMMAND_LUT "&st; &ps -l; "/*"&sweep -v;"*/" &scorr; " \
28 "&st; &if {W}; &save; &st; &syn2; &if {W}; &save; &load; "\
29 "&st; &if -g -K 6; &dch -f; &if {W}; &save; &load; "\
30 "&st; &if -g -K 6; &synch2; &if {W}; &save; &load"
32 #define ABC_COMMAND_LUT "&st; &scorr; &sweep; &dc2; &st; &dch -f; &ps -l; &if {W} {D} -v; "/*"&mfs; "*/"&ps -l"
36 #define ABC_FAST_COMMAND_LUT "&st; &retime; &if {W}"
38 #include "kernel/register.h"
39 #include "kernel/sigtools.h"
40 #include "kernel/celltypes.h"
41 #include "kernel/cost.h"
42 #include "kernel/log.h"
55 #include "frontends/aiger/aigerparse.h"
58 extern "C" int Abc_RealMain(int argc
, char *argv
[]);
62 PRIVATE_NAMESPACE_BEGIN
67 RTLIL::Module
*module
;
69 bool clk_polarity
, en_polarity
;
70 RTLIL::SigSpec clk_sig
, en_sig
;
72 std::string
remap_name(RTLIL::IdString abc_name
)
74 std::stringstream sstr
;
75 sstr
<< "$abc$" << map_autoidx
<< "$" << abc_name
.substr(1);
79 void handle_loops(RTLIL::Design
*design
)
81 Pass::call(design
, "scc -set_attr abc_scc_id {}");
83 design
->selection_stack
.emplace_back(false);
84 RTLIL::Selection
& sel
= design
->selection_stack
.back();
86 // For every unique SCC found, (arbitrarily) find the first
87 // cell in the component, and select (and mark) all its output
89 pool
<RTLIL::Const
> ids_seen
;
90 for (auto cell
: module
->cells()) {
91 auto it
= cell
->attributes
.find("\\abc_scc_id");
92 if (it
!= cell
->attributes
.end()) {
93 auto r
= ids_seen
.insert(it
->second
);
95 for (const auto &c
: cell
->connections()) {
96 if (c
.second
.is_fully_const()) continue;
97 if (cell
->output(c
.first
)) {
98 SigBit b
= c
.second
.as_bit();
100 w
->set_bool_attribute("\\abc_scc_break");
101 sel
.select(module
, w
);
105 cell
->attributes
.erase(it
);
109 // Then cut those selected wires to expose them as new PO/PI
110 Pass::call(design
, "expose -cut -sep .abc");
112 design
->selection_stack
.pop_back();
115 std::string
add_echos_to_abc_cmd(std::string str
)
117 std::string new_str
, token
;
118 for (size_t i
= 0; i
< str
.size(); i
++) {
121 while (i
+1 < str
.size() && str
[i
+1] == ' ')
123 new_str
+= "echo + " + token
+ " " + token
+ " ";
128 if (!token
.empty()) {
129 if (!new_str
.empty())
130 new_str
+= "echo + " + token
+ "; ";
137 std::string
fold_abc_cmd(std::string str
)
139 std::string token
, new_str
= " ";
140 int char_counter
= 10;
142 for (size_t i
= 0; i
<= str
.size(); i
++) {
145 if (i
== str
.size() || str
[i
] == ';') {
146 if (char_counter
+ token
.size() > 75)
147 new_str
+= "\n ", char_counter
= 14;
148 new_str
+= token
, char_counter
+= token
.size();
156 std::string
replace_tempdir(std::string text
, std::string tempdir_name
, bool show_tempdir
)
162 size_t pos
= text
.find(tempdir_name
);
163 if (pos
== std::string::npos
)
165 text
= text
.substr(0, pos
) + "<abc-temp-dir>" + text
.substr(pos
+ GetSize(tempdir_name
));
168 std::string selfdir_name
= proc_self_dirname();
169 if (selfdir_name
!= "/") {
171 size_t pos
= text
.find(selfdir_name
);
172 if (pos
== std::string::npos
)
174 text
= text
.substr(0, pos
) + "<yosys-exe-dir>/" + text
.substr(pos
+ GetSize(selfdir_name
));
181 struct abc_output_filter
184 int escape_seq_state
;
186 std::string tempdir_name
;
189 abc_output_filter(std::string tempdir_name
, bool show_tempdir
) : tempdir_name(tempdir_name
), show_tempdir(show_tempdir
)
192 escape_seq_state
= 0;
195 void next_char(char ch
)
197 if (escape_seq_state
== 0 && ch
== '\033') {
198 escape_seq_state
= 1;
201 if (escape_seq_state
== 1) {
202 escape_seq_state
= ch
== '[' ? 2 : 0;
205 if (escape_seq_state
== 2) {
206 if ((ch
< '0' || '9' < ch
) && ch
!= ';')
207 escape_seq_state
= 0;
210 escape_seq_state
= 0;
216 log("ABC: %s\n", replace_tempdir(linebuf
, tempdir_name
, show_tempdir
).c_str());
217 got_cr
= false, linebuf
.clear();
221 got_cr
= false, linebuf
.clear();
225 void next_line(const std::string
&line
)
228 //if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
229 // log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
230 // pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
231 // po, po_map.count(po) ? po_map.at(po).c_str() : "???");
240 void abc9_module(RTLIL::Design
*design
, RTLIL::Module
*current_module
, std::string script_file
, std::string exe_file
,
241 bool cleanup
, vector
<int> lut_costs
, bool dff_mode
, std::string clk_str
,
242 bool /*keepff*/, std::string delay_target
, std::string
/*lutin_shared*/, bool fast_mode
,
243 bool show_tempdir
, std::string box_file
, std::string lut_file
,
244 std::string wire_delay
)
246 module
= current_module
;
247 map_autoidx
= autoidx
++;
252 clk_sig
= RTLIL::SigSpec();
255 en_sig
= RTLIL::SigSpec();
258 if (!clk_str
.empty() && clk_str
!= "$")
260 if (clk_str
.find(',') != std::string::npos
) {
261 int pos
= clk_str
.find(',');
262 std::string en_str
= clk_str
.substr(pos
+1);
263 clk_str
= clk_str
.substr(0, pos
);
264 if (en_str
[0] == '!') {
266 en_str
= en_str
.substr(1);
268 if (module
->wires_
.count(RTLIL::escape_id(en_str
)) != 0)
269 en_sig
= assign_map(RTLIL::SigSpec(module
->wires_
.at(RTLIL::escape_id(en_str
)), 0));
271 if (clk_str
[0] == '!') {
272 clk_polarity
= false;
273 clk_str
= clk_str
.substr(1);
275 if (module
->wires_
.count(RTLIL::escape_id(clk_str
)) != 0)
276 clk_sig
= assign_map(RTLIL::SigSpec(module
->wires_
.at(RTLIL::escape_id(clk_str
)), 0));
279 if (dff_mode
&& clk_sig
.empty())
280 log_cmd_error("Clock domain %s not found.\n", clk_str
.c_str());
282 std::string tempdir_name
= "/tmp/yosys-abc-XXXXXX";
284 tempdir_name
[0] = tempdir_name
[4] = '_';
285 tempdir_name
= make_temp_dir(tempdir_name
);
286 log_header(design
, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
287 module
->name
.c_str(), replace_tempdir(tempdir_name
, tempdir_name
, show_tempdir
).c_str());
289 std::string abc_script
;
291 if (!lut_costs
.empty()) {
292 abc_script
+= stringf("read_lut %s/lutdefs.txt; ", tempdir_name
.c_str());
293 if (!box_file
.empty())
294 abc_script
+= stringf("read_box -v %s; ", box_file
.c_str());
297 if (!lut_file
.empty()) {
298 abc_script
+= stringf("read_lut %s; ", lut_file
.c_str());
299 if (!box_file
.empty())
300 abc_script
+= stringf("read_box -v %s; ", box_file
.c_str());
305 abc_script
+= stringf("&read %s/input.xaig; &ps; ", tempdir_name
.c_str());
307 if (!script_file
.empty()) {
308 if (script_file
[0] == '+') {
309 for (size_t i
= 1; i
< script_file
.size(); i
++)
310 if (script_file
[i
] == '\'')
311 abc_script
+= "'\\''";
312 else if (script_file
[i
] == ',')
315 abc_script
+= script_file
[i
];
317 abc_script
+= stringf("source %s", script_file
.c_str());
318 } else if (!lut_costs
.empty() || !lut_file
.empty()) {
319 //bool all_luts_cost_same = true;
320 //for (int this_cost : lut_costs)
321 // if (this_cost != lut_costs.front())
322 // all_luts_cost_same = false;
323 abc_script
+= fast_mode
? ABC_FAST_COMMAND_LUT
: ABC_COMMAND_LUT
;
324 //if (all_luts_cost_same && !fast_mode)
325 // abc_script += "; lutpack {S}";
329 //if (script_file.empty() && !delay_target.empty())
330 // for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
331 // abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
333 for (size_t pos
= abc_script
.find("{D}"); pos
!= std::string::npos
; pos
= abc_script
.find("{D}", pos
))
334 abc_script
= abc_script
.substr(0, pos
) + delay_target
+ abc_script
.substr(pos
+3);
336 //for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
337 // abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
339 for (size_t pos
= abc_script
.find("{W}"); pos
!= std::string::npos
; pos
= abc_script
.find("{W}", pos
))
340 abc_script
= abc_script
.substr(0, pos
) + wire_delay
+ abc_script
.substr(pos
+3);
342 abc_script
+= stringf("; &write %s/output.aig", tempdir_name
.c_str());
343 abc_script
= add_echos_to_abc_cmd(abc_script
);
345 for (size_t i
= 0; i
+1 < abc_script
.size(); i
++)
346 if (abc_script
[i
] == ';' && abc_script
[i
+1] == ' ')
347 abc_script
[i
+1] = '\n';
349 FILE *f
= fopen(stringf("%s/abc.script", tempdir_name
.c_str()).c_str(), "wt");
350 fprintf(f
, "%s\n", abc_script
.c_str());
353 if (dff_mode
|| !clk_str
.empty())
355 if (clk_sig
.size() == 0)
356 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str
.empty() ? "" : " matching");
358 log("Found%s %s clock domain: %s", clk_str
.empty() ? "" : " matching", clk_polarity
? "posedge" : "negedge", log_signal(clk_sig
));
359 if (en_sig
.size() != 0)
360 log(", enabled by %s%s", en_polarity
? "" : "!", log_signal(en_sig
));
365 bool count_output
= false;
366 for (auto port_name
: module
->ports
) {
367 RTLIL::Wire
*port_wire
= module
->wire(port_name
);
368 log_assert(port_wire
);
369 if (port_wire
->port_output
) {
379 design
->selection_stack
.emplace_back(false);
380 RTLIL::Selection
& sel
= design
->selection_stack
.back();
383 Pass::call(design
, "aigmap");
385 handle_loops(design
);
387 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
388 // count_gates, GetSize(signal_list), count_input, count_output);
390 Pass::call(design
, stringf("write_xaiger -map %s/input.sym %s/input.xaig", tempdir_name
.c_str(), tempdir_name
.c_str()));
395 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.xaig");
398 log_error("Can't open ABC output file `%s'.\n", buffer
.c_str());
399 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.sym");
400 log_assert(!design
->module("$__abc9__"));
402 AigerReader
reader(design
, ifs
, "$__abc9__", "" /* clk_name */, buffer
.c_str() /* map_filename */, true /* wideports */);
403 reader
.parse_xaiger();
406 Pass::call(design
, stringf("write_verilog -noexpr -norename"));
407 design
->remove(design
->module("$__abc9__"));
410 design
->selection_stack
.pop_back();
412 // Now 'unexpose' those wires by undoing
413 // the expose operation -- remove them from PO/PI
414 // and re-connecting them back together
415 for (auto wire
: module
->wires()) {
416 auto it
= wire
->attributes
.find("\\abc_scc_break");
417 if (it
!= wire
->attributes
.end()) {
418 wire
->attributes
.erase(it
);
419 log_assert(wire
->port_output
);
420 wire
->port_output
= false;
421 RTLIL::Wire
*i_wire
= module
->wire(wire
->name
.str() + ".abci");
423 log_assert(i_wire
->port_input
);
424 i_wire
->port_input
= false;
425 module
->connect(i_wire
, wire
);
428 module
->fixup_ports();
431 log_header(design
, "Executing ABC9.\n");
433 if (!lut_costs
.empty()) {
434 buffer
= stringf("%s/lutdefs.txt", tempdir_name
.c_str());
435 f
= fopen(buffer
.c_str(), "wt");
437 log_error("Opening %s for writing failed: %s\n", buffer
.c_str(), strerror(errno
));
438 for (int i
= 0; i
< GetSize(lut_costs
); i
++)
439 fprintf(f
, "%d %d.00 1.00\n", i
+1, lut_costs
.at(i
));
443 buffer
= stringf("%s -s -f %s/abc.script 2>&1", exe_file
.c_str(), tempdir_name
.c_str());
444 log("Running ABC command: %s\n", replace_tempdir(buffer
, tempdir_name
, show_tempdir
).c_str());
446 #ifndef YOSYS_LINK_ABC
447 abc_output_filter
filt(tempdir_name
, show_tempdir
);
448 int ret
= run_command(buffer
, std::bind(&abc_output_filter::next_line
, filt
, std::placeholders::_1
));
450 // These needs to be mutable, supposedly due to getopt
452 string tmp_script_name
= stringf("%s/abc.script", tempdir_name
.c_str());
453 abc_argv
[0] = strdup(exe_file
.c_str());
454 abc_argv
[1] = strdup("-s");
455 abc_argv
[2] = strdup("-f");
456 abc_argv
[3] = strdup(tmp_script_name
.c_str());
458 int ret
= Abc_RealMain(4, abc_argv
);
465 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer
.c_str(), ret
);
467 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "output.aig");
470 log_error("Can't open ABC output file `%s'.\n", buffer
.c_str());
472 buffer
= stringf("%s/%s", tempdir_name
.c_str(), "input.sym");
473 log_assert(!design
->module("$__abc9__"));
474 AigerReader
reader(design
, ifs
, "$__abc9__", "" /* clk_name */, buffer
.c_str() /* map_filename */, true /* wideports */);
475 reader
.parse_xaiger();
479 Pass::call(design
, stringf("write_verilog -noexpr -norename"));
482 log_header(design
, "Re-integrating ABC9 results.\n");
483 RTLIL::Module
*mapped_mod
= design
->module("$__abc9__");
484 if (mapped_mod
== NULL
)
485 log_error("ABC output file does not contain a module `$__abc9__'.\n");
487 pool
<RTLIL::SigBit
> output_bits
;
488 for (auto &it
: mapped_mod
->wires_
) {
489 RTLIL::Wire
*w
= it
.second
;
490 RTLIL::Wire
*remap_wire
= module
->addWire(remap_name(w
->name
), GetSize(w
));
491 if (markgroups
) remap_wire
->attributes
["\\abcgroup"] = map_autoidx
;
492 if (w
->port_output
) {
493 RTLIL::Wire
*wire
= module
->wire(w
->name
);
495 for (int i
= 0; i
< GetSize(wire
); i
++)
496 output_bits
.insert({wire
, i
});
500 for (auto &it
: module
->connections_
) {
501 auto &signal
= it
.first
;
502 auto bits
= signal
.bits();
504 if (output_bits
.count(b
))
505 b
= module
->addWire(NEW_ID
);
506 signal
= std::move(bits
);
509 vector
<RTLIL::Cell
*> boxes
;
510 for (auto it
= module
->cells_
.begin(); it
!= module
->cells_
.end(); ) {
511 RTLIL::Cell
* cell
= it
->second
;
512 if (cell
->type
.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
513 it
= module
->remove(it
);
516 RTLIL::Module
* box_module
= design
->module(cell
->type
);
517 if (box_module
&& box_module
->attributes
.count("\\abc_box_id"))
518 boxes
.emplace_back(it
->second
);
522 std::map
<std::string
, int> cell_stats
;
523 for (auto c
: mapped_mod
->cells())
525 if (c
->type
== "$_NOT_") {
527 RTLIL::SigBit a_bit
= c
->getPort("\\A").as_bit();
528 RTLIL::SigBit y_bit
= c
->getPort("\\Y").as_bit();
530 c
->setPort("\\Y", module
->addWire(NEW_ID
));
531 RTLIL::Wire
*wire
= module
->wire(remap_name(y_bit
.wire
->name
));
533 module
->connect(RTLIL::SigBit(wire
, y_bit
.offset
), RTLIL::S1
);
535 else if (!lut_costs
.empty() || !lut_file
.empty()) {
536 RTLIL::Cell
* driving_lut
= nullptr;
537 // ABC can return NOT gates that drive POs
538 if (!a_bit
.wire
->port_input
) {
539 // If it's not a NOT gate that that comes from a PI directly,
540 // find the driving LUT and clone that to guarantee that we won't
541 // increase the max logic depth
542 // (TODO: Optimise by not cloning unless will increase depth)
543 RTLIL::IdString driver_name
;
544 if (GetSize(a_bit
.wire
) == 1)
545 driver_name
= stringf("%s$lut", a_bit
.wire
->name
.c_str());
547 driver_name
= stringf("%s[%d]$lut", a_bit
.wire
->name
.c_str(), a_bit
.offset
);
548 driving_lut
= mapped_mod
->cell(driver_name
);
552 // If a driver couldn't be found (could be from PI,
553 // or from a box) then implement using a LUT
554 cell
= module
->addLut(remap_name(stringf("%s$lut", c
->name
.c_str())),
555 RTLIL::SigBit(module
->wires_
[remap_name(a_bit
.wire
->name
)], a_bit
.offset
),
556 RTLIL::SigBit(module
->wires_
[remap_name(y_bit
.wire
->name
)], y_bit
.offset
),
560 auto driver_a
= driving_lut
->getPort("\\A").chunks();
561 for (auto &chunk
: driver_a
)
562 chunk
.wire
= module
->wires_
[remap_name(chunk
.wire
->name
)];
563 RTLIL::Const driver_lut
= driving_lut
->getParam("\\LUT");
564 for (auto &b
: driver_lut
.bits
) {
565 if (b
== RTLIL::State::S0
) b
= RTLIL::State::S1
;
566 else if (b
== RTLIL::State::S1
) b
= RTLIL::State::S0
;
568 cell
= module
->addLut(remap_name(stringf("%s$lut", c
->name
.c_str())),
570 RTLIL::SigBit(module
->wires_
[remap_name(y_bit
.wire
->name
)], y_bit
.offset
),
575 cell
= module
->addCell(remap_name(c
->name
), "$_NOT_");
576 cell
->setPort("\\A", RTLIL::SigBit(module
->wires_
[remap_name(a_bit
.wire
->name
)], a_bit
.offset
));
577 cell
->setPort("\\Y", RTLIL::SigBit(module
->wires_
[remap_name(y_bit
.wire
->name
)], y_bit
.offset
));
578 cell_stats
[RTLIL::unescape_id(c
->type
)]++;
580 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
583 cell_stats
[RTLIL::unescape_id(c
->type
)]++;
585 if (c
->type
== "$lut") {
586 if (GetSize(c
->getPort("\\A")) == 1 && c
->getParam("\\LUT").as_int() == 2) {
587 SigSpec my_a
= module
->wires_
[remap_name(c
->getPort("\\A").as_wire()->name
)];
588 SigSpec my_y
= module
->wires_
[remap_name(c
->getPort("\\Y").as_wire()->name
)];
589 module
->connect(my_y
, my_a
);
590 if (markgroups
) c
->attributes
["\\abcgroup"] = map_autoidx
;
595 RTLIL::Cell
*cell
= module
->addCell(remap_name(c
->name
), c
->type
);
596 if (markgroups
) cell
->attributes
["\\abcgroup"] = map_autoidx
;
597 RTLIL::Cell
*existing_cell
= module
->cell(c
->name
);
599 cell
->parameters
= existing_cell
->parameters
;
600 cell
->attributes
= existing_cell
->attributes
;
603 cell
->parameters
= c
->parameters
;
604 cell
->attributes
= c
->attributes
;
606 for (auto &conn
: c
->connections()) {
607 RTLIL::SigSpec newsig
;
608 for (auto c
: conn
.second
.chunks()) {
611 //log_assert(c.width == 1);
613 c
.wire
= module
->wires_
[remap_name(c
.wire
->name
)];
616 cell
->setPort(conn
.first
, newsig
);
620 for (auto cell
: boxes
)
621 module
->remove(cell
);
623 // Copy connections (and rename) from mapped_mod to module
624 for (auto conn
: mapped_mod
->connections()) {
625 if (!conn
.first
.is_fully_const()) {
626 auto chunks
= conn
.first
.chunks();
627 for (auto &c
: chunks
)
628 c
.wire
= module
->wires_
[remap_name(c
.wire
->name
)];
629 conn
.first
= std::move(chunks
);
631 if (!conn
.second
.is_fully_const()) {
632 auto chunks
= conn
.second
.chunks();
633 for (auto &c
: chunks
)
635 c
.wire
= module
->wires_
[remap_name(c
.wire
->name
)];
636 conn
.second
= std::move(chunks
);
638 module
->connect(conn
);
641 for (auto &it
: cell_stats
)
642 log("ABC RESULTS: %15s cells: %8d\n", it
.first
.c_str(), it
.second
);
643 int in_wires
= 0, out_wires
= 0;
645 // Stitch in mapped_mod's inputs/outputs into module
646 for (auto &it
: mapped_mod
->wires_
) {
647 RTLIL::Wire
*w
= it
.second
;
648 if (!w
->port_input
&& !w
->port_output
)
650 RTLIL::Wire
*wire
= module
->wire(w
->name
);
652 RTLIL::Wire
*remap_wire
= module
->wire(remap_name(w
->name
));
653 RTLIL::SigSpec signal
= RTLIL::SigSpec(wire
, 0, GetSize(remap_wire
));
654 log_assert(GetSize(signal
) >= GetSize(remap_wire
));
656 log_assert(w
->port_input
|| w
->port_output
);
659 conn
.first
= remap_wire
;
660 conn
.second
= signal
;
662 module
->connect(conn
);
664 if (w
->port_output
) {
666 conn
.second
= remap_wire
;
668 module
->connect(conn
);
672 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
673 log("ABC RESULTS: input signals: %8d\n", in_wires
);
674 log("ABC RESULTS: output signals: %8d\n", out_wires
);
676 design
->remove(mapped_mod
);
680 log("Don't call ABC as there is nothing to map.\n");
685 log("Removing temp directory.\n");
686 remove_directory(tempdir_name
);
692 struct Abc9Pass
: public Pass
{
693 Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
694 void help() YS_OVERRIDE
696 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
698 log(" abc9 [options] [selection]\n");
700 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
701 log("library to a target architecture.\n");
703 log(" -exe <command>\n");
705 log(" use the specified command instead of \"" ABCEXTERNAL
"\" to execute ABC.\n");
707 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
709 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
711 log(" -script <file>\n");
712 log(" use the specified ABC script file instead of the default script.\n");
714 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
715 log(" string is interpreted as the command string to be passed to ABC. The\n");
716 log(" leading plus sign is removed and all commas (,) in the string are\n");
717 log(" replaced with blanks before the string is passed to ABC.\n");
719 log(" if no -script parameter is given, the following scripts are used:\n");
721 log(" for -lut/-luts (only one LUT size):\n");
722 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT
/*"; lutpack {S}"*/).c_str());
724 log(" for -lut/-luts (different LUT sizes):\n");
725 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT
).c_str());
728 log(" use different default scripts that are slightly faster (at the cost\n");
729 log(" of output quality):\n");
731 log(" for -lut/-luts:\n");
732 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT
).c_str());
734 log(" -D <picoseconds>\n");
735 log(" set delay target. the string {D} in the default scripts above is\n");
736 log(" replaced by this option when used, and an empty string otherwise\n");
737 log(" (indicating best possible delay).\n");
738 // log(" This also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
739 // log(" default scripts above.\n");
741 // log(" -S <num>\n");
742 // log(" maximum number of LUT inputs shared.\n");
743 // log(" (replaces {S} in the default scripts above, default: -S 1)\n");
745 log(" -lut <width>\n");
746 log(" generate netlist using luts of (max) the specified width.\n");
748 log(" -lut <w1>:<w2>\n");
749 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
750 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
751 log(" the area cost doubles with each additional input bit. the delay cost\n");
752 log(" is still constant for all lut widths.\n");
754 log(" -lut <file>\n");
755 log(" pass this file with lut library to ABC.\n");
757 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
758 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
759 log(" 2, 3, .. inputs.\n");
762 // log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
763 // log(" clock domains are automatically partitioned in clock domains and each\n");
764 // log(" domain is passed through ABC independently.\n");
766 // log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
767 // log(" use only the specified clock domain. this is like -dff, but only FF\n");
768 // log(" cells that belong to the specified clock domain are used.\n");
770 // log(" -keepff\n");
771 // log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
772 // log(" them, for example for equivalence checking.)\n");
774 log(" -nocleanup\n");
775 log(" when this option is used, the temporary files created by this pass\n");
776 log(" are not removed. this is useful for debugging.\n");
779 log(" print the temp dir name in log. usually this is suppressed so that the\n");
780 log(" command output is identical across runs.\n");
782 log(" -markgroups\n");
783 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
784 log(" this attribute is a unique integer for each ABC process started. This\n");
785 log(" is useful for debugging the partitioning of clock domains.\n");
787 log(" -box <file>\n");
788 log(" pass this file with box library to ABC. Use with -lut.\n");
790 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
791 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
792 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
793 log("output when passing an ABC script that writes a file. Instead write your full\n");
794 log("design as BLIF file with write_blif and then load that into ABC externally if\n");
795 log("you want to use ABC to convert your design into another format.\n");
797 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
800 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
802 log_header(design
, "Executing ABC9 pass (technology mapping using ABC9).\n");
808 std::string exe_file
= ABCEXTERNAL
;
810 std::string exe_file
= proc_self_dirname() + "yosys-abc";
812 std::string script_file
, clk_str
, box_file
, lut_file
;
813 std::string delay_target
, lutin_shared
= "-S 1", wire_delay
;
814 bool fast_mode
= false, dff_mode
= false, keepff
= false, cleanup
= true;
815 bool show_tempdir
= false;
816 vector
<int> lut_costs
;
826 if (!check_file_exists(exe_file
+ ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
827 exe_file
= proc_self_dirname() + "..\\yosys-abc";
833 if (!getcwd(pwd
, sizeof(pwd
))) {
834 log_cmd_error("getcwd failed: %s\n", strerror(errno
));
837 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
838 std::string arg
= args
[argidx
];
839 if (arg
== "-exe" && argidx
+1 < args
.size()) {
840 exe_file
= args
[++argidx
];
843 if (arg
== "-script" && argidx
+1 < args
.size()) {
844 script_file
= args
[++argidx
];
845 rewrite_filename(script_file
);
846 if (!script_file
.empty() && !is_absolute_path(script_file
) && script_file
[0] != '+')
847 script_file
= std::string(pwd
) + "/" + script_file
;
850 if (arg
== "-D" && argidx
+1 < args
.size()) {
851 delay_target
= "-D " + args
[++argidx
];
854 //if (arg == "-S" && argidx+1 < args.size()) {
855 // lutin_shared = "-S " + args[++argidx];
858 if (arg
== "-lut" && argidx
+1 < args
.size()) {
859 string arg
= args
[++argidx
];
860 size_t pos
= arg
.find_first_of(':');
861 int lut_mode
= 0, lut_mode2
= 0;
862 if (pos
!= string::npos
) {
863 lut_mode
= atoi(arg
.substr(0, pos
).c_str());
864 lut_mode2
= atoi(arg
.substr(pos
+1).c_str());
866 pos
= arg
.find_first_of('.');
867 if (pos
!= string::npos
) {
869 rewrite_filename(lut_file
);
870 if (!lut_file
.empty() && !is_absolute_path(lut_file
))
871 lut_file
= std::string(pwd
) + "/" + lut_file
;
874 lut_mode
= atoi(arg
.c_str());
875 lut_mode2
= lut_mode
;
879 for (int i
= 0; i
< lut_mode
; i
++)
880 lut_costs
.push_back(1);
881 for (int i
= lut_mode
; i
< lut_mode2
; i
++)
882 lut_costs
.push_back(2 << (i
- lut_mode
));
885 if (arg
== "-luts" && argidx
+1 < args
.size()) {
887 for (auto &tok
: split_tokens(args
[++argidx
], ",")) {
888 auto parts
= split_tokens(tok
, ":");
889 if (GetSize(parts
) == 0 && !lut_costs
.empty())
890 lut_costs
.push_back(lut_costs
.back());
891 else if (GetSize(parts
) == 1)
892 lut_costs
.push_back(atoi(parts
.at(0).c_str()));
893 else if (GetSize(parts
) == 2)
894 while (GetSize(lut_costs
) < atoi(parts
.at(0).c_str()))
895 lut_costs
.push_back(atoi(parts
.at(1).c_str()));
897 log_cmd_error("Invalid -luts syntax.\n");
901 if (arg
== "-fast") {
905 //if (arg == "-dff") {
909 //if (arg == "-clk" && argidx+1 < args.size()) {
910 // clk_str = args[++argidx];
914 //if (arg == "-keepff") {
918 if (arg
== "-nocleanup") {
922 if (arg
== "-showtmp") {
926 if (arg
== "-markgroups") {
930 if (arg
== "-box" && argidx
+1 < args
.size()) {
931 box_file
= args
[++argidx
];
932 rewrite_filename(box_file
);
933 if (!box_file
.empty() && !is_absolute_path(box_file
))
934 box_file
= std::string(pwd
) + "/" + box_file
;
937 if (arg
== "-W" && argidx
+1 < args
.size()) {
938 wire_delay
= "-W " + args
[++argidx
];
943 extra_args(args
, argidx
, design
);
945 for (auto mod
: design
->selected_modules())
947 if (mod
->attributes
.count("\\abc_box_id"))
950 if (mod
->processes
.size() > 0) {
951 log("Skipping module %s as it contains processes.\n", log_id(mod
));
957 if (!dff_mode
|| !clk_str
.empty()) {
958 abc9_module(design
, mod
, script_file
, exe_file
, cleanup
, lut_costs
, dff_mode
, clk_str
, keepff
,
959 delay_target
, lutin_shared
, fast_mode
, show_tempdir
,
960 box_file
, lut_file
, wire_delay
);
964 CellTypes
ct(design
);
966 std::vector
<RTLIL::Cell
*> all_cells
= mod
->selected_cells();
967 std::set
<RTLIL::Cell
*> unassigned_cells(all_cells
.begin(), all_cells
.end());
969 std::set
<RTLIL::Cell
*> expand_queue
, next_expand_queue
;
970 std::set
<RTLIL::Cell
*> expand_queue_up
, next_expand_queue_up
;
971 std::set
<RTLIL::Cell
*> expand_queue_down
, next_expand_queue_down
;
973 typedef tuple
<bool, RTLIL::SigSpec
, bool, RTLIL::SigSpec
> clkdomain_t
;
974 std::map
<clkdomain_t
, std::vector
<RTLIL::Cell
*>> assigned_cells
;
975 std::map
<RTLIL::Cell
*, clkdomain_t
> assigned_cells_reverse
;
977 std::map
<RTLIL::Cell
*, std::set
<RTLIL::SigBit
>> cell_to_bit
, cell_to_bit_up
, cell_to_bit_down
;
978 std::map
<RTLIL::SigBit
, std::set
<RTLIL::Cell
*>> bit_to_cell
, bit_to_cell_up
, bit_to_cell_down
;
980 for (auto cell
: all_cells
)
984 for (auto &conn
: cell
->connections())
985 for (auto bit
: conn
.second
) {
986 bit
= assign_map(bit
);
987 if (bit
.wire
!= nullptr) {
988 cell_to_bit
[cell
].insert(bit
);
989 bit_to_cell
[bit
].insert(cell
);
990 if (ct
.cell_input(cell
->type
, conn
.first
)) {
991 cell_to_bit_up
[cell
].insert(bit
);
992 bit_to_cell_down
[bit
].insert(cell
);
994 if (ct
.cell_output(cell
->type
, conn
.first
)) {
995 cell_to_bit_down
[cell
].insert(bit
);
996 bit_to_cell_up
[bit
].insert(cell
);
1001 if (cell
->type
== "$_DFF_N_" || cell
->type
== "$_DFF_P_")
1003 key
= clkdomain_t(cell
->type
== "$_DFF_P_", assign_map(cell
->getPort("\\C")), true, RTLIL::SigSpec());
1006 if (cell
->type
== "$_DFFE_NN_" || cell
->type
== "$_DFFE_NP_" || cell
->type
== "$_DFFE_PN_" || cell
->type
== "$_DFFE_PP_")
1008 bool this_clk_pol
= cell
->type
== "$_DFFE_PN_" || cell
->type
== "$_DFFE_PP_";
1009 bool this_en_pol
= cell
->type
== "$_DFFE_NP_" || cell
->type
== "$_DFFE_PP_";
1010 key
= clkdomain_t(this_clk_pol
, assign_map(cell
->getPort("\\C")), this_en_pol
, assign_map(cell
->getPort("\\E")));
1015 unassigned_cells
.erase(cell
);
1016 expand_queue
.insert(cell
);
1017 expand_queue_up
.insert(cell
);
1018 expand_queue_down
.insert(cell
);
1020 assigned_cells
[key
].push_back(cell
);
1021 assigned_cells_reverse
[cell
] = key
;
1024 while (!expand_queue_up
.empty() || !expand_queue_down
.empty())
1026 if (!expand_queue_up
.empty())
1028 RTLIL::Cell
*cell
= *expand_queue_up
.begin();
1029 clkdomain_t key
= assigned_cells_reverse
.at(cell
);
1030 expand_queue_up
.erase(cell
);
1032 for (auto bit
: cell_to_bit_up
[cell
])
1033 for (auto c
: bit_to_cell_up
[bit
])
1034 if (unassigned_cells
.count(c
)) {
1035 unassigned_cells
.erase(c
);
1036 next_expand_queue_up
.insert(c
);
1037 assigned_cells
[key
].push_back(c
);
1038 assigned_cells_reverse
[c
] = key
;
1039 expand_queue
.insert(c
);
1043 if (!expand_queue_down
.empty())
1045 RTLIL::Cell
*cell
= *expand_queue_down
.begin();
1046 clkdomain_t key
= assigned_cells_reverse
.at(cell
);
1047 expand_queue_down
.erase(cell
);
1049 for (auto bit
: cell_to_bit_down
[cell
])
1050 for (auto c
: bit_to_cell_down
[bit
])
1051 if (unassigned_cells
.count(c
)) {
1052 unassigned_cells
.erase(c
);
1053 next_expand_queue_up
.insert(c
);
1054 assigned_cells
[key
].push_back(c
);
1055 assigned_cells_reverse
[c
] = key
;
1056 expand_queue
.insert(c
);
1060 if (expand_queue_up
.empty() && expand_queue_down
.empty()) {
1061 expand_queue_up
.swap(next_expand_queue_up
);
1062 expand_queue_down
.swap(next_expand_queue_down
);
1066 while (!expand_queue
.empty())
1068 RTLIL::Cell
*cell
= *expand_queue
.begin();
1069 clkdomain_t key
= assigned_cells_reverse
.at(cell
);
1070 expand_queue
.erase(cell
);
1072 for (auto bit
: cell_to_bit
.at(cell
)) {
1073 for (auto c
: bit_to_cell
[bit
])
1074 if (unassigned_cells
.count(c
)) {
1075 unassigned_cells
.erase(c
);
1076 next_expand_queue
.insert(c
);
1077 assigned_cells
[key
].push_back(c
);
1078 assigned_cells_reverse
[c
] = key
;
1080 bit_to_cell
[bit
].clear();
1083 if (expand_queue
.empty())
1084 expand_queue
.swap(next_expand_queue
);
1087 clkdomain_t
key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1088 for (auto cell
: unassigned_cells
) {
1089 assigned_cells
[key
].push_back(cell
);
1090 assigned_cells_reverse
[cell
] = key
;
1093 log_header(design
, "Summary of detected clock domains:\n");
1094 for (auto &it
: assigned_cells
)
1095 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it
.second
),
1096 std::get
<0>(it
.first
) ? "" : "!", log_signal(std::get
<1>(it
.first
)),
1097 std::get
<2>(it
.first
) ? "" : "!", log_signal(std::get
<3>(it
.first
)));
1099 for (auto &it
: assigned_cells
) {
1100 clk_polarity
= std::get
<0>(it
.first
);
1101 clk_sig
= assign_map(std::get
<1>(it
.first
));
1102 en_polarity
= std::get
<2>(it
.first
);
1103 en_sig
= assign_map(std::get
<3>(it
.first
));
1104 abc9_module(design
, mod
, script_file
, exe_file
, cleanup
, lut_costs
, !clk_sig
.empty(), "$",
1105 keepff
, delay_target
, lutin_shared
, fast_mode
, show_tempdir
,
1106 box_file
, lut_file
, wire_delay
);
1107 assign_map
.set(mod
);
1111 Pass::call(design
, "clean");
1119 PRIVATE_NAMESPACE_END