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abc9 to write_xaiger -symbols, not -map
[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] ABC
21 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
22 // http://www.eecs.berkeley.edu/~alanmi/abc/
23
24 // [[CITE]] Berkeley Logic Interchange Format (BLIF)
25 // University of California. Berkeley. July 28, 1992
26 // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
27
28 // [[CITE]] Kahn's Topological sorting algorithm
29 // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
30 // http://en.wikipedia.org/wiki/Topological_sorting
31
32 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
33 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
34 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
35 #define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs"
36 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
37 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
38
39 #define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
40 #define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
41 #define ABC_FAST_COMMAND_LUT "&st; &retime; &if"
42 #define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
43 #define ABC_FAST_COMMAND_DFL "strash; dretime; map"
44
45 #include "kernel/register.h"
46 #include "kernel/sigtools.h"
47 #include "kernel/celltypes.h"
48 #include "kernel/cost.h"
49 #include "kernel/log.h"
50 #include <stdlib.h>
51 #include <stdio.h>
52 #include <string.h>
53 #include <cerrno>
54 #include <sstream>
55 #include <climits>
56
57 #ifndef _WIN32
58 # include <unistd.h>
59 # include <dirent.h>
60 #endif
61
62 #include "frontends/aiger/aigerparse.h"
63
64 #ifdef YOSYS_LINK_ABC
65 extern "C" int Abc_RealMain(int argc, char *argv[]);
66 #endif
67
68 USING_YOSYS_NAMESPACE
69 PRIVATE_NAMESPACE_BEGIN
70
71 bool map_mux4;
72 bool map_mux8;
73 bool map_mux16;
74
75 bool markgroups;
76 int map_autoidx;
77 SigMap assign_map;
78 RTLIL::Module *module;
79 std::map<RTLIL::SigBit, int> signal_map;
80 std::map<RTLIL::SigBit, RTLIL::State> signal_init;
81 pool<std::string> enabled_gates;
82 bool recover_init;
83
84 bool clk_polarity, en_polarity;
85 RTLIL::SigSpec clk_sig, en_sig;
86 dict<int, std::string> pi_map, po_map;
87
88 std::string remap_name(RTLIL::IdString abc_name)
89 {
90 std::stringstream sstr;
91 sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
92 return sstr.str();
93 }
94
95 void handle_loops(RTLIL::Design *design)
96 {
97 Pass::call(design, "scc -set_attr abc_scc_id {}");
98
99 design->selection_stack.emplace_back(false);
100 RTLIL::Selection& sel = design->selection_stack.back();
101
102 // For every unique SCC found, (arbitrarily) find the first
103 // cell in the component, and select (and mark) all its output
104 // wires
105 pool<RTLIL::Const> ids_seen;
106 for (auto cell : module->cells()) {
107 auto it = cell->attributes.find("\\abc_scc_id");
108 if (it != cell->attributes.end()) {
109 auto r = ids_seen.insert(it->second);
110 if (r.second) {
111 for (const auto &c : cell->connections()) {
112 if (c.second.is_fully_const()) continue;
113 if (cell->output(c.first)) {
114 SigBit b = c.second.as_bit();
115 Wire *w = b.wire;
116 w->set_bool_attribute("\\abc_scc_break");
117 sel.select(module, w);
118 }
119 }
120 }
121 cell->attributes.erase(it);
122 }
123 }
124
125 // Then cut those selected wires to expose them as new PO/PI
126 Pass::call(design, "expose -cut -sep .abc");
127
128 design->selection_stack.pop_back();
129 }
130
131 std::string add_echos_to_abc_cmd(std::string str)
132 {
133 std::string new_str, token;
134 for (size_t i = 0; i < str.size(); i++) {
135 token += str[i];
136 if (str[i] == ';') {
137 while (i+1 < str.size() && str[i+1] == ' ')
138 i++;
139 new_str += "echo + " + token + " " + token + " ";
140 token.clear();
141 }
142 }
143
144 if (!token.empty()) {
145 if (!new_str.empty())
146 new_str += "echo + " + token + "; ";
147 new_str += token;
148 }
149
150 return new_str;
151 }
152
153 std::string fold_abc_cmd(std::string str)
154 {
155 std::string token, new_str = " ";
156 int char_counter = 10;
157
158 for (size_t i = 0; i <= str.size(); i++) {
159 if (i < str.size())
160 token += str[i];
161 if (i == str.size() || str[i] == ';') {
162 if (char_counter + token.size() > 75)
163 new_str += "\n ", char_counter = 14;
164 new_str += token, char_counter += token.size();
165 token.clear();
166 }
167 }
168
169 return new_str;
170 }
171
172 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
173 {
174 if (show_tempdir)
175 return text;
176
177 while (1) {
178 size_t pos = text.find(tempdir_name);
179 if (pos == std::string::npos)
180 break;
181 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
182 }
183
184 std::string selfdir_name = proc_self_dirname();
185 if (selfdir_name != "/") {
186 while (1) {
187 size_t pos = text.find(selfdir_name);
188 if (pos == std::string::npos)
189 break;
190 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
191 }
192 }
193
194 return text;
195 }
196
197 struct abc_output_filter
198 {
199 bool got_cr;
200 int escape_seq_state;
201 std::string linebuf;
202 std::string tempdir_name;
203 bool show_tempdir;
204
205 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
206 {
207 got_cr = false;
208 escape_seq_state = 0;
209 }
210
211 void next_char(char ch)
212 {
213 if (escape_seq_state == 0 && ch == '\033') {
214 escape_seq_state = 1;
215 return;
216 }
217 if (escape_seq_state == 1) {
218 escape_seq_state = ch == '[' ? 2 : 0;
219 return;
220 }
221 if (escape_seq_state == 2) {
222 if ((ch < '0' || '9' < ch) && ch != ';')
223 escape_seq_state = 0;
224 return;
225 }
226 escape_seq_state = 0;
227 if (ch == '\r') {
228 got_cr = true;
229 return;
230 }
231 if (ch == '\n') {
232 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
233 got_cr = false, linebuf.clear();
234 return;
235 }
236 if (got_cr)
237 got_cr = false, linebuf.clear();
238 linebuf += ch;
239 }
240
241 void next_line(const std::string &line)
242 {
243 int pi, po;
244 if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
245 log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
246 pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
247 po, po_map.count(po) ? po_map.at(po).c_str() : "???");
248 return;
249 }
250
251 for (char ch : line)
252 next_char(ch);
253 }
254 };
255
256 static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
257 {
258 int pos = -1;
259
260 if (name.empty() || name.back() != ']')
261 goto failed;
262
263 for (int i = 0; i+1 < GetSize(name); i++) {
264 if (name[i] == '[')
265 pos = i;
266 else if (name[i] < '0' || name[i] > '9')
267 pos = -1;
268 else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
269 pos = -1;
270 }
271
272 if (pos >= 0)
273 return std::pair<RTLIL::IdString, int>(RTLIL::escape_id(name.substr(0, pos)), atoi(name.c_str() + pos+1));
274
275 failed:
276 return std::pair<RTLIL::IdString, int>(name, 0);
277 }
278
279 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
280 std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
281 bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
282 const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
283 {
284 module = current_module;
285 map_autoidx = autoidx++;
286
287 signal_map.clear();
288 pi_map.clear();
289 po_map.clear();
290 recover_init = false;
291
292 if (clk_str != "$")
293 {
294 clk_polarity = true;
295 clk_sig = RTLIL::SigSpec();
296
297 en_polarity = true;
298 en_sig = RTLIL::SigSpec();
299 }
300
301 if (!clk_str.empty() && clk_str != "$")
302 {
303 if (clk_str.find(',') != std::string::npos) {
304 int pos = clk_str.find(',');
305 std::string en_str = clk_str.substr(pos+1);
306 clk_str = clk_str.substr(0, pos);
307 if (en_str[0] == '!') {
308 en_polarity = false;
309 en_str = en_str.substr(1);
310 }
311 if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
312 en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
313 }
314 if (clk_str[0] == '!') {
315 clk_polarity = false;
316 clk_str = clk_str.substr(1);
317 }
318 if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
319 clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
320 }
321
322 if (dff_mode && clk_sig.empty())
323 log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
324
325 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
326 if (!cleanup)
327 tempdir_name[0] = tempdir_name[4] = '_';
328 tempdir_name = make_temp_dir(tempdir_name);
329 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
330 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
331
332 std::string abc_script = stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
333
334 if (!liberty_file.empty()) {
335 abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
336 if (!constr_file.empty())
337 abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
338 } else
339 if (!lut_costs.empty())
340 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
341 else
342 abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
343
344 if (!script_file.empty()) {
345 if (script_file[0] == '+') {
346 for (size_t i = 1; i < script_file.size(); i++)
347 if (script_file[i] == '\'')
348 abc_script += "'\\''";
349 else if (script_file[i] == ',')
350 abc_script += " ";
351 else
352 abc_script += script_file[i];
353 } else
354 abc_script += stringf("source %s", script_file.c_str());
355 } else if (!lut_costs.empty()) {
356 bool all_luts_cost_same = true;
357 for (int this_cost : lut_costs)
358 if (this_cost != lut_costs.front())
359 all_luts_cost_same = false;
360 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
361 //if (all_luts_cost_same && !fast_mode)
362 // abc_script += "; lutpack {S}";
363 } else if (!liberty_file.empty())
364 abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
365 else if (sop_mode)
366 abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
367 else
368 abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
369
370 if (script_file.empty() && !delay_target.empty())
371 for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
372 abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
373
374 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
375 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
376
377 for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
378 abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
379
380 for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
381 abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
382
383 for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
384 abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
385
386 abc_script += stringf("; &ps; &write %s/output.xaig", tempdir_name.c_str());
387 abc_script = add_echos_to_abc_cmd(abc_script);
388
389 for (size_t i = 0; i+1 < abc_script.size(); i++)
390 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
391 abc_script[i+1] = '\n';
392
393 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
394 fprintf(f, "%s\n", abc_script.c_str());
395 fclose(f);
396
397 if (dff_mode || !clk_str.empty())
398 {
399 if (clk_sig.size() == 0)
400 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
401 else {
402 log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
403 if (en_sig.size() != 0)
404 log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
405 log("\n");
406 }
407 }
408
409 design->selection_stack.emplace_back(false);
410 RTLIL::Selection& sel = design->selection_stack.back();
411 sel.select(module);
412
413 Pass::call(design, "aigmap; clean;");
414
415 handle_loops(design);
416
417 Pass::call(design, stringf("write_xaiger -O -symbols %s/input.xaig; ", tempdir_name.c_str()));
418
419 design->selection_stack.pop_back();
420
421 // Now 'unexpose' those wires by undoing
422 // the expose operation -- remove them from PO/PI
423 // and re-connecting them back together
424 for (auto wire : module->wires()) {
425 auto it = wire->attributes.find("\\abc_scc_break");
426 if (it != wire->attributes.end()) {
427 wire->attributes.erase(it);
428 log_assert(wire->port_output);
429 wire->port_output = false;
430 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
431 log_assert(i_wire);
432 log_assert(i_wire->port_input);
433 i_wire->port_input = false;
434 module->connect(i_wire, wire);
435 }
436 }
437 module->fixup_ports();
438
439 log_push();
440
441 //if (count_output > 0)
442 {
443 log_header(design, "Executing ABC9.\n");
444
445 std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
446 f = fopen(buffer.c_str(), "wt");
447 if (f == NULL)
448 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
449 fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
450 fprintf(f, "GATE ONE 1 Y=CONST1;\n");
451 fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
452 fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
453 if (enabled_gates.empty() || enabled_gates.count("AND"))
454 fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
455 if (enabled_gates.empty() || enabled_gates.count("NAND"))
456 fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
457 if (enabled_gates.empty() || enabled_gates.count("OR"))
458 fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
459 if (enabled_gates.empty() || enabled_gates.count("NOR"))
460 fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
461 if (enabled_gates.empty() || enabled_gates.count("XOR"))
462 fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
463 if (enabled_gates.empty() || enabled_gates.count("XNOR"))
464 fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
465 if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
466 fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
467 if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
468 fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
469 if (enabled_gates.empty() || enabled_gates.count("AOI3"))
470 fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
471 if (enabled_gates.empty() || enabled_gates.count("OAI3"))
472 fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
473 if (enabled_gates.empty() || enabled_gates.count("AOI4"))
474 fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
475 if (enabled_gates.empty() || enabled_gates.count("OAI4"))
476 fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
477 if (enabled_gates.empty() || enabled_gates.count("MUX"))
478 fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
479 if (map_mux4)
480 fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
481 if (map_mux8)
482 fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
483 if (map_mux16)
484 fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
485 fclose(f);
486
487 if (!lut_costs.empty()) {
488 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
489 f = fopen(buffer.c_str(), "wt");
490 if (f == NULL)
491 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
492 for (int i = 0; i < GetSize(lut_costs); i++)
493 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
494 fclose(f);
495 }
496
497 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
498 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
499
500 #ifndef YOSYS_LINK_ABC
501 abc_output_filter filt(tempdir_name, show_tempdir);
502 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
503 #else
504 // These needs to be mutable, supposedly due to getopt
505 char *abc_argv[5];
506 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
507 abc_argv[0] = strdup(exe_file.c_str());
508 abc_argv[1] = strdup("-s");
509 abc_argv[2] = strdup("-f");
510 abc_argv[3] = strdup(tmp_script_name.c_str());
511 abc_argv[4] = 0;
512 int ret = Abc_RealMain(4, abc_argv);
513 free(abc_argv[0]);
514 free(abc_argv[1]);
515 free(abc_argv[2]);
516 free(abc_argv[3]);
517 #endif
518 if (ret != 0)
519 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
520
521 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.xaig");
522 std::ifstream ifs;
523 ifs.open(buffer);
524 if (ifs.fail())
525 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
526
527 bool builtin_lib = liberty_file.empty();
528 RTLIL::Design *mapped_design = new RTLIL::Design;
529 //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
530 AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", "", true /* wideports */);
531 reader.parse_xaiger();
532
533 ifs.close();
534
535 log_header(design, "Re-integrating ABC9 results.\n");
536 RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
537 if (mapped_mod == NULL)
538 log_error("ABC output file does not contain a module `netlist'.\n");
539
540 pool<RTLIL::SigBit> output_bits;
541 for (auto &it : mapped_mod->wires_) {
542 RTLIL::Wire *w = it.second;
543 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
544 if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
545 design->select(module, remap_wire);
546 if (w->port_output) {
547 RTLIL::Wire *wire = module->wire(w->name);
548 if (wire) {
549 for (int i = 0; i < GetSize(wire); i++)
550 output_bits.insert({wire, i});
551 }
552 else {
553 if (w->name.str() == "\\__dummy_o__") {
554 log("Don't call ABC as there is nothing to map.\n");
555 goto cleanup;
556 }
557
558 auto r = wideports_split(w->name.str());
559 wire = module->wire(r.first);
560 log_assert(wire);
561 int i = r.second;
562 output_bits.insert({wire, i});
563 }
564 }
565 }
566
567 std::map<std::string, int> cell_stats;
568 for (auto c : mapped_mod->cells())
569 {
570 if (builtin_lib)
571 {
572 if (c->type == "$_NOT_") {
573 RTLIL::Cell *cell;
574 RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
575 RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
576 if (!lut_costs.empty()) {
577 // ABC can return NOT gates that drive POs
578 if (a_bit.wire->port_input) {
579 // If it's a NOT gate that comes from a primary input directly
580 // then implement it using a LUT
581 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
582 RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
583 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
584 1);
585 }
586 else {
587 // Otherwise, clone the driving LUT to guarantee that we
588 // won't increase the max logic depth
589 // (TODO: Optimise by not cloning unless will increase depth)
590 RTLIL::IdString driver_name;
591 if (GetSize(a_bit.wire) == 1)
592 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
593 else
594 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
595 RTLIL::Cell* driver = mapped_mod->cell(driver_name);
596 log_assert(driver);
597 auto driver_a = driver->getPort("\\A").chunks();
598 for (auto &chunk : driver_a)
599 chunk.wire = module->wires_[remap_name(chunk.wire->name)];
600 RTLIL::Const driver_lut = driver->getParam("\\LUT");
601 for (auto &b : driver_lut.bits) {
602 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
603 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
604 }
605 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
606 driver_a,
607 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
608 driver_lut);
609 }
610 cell_stats["$lut"]++;
611 }
612 else {
613 cell = module->addCell(remap_name(c->name), "$_NOT_");
614 cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
615 cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
616 cell_stats[RTLIL::unescape_id(c->type)]++;
617 }
618 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
619 design->select(module, cell);
620 continue;
621 }
622
623 cell_stats[RTLIL::unescape_id(c->type)]++;
624 if (c->type == "\\ZERO" || c->type == "\\ONE") {
625 RTLIL::SigSig conn;
626 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
627 conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
628 module->connect(conn);
629 continue;
630 }
631 if (c->type == "\\BUF") {
632 RTLIL::SigSig conn;
633 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
634 conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
635 module->connect(conn);
636 continue;
637 }
638
639 if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" ||
640 c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") {
641 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
642 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
643 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
644 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
645 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
646 design->select(module, cell);
647 continue;
648 }
649 if (c->type == "\\MUX") {
650 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
651 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
652 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
653 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
654 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
655 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
656 design->select(module, cell);
657 continue;
658 }
659 if (c->type == "\\MUX4") {
660 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_");
661 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
662 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
663 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
664 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
665 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
666 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
667 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
668 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
669 design->select(module, cell);
670 continue;
671 }
672 if (c->type == "\\MUX8") {
673 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_");
674 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
675 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
676 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
677 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
678 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
679 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
680 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
681 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
682 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
683 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
684 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
685 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
686 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
687 design->select(module, cell);
688 continue;
689 }
690 if (c->type == "\\MUX16") {
691 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_");
692 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
693 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
694 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
695 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
696 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
697 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
698 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
699 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
700 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
701 cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)]));
702 cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)]));
703 cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)]));
704 cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)]));
705 cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)]));
706 cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)]));
707 cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)]));
708 cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)]));
709 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
710 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
711 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
712 cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)]));
713 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
714 design->select(module, cell);
715 continue;
716 }
717 if (c->type == "\\AOI3" || c->type == "\\OAI3") {
718 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
719 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
720 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
721 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
722 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
723 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
724 design->select(module, cell);
725 continue;
726 }
727 if (c->type == "\\AOI4" || c->type == "\\OAI4") {
728 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
729 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
730 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
731 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
732 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
733 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
734 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
735 design->select(module, cell);
736 continue;
737 }
738 if (c->type == "\\DFF") {
739 log_assert(clk_sig.size() == 1);
740 RTLIL::Cell *cell;
741 if (en_sig.size() == 0) {
742 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
743 } else {
744 log_assert(en_sig.size() == 1);
745 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
746 cell->setPort("\\E", en_sig);
747 }
748 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
749 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
750 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
751 cell->setPort("\\C", clk_sig);
752 design->select(module, cell);
753 continue;
754 }
755 }
756 else
757 cell_stats[RTLIL::unescape_id(c->type)]++;
758
759 if (c->type == "\\_const0_" || c->type == "\\_const1_") {
760 RTLIL::SigSig conn;
761 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
762 conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
763 module->connect(conn);
764 continue;
765 }
766
767 if (c->type == "\\_dff_") {
768 log_assert(clk_sig.size() == 1);
769 RTLIL::Cell *cell;
770 if (en_sig.size() == 0) {
771 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
772 } else {
773 log_assert(en_sig.size() == 1);
774 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
775 cell->setPort("\\E", en_sig);
776 }
777 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
778 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
779 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
780 cell->setPort("\\C", clk_sig);
781 design->select(module, cell);
782 continue;
783 }
784
785 if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
786 SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
787 SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
788 module->connect(my_y, my_a);
789 continue;
790 }
791
792 RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
793 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
794 cell->parameters = c->parameters;
795 for (auto &conn : c->connections()) {
796 RTLIL::SigSpec newsig;
797 for (auto c : conn.second.chunks()) {
798 if (c.width == 0)
799 continue;
800 //log_assert(c.width == 1);
801 c.wire = module->wires_[remap_name(c.wire->name)];
802 newsig.append(c);
803 }
804 cell->setPort(conn.first, newsig);
805 }
806 design->select(module, cell);
807 }
808
809 // Copy connections (and rename) from mapped_mod to module
810 for (auto conn : mapped_mod->connections()) {
811 if (!conn.first.is_fully_const()) {
812 auto chunks = conn.first.chunks();
813 for (auto &c : chunks)
814 c.wire = module->wires_[remap_name(c.wire->name)];
815 conn.first = std::move(chunks);
816 }
817 if (!conn.second.is_fully_const()) {
818 auto chunks = conn.second.chunks();
819 for (auto &c : chunks)
820 if (c.wire)
821 c.wire = module->wires_[remap_name(c.wire->name)];
822 conn.second = std::move(chunks);
823 }
824 module->connect(conn);
825 }
826
827 if (recover_init)
828 for (auto wire : mapped_mod->wires()) {
829 if (wire->attributes.count("\\init")) {
830 Wire *w = module->wires_[remap_name(wire->name)];
831 log_assert(w->attributes.count("\\init") == 0);
832 w->attributes["\\init"] = wire->attributes.at("\\init");
833 }
834 }
835
836 for (auto &it : cell_stats)
837 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
838 int in_wires = 0, out_wires = 0;
839 //for (auto &si : signal_list)
840 // if (si.is_port) {
841 // char buffer[100];
842 // snprintf(buffer, 100, "\\n%d", si.id);
843 // RTLIL::SigSig conn;
844 // if (si.type != G(NONE)) {
845 // conn.first = si.bit;
846 // conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
847 // out_wires++;
848 // } else {
849 // conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
850 // conn.second = si.bit;
851 // in_wires++;
852 // }
853 // module->connect(conn);
854 // }
855
856 // Go through all AND and NOT output connections,
857 // and for those output ports driving wires
858 // also driven by mapped_mod, disconnect them
859 for (auto cell : module->cells()) {
860 if (!cell->type.in("$_AND_", "$_NOT_"))
861 continue;
862 for (auto &it : cell->connections_) {
863 auto port_name = it.first;
864 if (!cell->output(port_name)) continue;
865 auto &signal = it.second;
866 auto bits = signal.bits();
867 for (auto &b : bits)
868 if (output_bits.count(b))
869 b = module->addWire(NEW_ID);
870 signal = std::move(bits);
871 }
872 }
873 // Do the same for module connections
874 for (auto &it : module->connections_) {
875 auto &signal = it.first;
876 auto bits = signal.bits();
877 for (auto &b : bits)
878 if (output_bits.count(b))
879 b = module->addWire(NEW_ID);
880 signal = std::move(bits);
881 }
882
883 // Stitch in mapped_mod's inputs/outputs into module
884 for (auto &it : mapped_mod->wires_) {
885 RTLIL::Wire *w = it.second;
886 if (!w->port_input && !w->port_output)
887 continue;
888 RTLIL::Wire *wire = module->wire(w->name);
889 RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
890 RTLIL::SigSpec signal;
891 if (wire) {
892 signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
893 }
894 else {
895 auto r = wideports_split(w->name.str());
896 wire = module->wire(r.first);
897 log_assert(wire);
898 int i = r.second;
899 signal = RTLIL::SigSpec(wire, i);
900 }
901 log_assert(GetSize(signal) >= GetSize(remap_wire));
902
903 if (w->port_input) {
904 RTLIL::SigSig conn;
905 conn.first = remap_wire;
906 conn.second = signal;
907 in_wires++;
908 module->connect(conn);
909 }
910 else if (w->port_output) {
911 RTLIL::SigSig conn;
912 conn.first = signal;
913 conn.second = remap_wire;
914 out_wires++;
915 module->connect(conn);
916 }
917 else log_abort();
918 }
919
920 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
921 log("ABC RESULTS: input signals: %8d\n", in_wires);
922 log("ABC RESULTS: output signals: %8d\n", out_wires);
923
924 delete mapped_design;
925 }
926 //else
927 //{
928 // log("Don't call ABC as there is nothing to map.\n");
929 //}
930
931 Pass::call(design, "clean");
932
933 cleanup:
934 if (cleanup)
935 {
936 log("Removing temp directory.\n");
937 remove_directory(tempdir_name);
938 }
939
940 log_pop();
941 }
942
943 struct Abc9Pass : public Pass {
944 Abc9Pass() : Pass("abc9", "use ABC for technology mapping") { }
945 void help() YS_OVERRIDE
946 {
947 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
948 log("\n");
949 log(" abc9 [options] [selection]\n");
950 log("\n");
951 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
952 log("library to a target architecture.\n");
953 log("\n");
954 log(" -exe <command>\n");
955 #ifdef ABCEXTERNAL
956 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
957 #else
958 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
959 #endif
960 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
961 log("\n");
962 log(" -script <file>\n");
963 log(" use the specified ABC script file instead of the default script.\n");
964 log("\n");
965 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
966 log(" string is interpreted as the command string to be passed to ABC. The\n");
967 log(" leading plus sign is removed and all commas (,) in the string are\n");
968 log(" replaced with blanks before the string is passed to ABC.\n");
969 log("\n");
970 log(" if no -script parameter is given, the following scripts are used:\n");
971 log("\n");
972 log(" for -liberty without -constr:\n");
973 log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
974 log("\n");
975 log(" for -liberty with -constr:\n");
976 log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
977 log("\n");
978 log(" for -lut/-luts (only one LUT size):\n");
979 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
980 log("\n");
981 log(" for -lut/-luts (different LUT sizes):\n");
982 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
983 log("\n");
984 log(" for -sop:\n");
985 log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
986 log("\n");
987 log(" otherwise:\n");
988 log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
989 log("\n");
990 log(" -fast\n");
991 log(" use different default scripts that are slightly faster (at the cost\n");
992 log(" of output quality):\n");
993 log("\n");
994 log(" for -liberty without -constr:\n");
995 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
996 log("\n");
997 log(" for -liberty with -constr:\n");
998 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
999 log("\n");
1000 log(" for -lut/-luts:\n");
1001 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
1002 log("\n");
1003 log(" for -sop:\n");
1004 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
1005 log("\n");
1006 log(" otherwise:\n");
1007 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
1008 log("\n");
1009 log(" -liberty <file>\n");
1010 log(" generate netlists for the specified cell library (using the liberty\n");
1011 log(" file format).\n");
1012 log("\n");
1013 log(" -constr <file>\n");
1014 log(" pass this file with timing constraints to ABC. use with -liberty.\n");
1015 log("\n");
1016 log(" a constr file contains two lines:\n");
1017 log(" set_driving_cell <cell_name>\n");
1018 log(" set_load <floating_point_number>\n");
1019 log("\n");
1020 log(" the set_driving_cell statement defines which cell type is assumed to\n");
1021 log(" drive the primary inputs and the set_load statement sets the load in\n");
1022 log(" femtofarads for each primary output.\n");
1023 log("\n");
1024 log(" -D <picoseconds>\n");
1025 log(" set delay target. the string {D} in the default scripts above is\n");
1026 log(" replaced by this option when used, and an empty string otherwise.\n");
1027 log(" this also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
1028 log(" default scripts above.\n");
1029 log("\n");
1030 log(" -I <num>\n");
1031 log(" maximum number of SOP inputs.\n");
1032 log(" (replaces {I} in the default scripts above)\n");
1033 log("\n");
1034 log(" -P <num>\n");
1035 log(" maximum number of SOP products.\n");
1036 log(" (replaces {P} in the default scripts above)\n");
1037 log("\n");
1038 log(" -S <num>\n");
1039 log(" maximum number of LUT inputs shared.\n");
1040 log(" (replaces {S} in the default scripts above, default: -S 1)\n");
1041 log("\n");
1042 log(" -lut <width>\n");
1043 log(" generate netlist using luts of (max) the specified width.\n");
1044 log("\n");
1045 log(" -lut <w1>:<w2>\n");
1046 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
1047 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
1048 log(" the area cost doubles with each additional input bit. the delay cost\n");
1049 log(" is still constant for all lut widths.\n");
1050 log("\n");
1051 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
1052 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
1053 log(" 2, 3, .. inputs.\n");
1054 log("\n");
1055 log(" -sop\n");
1056 log(" map to sum-of-product cells and inverters\n");
1057 log("\n");
1058 // log(" -mux4, -mux8, -mux16\n");
1059 // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
1060 // log(" (ignored when used with -liberty or -lut)\n");
1061 // log("\n");
1062 log(" -g type1,type2,...\n");
1063 log(" Map to the specified list of gate types. Supported gates types are:\n");
1064 log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.\n");
1065 log(" (The NOT gate is always added to this list automatically.)\n");
1066 log("\n");
1067 log(" The following aliases can be used to reference common sets of gate types:\n");
1068 log(" simple: AND OR XOR MUX\n");
1069 log(" cmos2: NAND NOR\n");
1070 log(" cmos3: NAND NOR AOI3 OAI3\n");
1071 log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
1072 log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
1073 log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
1074 log("\n");
1075 log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
1076 log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
1077 log("\n");
1078 log(" -dff\n");
1079 log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
1080 log(" clock domains are automatically partitioned in clock domains and each\n");
1081 log(" domain is passed through ABC independently.\n");
1082 log("\n");
1083 log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
1084 log(" use only the specified clock domain. this is like -dff, but only FF\n");
1085 log(" cells that belong to the specified clock domain are used.\n");
1086 log("\n");
1087 log(" -keepff\n");
1088 log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
1089 log(" them, for example for equivalence checking.)\n");
1090 log("\n");
1091 log(" -nocleanup\n");
1092 log(" when this option is used, the temporary files created by this pass\n");
1093 log(" are not removed. this is useful for debugging.\n");
1094 log("\n");
1095 log(" -showtmp\n");
1096 log(" print the temp dir name in log. usually this is suppressed so that the\n");
1097 log(" command output is identical across runs.\n");
1098 log("\n");
1099 log(" -markgroups\n");
1100 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
1101 log(" this attribute is a unique integer for each ABC process started. This\n");
1102 log(" is useful for debugging the partitioning of clock domains.\n");
1103 log("\n");
1104 log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
1105 log("loaded into ABC before the ABC script is executed.\n");
1106 log("\n");
1107 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
1108 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
1109 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
1110 log("output when passing an ABC script that writes a file. Instead write your full\n");
1111 log("design as BLIF file with write_blif and the load that into ABC externally if\n");
1112 log("you want to use ABC to convert your design into another format.\n");
1113 log("\n");
1114 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
1115 log("\n");
1116 }
1117 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1118 {
1119 log_header(design, "Executing ABC9 pass (technology mapping using ABC).\n");
1120 log_push();
1121
1122 assign_map.clear();
1123 signal_map.clear();
1124 signal_init.clear();
1125 pi_map.clear();
1126 po_map.clear();
1127
1128 #ifdef ABCEXTERNAL
1129 std::string exe_file = ABCEXTERNAL;
1130 #else
1131 std::string exe_file = proc_self_dirname() + "yosys-abc";
1132 #endif
1133 std::string script_file, liberty_file, constr_file, clk_str;
1134 std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
1135 bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
1136 bool show_tempdir = false, sop_mode = false;
1137 vector<int> lut_costs;
1138 markgroups = false;
1139
1140 map_mux4 = false;
1141 map_mux8 = false;
1142 map_mux16 = false;
1143 enabled_gates.clear();
1144
1145 #ifdef _WIN32
1146 #ifndef ABCEXTERNAL
1147 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
1148 exe_file = proc_self_dirname() + "..\\yosys-abc";
1149 #endif
1150 #endif
1151
1152 size_t argidx;
1153 char pwd [PATH_MAX];
1154 if (!getcwd(pwd, sizeof(pwd))) {
1155 log_cmd_error("getcwd failed: %s\n", strerror(errno));
1156 log_abort();
1157 }
1158 for (argidx = 1; argidx < args.size(); argidx++) {
1159 std::string arg = args[argidx];
1160 if (arg == "-exe" && argidx+1 < args.size()) {
1161 exe_file = args[++argidx];
1162 continue;
1163 }
1164 if (arg == "-script" && argidx+1 < args.size()) {
1165 script_file = args[++argidx];
1166 rewrite_filename(script_file);
1167 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
1168 script_file = std::string(pwd) + "/" + script_file;
1169 continue;
1170 }
1171 if (arg == "-liberty" && argidx+1 < args.size()) {
1172 liberty_file = args[++argidx];
1173 rewrite_filename(liberty_file);
1174 if (!liberty_file.empty() && !is_absolute_path(liberty_file))
1175 liberty_file = std::string(pwd) + "/" + liberty_file;
1176 continue;
1177 }
1178 if (arg == "-constr" && argidx+1 < args.size()) {
1179 rewrite_filename(constr_file);
1180 constr_file = args[++argidx];
1181 if (!constr_file.empty() && !is_absolute_path(constr_file))
1182 constr_file = std::string(pwd) + "/" + constr_file;
1183 continue;
1184 }
1185 if (arg == "-D" && argidx+1 < args.size()) {
1186 delay_target = "-D " + args[++argidx];
1187 continue;
1188 }
1189 if (arg == "-I" && argidx+1 < args.size()) {
1190 sop_inputs = "-I " + args[++argidx];
1191 continue;
1192 }
1193 if (arg == "-P" && argidx+1 < args.size()) {
1194 sop_products = "-P " + args[++argidx];
1195 continue;
1196 }
1197 if (arg == "-S" && argidx+1 < args.size()) {
1198 lutin_shared = "-S " + args[++argidx];
1199 continue;
1200 }
1201 if (arg == "-lut" && argidx+1 < args.size()) {
1202 string arg = args[++argidx];
1203 size_t pos = arg.find_first_of(':');
1204 int lut_mode = 0, lut_mode2 = 0;
1205 if (pos != string::npos) {
1206 lut_mode = atoi(arg.substr(0, pos).c_str());
1207 lut_mode2 = atoi(arg.substr(pos+1).c_str());
1208 } else {
1209 lut_mode = atoi(arg.c_str());
1210 lut_mode2 = lut_mode;
1211 }
1212 lut_costs.clear();
1213 for (int i = 0; i < lut_mode; i++)
1214 lut_costs.push_back(1);
1215 for (int i = lut_mode; i < lut_mode2; i++)
1216 lut_costs.push_back(2 << (i - lut_mode));
1217 continue;
1218 }
1219 if (arg == "-luts" && argidx+1 < args.size()) {
1220 lut_costs.clear();
1221 for (auto &tok : split_tokens(args[++argidx], ",")) {
1222 auto parts = split_tokens(tok, ":");
1223 if (GetSize(parts) == 0 && !lut_costs.empty())
1224 lut_costs.push_back(lut_costs.back());
1225 else if (GetSize(parts) == 1)
1226 lut_costs.push_back(atoi(parts.at(0).c_str()));
1227 else if (GetSize(parts) == 2)
1228 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
1229 lut_costs.push_back(atoi(parts.at(1).c_str()));
1230 else
1231 log_cmd_error("Invalid -luts syntax.\n");
1232 }
1233 continue;
1234 }
1235 if (arg == "-sop") {
1236 sop_mode = true;
1237 continue;
1238 }
1239 if (arg == "-mux4") {
1240 map_mux4 = true;
1241 continue;
1242 }
1243 if (arg == "-mux8") {
1244 map_mux8 = true;
1245 continue;
1246 }
1247 if (arg == "-mux16") {
1248 map_mux16 = true;
1249 continue;
1250 }
1251 if (arg == "-g" && argidx+1 < args.size()) {
1252 for (auto g : split_tokens(args[++argidx], ",")) {
1253 vector<string> gate_list;
1254 bool remove_gates = false;
1255 if (GetSize(g) > 0 && g[0] == '-') {
1256 remove_gates = true;
1257 g = g.substr(1);
1258 }
1259 if (g == "AND") goto ok_gate;
1260 if (g == "NAND") goto ok_gate;
1261 if (g == "OR") goto ok_gate;
1262 if (g == "NOR") goto ok_gate;
1263 if (g == "XOR") goto ok_gate;
1264 if (g == "XNOR") goto ok_gate;
1265 if (g == "ANDNOT") goto ok_gate;
1266 if (g == "ORNOT") goto ok_gate;
1267 if (g == "MUX") goto ok_gate;
1268 if (g == "AOI3") goto ok_gate;
1269 if (g == "OAI3") goto ok_gate;
1270 if (g == "AOI4") goto ok_gate;
1271 if (g == "OAI4") goto ok_gate;
1272 if (g == "simple") {
1273 gate_list.push_back("AND");
1274 gate_list.push_back("OR");
1275 gate_list.push_back("XOR");
1276 gate_list.push_back("MUX");
1277 goto ok_alias;
1278 }
1279 if (g == "cmos2") {
1280 gate_list.push_back("NAND");
1281 gate_list.push_back("NOR");
1282 goto ok_alias;
1283 }
1284 if (g == "cmos3") {
1285 gate_list.push_back("NAND");
1286 gate_list.push_back("NOR");
1287 gate_list.push_back("AOI3");
1288 gate_list.push_back("OAI3");
1289 goto ok_alias;
1290 }
1291 if (g == "cmos4") {
1292 gate_list.push_back("NAND");
1293 gate_list.push_back("NOR");
1294 gate_list.push_back("AOI3");
1295 gate_list.push_back("OAI3");
1296 gate_list.push_back("AOI4");
1297 gate_list.push_back("OAI4");
1298 goto ok_alias;
1299 }
1300 if (g == "gates") {
1301 gate_list.push_back("AND");
1302 gate_list.push_back("NAND");
1303 gate_list.push_back("OR");
1304 gate_list.push_back("NOR");
1305 gate_list.push_back("XOR");
1306 gate_list.push_back("XNOR");
1307 gate_list.push_back("ANDNOT");
1308 gate_list.push_back("ORNOT");
1309 goto ok_alias;
1310 }
1311 if (g == "aig") {
1312 gate_list.push_back("AND");
1313 gate_list.push_back("NAND");
1314 gate_list.push_back("OR");
1315 gate_list.push_back("NOR");
1316 gate_list.push_back("ANDNOT");
1317 gate_list.push_back("ORNOT");
1318 goto ok_alias;
1319 }
1320 cmd_error(args, argidx, stringf("Unsupported gate type: %s", g.c_str()));
1321 ok_gate:
1322 gate_list.push_back(g);
1323 ok_alias:
1324 for (auto gate : gate_list) {
1325 if (remove_gates)
1326 enabled_gates.erase(gate);
1327 else
1328 enabled_gates.insert(gate);
1329 }
1330 }
1331 continue;
1332 }
1333 if (arg == "-fast") {
1334 fast_mode = true;
1335 continue;
1336 }
1337 if (arg == "-dff") {
1338 dff_mode = true;
1339 continue;
1340 }
1341 if (arg == "-clk" && argidx+1 < args.size()) {
1342 clk_str = args[++argidx];
1343 dff_mode = true;
1344 continue;
1345 }
1346 if (arg == "-keepff") {
1347 keepff = true;
1348 continue;
1349 }
1350 if (arg == "-nocleanup") {
1351 cleanup = false;
1352 continue;
1353 }
1354 if (arg == "-showtmp") {
1355 show_tempdir = true;
1356 continue;
1357 }
1358 if (arg == "-markgroups") {
1359 markgroups = true;
1360 continue;
1361 }
1362 break;
1363 }
1364 extra_args(args, argidx, design);
1365
1366 if (!lut_costs.empty() && !liberty_file.empty())
1367 log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
1368 if (!constr_file.empty() && liberty_file.empty())
1369 log_cmd_error("Got -constr but no -liberty!\n");
1370
1371 for (auto mod : design->selected_modules())
1372 {
1373 if (mod->processes.size() > 0) {
1374 log("Skipping module %s as it contains processes.\n", log_id(mod));
1375 continue;
1376 }
1377
1378 assign_map.set(mod);
1379 signal_init.clear();
1380
1381 for (Wire *wire : mod->wires())
1382 if (wire->attributes.count("\\init")) {
1383 SigSpec initsig = assign_map(wire);
1384 Const initval = wire->attributes.at("\\init");
1385 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
1386 switch (initval[i]) {
1387 case State::S0:
1388 signal_init[initsig[i]] = State::S0;
1389 break;
1390 case State::S1:
1391 signal_init[initsig[i]] = State::S0;
1392 break;
1393 default:
1394 break;
1395 }
1396 }
1397
1398 if (!dff_mode || !clk_str.empty()) {
1399 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
1400 delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
1401 continue;
1402 }
1403
1404 CellTypes ct(design);
1405
1406 std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
1407 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1408
1409 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1410 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1411 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1412
1413 typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
1414 std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
1415 std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
1416
1417 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1418 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1419
1420 for (auto cell : all_cells)
1421 {
1422 clkdomain_t key;
1423
1424 for (auto &conn : cell->connections())
1425 for (auto bit : conn.second) {
1426 bit = assign_map(bit);
1427 if (bit.wire != nullptr) {
1428 cell_to_bit[cell].insert(bit);
1429 bit_to_cell[bit].insert(cell);
1430 if (ct.cell_input(cell->type, conn.first)) {
1431 cell_to_bit_up[cell].insert(bit);
1432 bit_to_cell_down[bit].insert(cell);
1433 }
1434 if (ct.cell_output(cell->type, conn.first)) {
1435 cell_to_bit_down[cell].insert(bit);
1436 bit_to_cell_up[bit].insert(cell);
1437 }
1438 }
1439 }
1440
1441 if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
1442 {
1443 key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
1444 }
1445 else
1446 if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
1447 {
1448 bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
1449 bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
1450 key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
1451 }
1452 else
1453 continue;
1454
1455 unassigned_cells.erase(cell);
1456 expand_queue.insert(cell);
1457 expand_queue_up.insert(cell);
1458 expand_queue_down.insert(cell);
1459
1460 assigned_cells[key].push_back(cell);
1461 assigned_cells_reverse[cell] = key;
1462 }
1463
1464 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1465 {
1466 if (!expand_queue_up.empty())
1467 {
1468 RTLIL::Cell *cell = *expand_queue_up.begin();
1469 clkdomain_t key = assigned_cells_reverse.at(cell);
1470 expand_queue_up.erase(cell);
1471
1472 for (auto bit : cell_to_bit_up[cell])
1473 for (auto c : bit_to_cell_up[bit])
1474 if (unassigned_cells.count(c)) {
1475 unassigned_cells.erase(c);
1476 next_expand_queue_up.insert(c);
1477 assigned_cells[key].push_back(c);
1478 assigned_cells_reverse[c] = key;
1479 expand_queue.insert(c);
1480 }
1481 }
1482
1483 if (!expand_queue_down.empty())
1484 {
1485 RTLIL::Cell *cell = *expand_queue_down.begin();
1486 clkdomain_t key = assigned_cells_reverse.at(cell);
1487 expand_queue_down.erase(cell);
1488
1489 for (auto bit : cell_to_bit_down[cell])
1490 for (auto c : bit_to_cell_down[bit])
1491 if (unassigned_cells.count(c)) {
1492 unassigned_cells.erase(c);
1493 next_expand_queue_up.insert(c);
1494 assigned_cells[key].push_back(c);
1495 assigned_cells_reverse[c] = key;
1496 expand_queue.insert(c);
1497 }
1498 }
1499
1500 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1501 expand_queue_up.swap(next_expand_queue_up);
1502 expand_queue_down.swap(next_expand_queue_down);
1503 }
1504 }
1505
1506 while (!expand_queue.empty())
1507 {
1508 RTLIL::Cell *cell = *expand_queue.begin();
1509 clkdomain_t key = assigned_cells_reverse.at(cell);
1510 expand_queue.erase(cell);
1511
1512 for (auto bit : cell_to_bit.at(cell)) {
1513 for (auto c : bit_to_cell[bit])
1514 if (unassigned_cells.count(c)) {
1515 unassigned_cells.erase(c);
1516 next_expand_queue.insert(c);
1517 assigned_cells[key].push_back(c);
1518 assigned_cells_reverse[c] = key;
1519 }
1520 bit_to_cell[bit].clear();
1521 }
1522
1523 if (expand_queue.empty())
1524 expand_queue.swap(next_expand_queue);
1525 }
1526
1527 clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1528 for (auto cell : unassigned_cells) {
1529 assigned_cells[key].push_back(cell);
1530 assigned_cells_reverse[cell] = key;
1531 }
1532
1533 log_header(design, "Summary of detected clock domains:\n");
1534 for (auto &it : assigned_cells)
1535 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
1536 std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
1537 std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
1538
1539 for (auto &it : assigned_cells) {
1540 clk_polarity = std::get<0>(it.first);
1541 clk_sig = assign_map(std::get<1>(it.first));
1542 en_polarity = std::get<2>(it.first);
1543 en_sig = assign_map(std::get<3>(it.first));
1544 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
1545 keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
1546 assign_map.set(mod);
1547 }
1548 }
1549
1550 assign_map.clear();
1551 signal_map.clear();
1552 signal_init.clear();
1553 pi_map.clear();
1554 po_map.clear();
1555
1556 log_pop();
1557 }
1558 } Abc9Pass;
1559
1560 PRIVATE_NAMESPACE_END