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Merge remote-tracking branch 'origin/master' into xaig
[yosys.git] / passes / techmap / abc9.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 * Copyright (C) 2019 Eddie Hung <eddie@fpgeh.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 */
20
21 // [[CITE]] ABC
22 // Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification
23 // http://www.eecs.berkeley.edu/~alanmi/abc/
24
25 #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
26 #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
27 //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
28 //#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps"
29 #define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &ps -l -m"
30 #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
31 #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
32
33 #define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
34 #define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
35 #define ABC_FAST_COMMAND_LUT "&st; &retime; &if"
36 #define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
37 #define ABC_FAST_COMMAND_DFL "strash; dretime; map"
38
39 #include "kernel/register.h"
40 #include "kernel/sigtools.h"
41 #include "kernel/celltypes.h"
42 #include "kernel/cost.h"
43 #include "kernel/log.h"
44 #include <stdlib.h>
45 #include <stdio.h>
46 #include <string.h>
47 #include <cerrno>
48 #include <sstream>
49 #include <climits>
50
51 #ifndef _WIN32
52 # include <unistd.h>
53 # include <dirent.h>
54 #endif
55
56 #include "frontends/aiger/aigerparse.h"
57
58 #ifdef YOSYS_LINK_ABC
59 extern "C" int Abc_RealMain(int argc, char *argv[]);
60 #endif
61
62 USING_YOSYS_NAMESPACE
63 PRIVATE_NAMESPACE_BEGIN
64
65 bool map_mux4;
66 bool map_mux8;
67 bool map_mux16;
68
69 bool markgroups;
70 int map_autoidx;
71 SigMap assign_map;
72 RTLIL::Module *module;
73 std::map<RTLIL::SigBit, int> signal_map;
74 std::map<RTLIL::SigBit, RTLIL::State> signal_init;
75 pool<std::string> enabled_gates;
76 bool recover_init;
77
78 bool clk_polarity, en_polarity;
79 RTLIL::SigSpec clk_sig, en_sig;
80 dict<int, std::string> pi_map, po_map;
81
82 std::string remap_name(RTLIL::IdString abc_name)
83 {
84 std::stringstream sstr;
85 sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
86 return sstr.str();
87 }
88
89 void handle_loops(RTLIL::Design *design)
90 {
91 Pass::call(design, "scc -set_attr abc_scc_id {}");
92
93 design->selection_stack.emplace_back(false);
94 RTLIL::Selection& sel = design->selection_stack.back();
95
96 // For every unique SCC found, (arbitrarily) find the first
97 // cell in the component, and select (and mark) all its output
98 // wires
99 pool<RTLIL::Const> ids_seen;
100 for (auto cell : module->cells()) {
101 auto it = cell->attributes.find("\\abc_scc_id");
102 if (it != cell->attributes.end()) {
103 auto r = ids_seen.insert(it->second);
104 if (r.second) {
105 for (const auto &c : cell->connections()) {
106 if (c.second.is_fully_const()) continue;
107 if (cell->output(c.first)) {
108 SigBit b = c.second.as_bit();
109 Wire *w = b.wire;
110 w->set_bool_attribute("\\abc_scc_break");
111 sel.select(module, w);
112 }
113 }
114 }
115 cell->attributes.erase(it);
116 }
117 }
118
119 // Then cut those selected wires to expose them as new PO/PI
120 Pass::call(design, "expose -cut -sep .abc");
121
122 design->selection_stack.pop_back();
123 }
124
125 std::string add_echos_to_abc_cmd(std::string str)
126 {
127 std::string new_str, token;
128 for (size_t i = 0; i < str.size(); i++) {
129 token += str[i];
130 if (str[i] == ';') {
131 while (i+1 < str.size() && str[i+1] == ' ')
132 i++;
133 new_str += "echo + " + token + " " + token + " ";
134 token.clear();
135 }
136 }
137
138 if (!token.empty()) {
139 if (!new_str.empty())
140 new_str += "echo + " + token + "; ";
141 new_str += token;
142 }
143
144 return new_str;
145 }
146
147 std::string fold_abc_cmd(std::string str)
148 {
149 std::string token, new_str = " ";
150 int char_counter = 10;
151
152 for (size_t i = 0; i <= str.size(); i++) {
153 if (i < str.size())
154 token += str[i];
155 if (i == str.size() || str[i] == ';') {
156 if (char_counter + token.size() > 75)
157 new_str += "\n ", char_counter = 14;
158 new_str += token, char_counter += token.size();
159 token.clear();
160 }
161 }
162
163 return new_str;
164 }
165
166 std::string replace_tempdir(std::string text, std::string tempdir_name, bool show_tempdir)
167 {
168 if (show_tempdir)
169 return text;
170
171 while (1) {
172 size_t pos = text.find(tempdir_name);
173 if (pos == std::string::npos)
174 break;
175 text = text.substr(0, pos) + "<abc-temp-dir>" + text.substr(pos + GetSize(tempdir_name));
176 }
177
178 std::string selfdir_name = proc_self_dirname();
179 if (selfdir_name != "/") {
180 while (1) {
181 size_t pos = text.find(selfdir_name);
182 if (pos == std::string::npos)
183 break;
184 text = text.substr(0, pos) + "<yosys-exe-dir>/" + text.substr(pos + GetSize(selfdir_name));
185 }
186 }
187
188 return text;
189 }
190
191 struct abc_output_filter
192 {
193 bool got_cr;
194 int escape_seq_state;
195 std::string linebuf;
196 std::string tempdir_name;
197 bool show_tempdir;
198
199 abc_output_filter(std::string tempdir_name, bool show_tempdir) : tempdir_name(tempdir_name), show_tempdir(show_tempdir)
200 {
201 got_cr = false;
202 escape_seq_state = 0;
203 }
204
205 void next_char(char ch)
206 {
207 if (escape_seq_state == 0 && ch == '\033') {
208 escape_seq_state = 1;
209 return;
210 }
211 if (escape_seq_state == 1) {
212 escape_seq_state = ch == '[' ? 2 : 0;
213 return;
214 }
215 if (escape_seq_state == 2) {
216 if ((ch < '0' || '9' < ch) && ch != ';')
217 escape_seq_state = 0;
218 return;
219 }
220 escape_seq_state = 0;
221 if (ch == '\r') {
222 got_cr = true;
223 return;
224 }
225 if (ch == '\n') {
226 log("ABC: %s\n", replace_tempdir(linebuf, tempdir_name, show_tempdir).c_str());
227 got_cr = false, linebuf.clear();
228 return;
229 }
230 if (got_cr)
231 got_cr = false, linebuf.clear();
232 linebuf += ch;
233 }
234
235 void next_line(const std::string &line)
236 {
237 int pi, po;
238 if (sscanf(line.c_str(), "Start-point = pi%d. End-point = po%d.", &pi, &po) == 2) {
239 log("ABC: Start-point = pi%d (%s). End-point = po%d (%s).\n",
240 pi, pi_map.count(pi) ? pi_map.at(pi).c_str() : "???",
241 po, po_map.count(po) ? po_map.at(po).c_str() : "???");
242 return;
243 }
244
245 for (char ch : line)
246 next_char(ch);
247 }
248 };
249
250 static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
251 {
252 int pos = -1;
253
254 if (name.empty() || name.back() != ']')
255 goto failed;
256
257 for (int i = 0; i+1 < GetSize(name); i++) {
258 if (name[i] == '[')
259 pos = i;
260 else if (name[i] < '0' || name[i] > '9')
261 pos = -1;
262 else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
263 pos = -1;
264 }
265
266 if (pos >= 0)
267 return std::pair<RTLIL::IdString, int>(RTLIL::escape_id(name.substr(0, pos)), atoi(name.c_str() + pos+1));
268
269 failed:
270 return std::pair<RTLIL::IdString, int>(name, 0);
271 }
272
273 void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
274 std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
275 bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
276 const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file)
277 {
278 module = current_module;
279 map_autoidx = autoidx++;
280
281 signal_map.clear();
282 pi_map.clear();
283 po_map.clear();
284 recover_init = false;
285
286 if (clk_str != "$")
287 {
288 clk_polarity = true;
289 clk_sig = RTLIL::SigSpec();
290
291 en_polarity = true;
292 en_sig = RTLIL::SigSpec();
293 }
294
295 if (!clk_str.empty() && clk_str != "$")
296 {
297 if (clk_str.find(',') != std::string::npos) {
298 int pos = clk_str.find(',');
299 std::string en_str = clk_str.substr(pos+1);
300 clk_str = clk_str.substr(0, pos);
301 if (en_str[0] == '!') {
302 en_polarity = false;
303 en_str = en_str.substr(1);
304 }
305 if (module->wires_.count(RTLIL::escape_id(en_str)) != 0)
306 en_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(en_str)), 0));
307 }
308 if (clk_str[0] == '!') {
309 clk_polarity = false;
310 clk_str = clk_str.substr(1);
311 }
312 if (module->wires_.count(RTLIL::escape_id(clk_str)) != 0)
313 clk_sig = assign_map(RTLIL::SigSpec(module->wires_.at(RTLIL::escape_id(clk_str)), 0));
314 }
315
316 if (dff_mode && clk_sig.empty())
317 log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
318
319 std::string tempdir_name = "/tmp/yosys-abc-XXXXXX";
320 if (!cleanup)
321 tempdir_name[0] = tempdir_name[4] = '_';
322 tempdir_name = make_temp_dir(tempdir_name);
323 log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n",
324 module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
325
326 std::string abc_script;
327
328 if (!liberty_file.empty()) {
329 abc_script += stringf("read_lib -w %s; ", liberty_file.c_str());
330 if (!constr_file.empty())
331 abc_script += stringf("read_constr -v %s; ", constr_file.c_str());
332 } else
333 if (!lut_costs.empty()) {
334 abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str());
335 if (!box_file.empty())
336 abc_script += stringf("read_box -v %s; ", box_file.c_str());
337 }
338 else
339 if (!lut_file.empty()) {
340 abc_script += stringf("read_lut %s; ", lut_file.c_str());
341 if (!box_file.empty())
342 abc_script += stringf("read_box -v %s; ", box_file.c_str());
343 }
344 else
345 abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str());
346
347 abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str());
348
349 if (!script_file.empty()) {
350 if (script_file[0] == '+') {
351 for (size_t i = 1; i < script_file.size(); i++)
352 if (script_file[i] == '\'')
353 abc_script += "'\\''";
354 else if (script_file[i] == ',')
355 abc_script += " ";
356 else
357 abc_script += script_file[i];
358 } else
359 abc_script += stringf("source %s", script_file.c_str());
360 } else if (!lut_costs.empty() || !lut_file.empty()) {
361 //bool all_luts_cost_same = true;
362 //for (int this_cost : lut_costs)
363 // if (this_cost != lut_costs.front())
364 // all_luts_cost_same = false;
365 abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
366 //if (all_luts_cost_same && !fast_mode)
367 // abc_script += "; lutpack {S}";
368 } else if (!liberty_file.empty())
369 abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
370 else if (sop_mode)
371 abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
372 else
373 abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
374
375 if (script_file.empty() && !delay_target.empty())
376 for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
377 abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
378
379 for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
380 abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
381
382 for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
383 abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
384
385 for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
386 abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
387
388 for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
389 abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
390
391 abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
392 abc_script = add_echos_to_abc_cmd(abc_script);
393
394 for (size_t i = 0; i+1 < abc_script.size(); i++)
395 if (abc_script[i] == ';' && abc_script[i+1] == ' ')
396 abc_script[i+1] = '\n';
397
398 FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
399 fprintf(f, "%s\n", abc_script.c_str());
400 fclose(f);
401
402 if (dff_mode || !clk_str.empty())
403 {
404 if (clk_sig.size() == 0)
405 log("No%s clock domain found. Not extracting any FF cells.\n", clk_str.empty() ? "" : " matching");
406 else {
407 log("Found%s %s clock domain: %s", clk_str.empty() ? "" : " matching", clk_polarity ? "posedge" : "negedge", log_signal(clk_sig));
408 if (en_sig.size() != 0)
409 log(", enabled by %s%s", en_polarity ? "" : "!", log_signal(en_sig));
410 log("\n");
411 }
412 }
413
414 design->selection_stack.emplace_back(false);
415 RTLIL::Selection& sel = design->selection_stack.back();
416 sel.select(module);
417
418 // Behave as for "abc" where BLIF writer implicitly outputs all undef as zero
419 Pass::call(design, "setundef -zero");
420
421 Pass::call(design, "aigmap");
422
423 handle_loops(design);
424
425 Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
426
427 design->selection_stack.pop_back();
428
429 // Now 'unexpose' those wires by undoing
430 // the expose operation -- remove them from PO/PI
431 // and re-connecting them back together
432 for (auto wire : module->wires()) {
433 auto it = wire->attributes.find("\\abc_scc_break");
434 if (it != wire->attributes.end()) {
435 wire->attributes.erase(it);
436 log_assert(wire->port_output);
437 wire->port_output = false;
438 RTLIL::Wire *i_wire = module->wire(wire->name.str() + ".abci");
439 log_assert(i_wire);
440 log_assert(i_wire->port_input);
441 i_wire->port_input = false;
442 module->connect(i_wire, wire);
443 }
444 }
445 module->fixup_ports();
446
447 //log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
448 // count_gates, GetSize(signal_list), count_input, count_output);
449
450 log_push();
451
452 //if (count_output > 0)
453 {
454 log_header(design, "Executing ABC9.\n");
455
456 std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
457 f = fopen(buffer.c_str(), "wt");
458 if (f == NULL)
459 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
460 fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
461 fprintf(f, "GATE ONE 1 Y=CONST1;\n");
462 fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
463 fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
464 if (enabled_gates.empty() || enabled_gates.count("AND"))
465 fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
466 if (enabled_gates.empty() || enabled_gates.count("NAND"))
467 fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
468 if (enabled_gates.empty() || enabled_gates.count("OR"))
469 fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
470 if (enabled_gates.empty() || enabled_gates.count("NOR"))
471 fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
472 if (enabled_gates.empty() || enabled_gates.count("XOR"))
473 fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
474 if (enabled_gates.empty() || enabled_gates.count("XNOR"))
475 fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
476 if (enabled_gates.empty() || enabled_gates.count("ANDNOT"))
477 fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_"));
478 if (enabled_gates.empty() || enabled_gates.count("ORNOT"))
479 fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_"));
480 if (enabled_gates.empty() || enabled_gates.count("AOI3"))
481 fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
482 if (enabled_gates.empty() || enabled_gates.count("OAI3"))
483 fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
484 if (enabled_gates.empty() || enabled_gates.count("AOI4"))
485 fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
486 if (enabled_gates.empty() || enabled_gates.count("OAI4"))
487 fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
488 if (enabled_gates.empty() || enabled_gates.count("MUX"))
489 fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
490 if (map_mux4)
491 fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_"));
492 if (map_mux8)
493 fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_"));
494 if (map_mux16)
495 fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_"));
496 fclose(f);
497
498 if (!lut_costs.empty()) {
499 buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
500 f = fopen(buffer.c_str(), "wt");
501 if (f == NULL)
502 log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno));
503 for (int i = 0; i < GetSize(lut_costs); i++)
504 fprintf(f, "%d %d.00 1.00\n", i+1, lut_costs.at(i));
505 fclose(f);
506 }
507
508 buffer = stringf("%s -s -f %s/abc.script 2>&1", exe_file.c_str(), tempdir_name.c_str());
509 log("Running ABC command: %s\n", replace_tempdir(buffer, tempdir_name, show_tempdir).c_str());
510
511 #ifndef YOSYS_LINK_ABC
512 abc_output_filter filt(tempdir_name, show_tempdir);
513 int ret = run_command(buffer, std::bind(&abc_output_filter::next_line, filt, std::placeholders::_1));
514 #else
515 // These needs to be mutable, supposedly due to getopt
516 char *abc_argv[5];
517 string tmp_script_name = stringf("%s/abc.script", tempdir_name.c_str());
518 abc_argv[0] = strdup(exe_file.c_str());
519 abc_argv[1] = strdup("-s");
520 abc_argv[2] = strdup("-f");
521 abc_argv[3] = strdup(tmp_script_name.c_str());
522 abc_argv[4] = 0;
523 int ret = Abc_RealMain(4, abc_argv);
524 free(abc_argv[0]);
525 free(abc_argv[1]);
526 free(abc_argv[2]);
527 free(abc_argv[3]);
528 #endif
529 if (ret != 0)
530 log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
531
532 buffer = stringf("%s/%s", tempdir_name.c_str(), "output.aig");
533 std::ifstream ifs;
534 ifs.open(buffer);
535 if (ifs.fail())
536 log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
537
538 bool builtin_lib = liberty_file.empty();
539 RTLIL::Design *mapped_design = new RTLIL::Design;
540 //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
541 buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
542 AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
543 reader.parse_xaiger();
544
545 ifs.close();
546
547 log_header(design, "Re-integrating ABC9 results.\n");
548 RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
549 if (mapped_mod == NULL)
550 log_error("ABC output file does not contain a module `netlist'.\n");
551
552 pool<RTLIL::SigBit> output_bits;
553 for (auto &it : mapped_mod->wires_) {
554 RTLIL::Wire *w = it.second;
555 RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w));
556 if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx;
557 if (w->port_output) {
558 RTLIL::Wire *wire = module->wire(w->name);
559 if (wire) {
560 for (int i = 0; i < GetSize(wire); i++)
561 output_bits.insert({wire, i});
562 }
563 else {
564 //if (w->name == "\\__dummy_o__") {
565 // log("Don't call ABC as there is nothing to map.\n");
566 // goto cleanup;
567 //}
568
569 // Attempt another wideports_split here because there
570 // exists the possibility that different bits of a port
571 // could be an input and output, therefore parse_xiager()
572 // could not combine it into a wideport
573 auto r = wideports_split(w->name.str());
574 wire = module->wire(r.first);
575 log_assert(wire);
576 int i = r.second;
577 output_bits.insert({wire, i});
578 }
579 }
580 }
581
582 std::map<std::string, int> cell_stats;
583 for (auto c : mapped_mod->cells())
584 {
585 if (builtin_lib)
586 {
587 if (c->type == "$_NOT_") {
588 RTLIL::Cell *cell;
589 RTLIL::SigBit a_bit = c->getPort("\\A").as_bit();
590 RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit();
591 if (!lut_costs.empty() || !lut_file.empty()) {
592 // ABC can return NOT gates that drive POs
593 if (a_bit.wire->port_input) {
594 // If it's a NOT gate that comes from a primary input directly
595 // then implement it using a LUT
596 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
597 RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset),
598 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
599 1);
600 }
601 else {
602 // Otherwise, clone the driving LUT to guarantee that we
603 // won't increase the max logic depth
604 // (TODO: Optimise by not cloning unless will increase depth)
605 RTLIL::IdString driver_name;
606 if (GetSize(a_bit.wire) == 1)
607 driver_name = stringf("%s$lut", a_bit.wire->name.c_str());
608 else
609 driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset);
610 RTLIL::Cell* driver = mapped_mod->cell(driver_name);
611 log_assert(driver);
612 auto driver_a = driver->getPort("\\A").chunks();
613 for (auto &chunk : driver_a)
614 chunk.wire = module->wires_[remap_name(chunk.wire->name)];
615 RTLIL::Const driver_lut = driver->getParam("\\LUT");
616 for (auto &b : driver_lut.bits) {
617 if (b == RTLIL::State::S0) b = RTLIL::State::S1;
618 else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
619 }
620 cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())),
621 driver_a,
622 RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
623 driver_lut);
624 }
625 cell_stats["$lut"]++;
626 }
627 else {
628 cell = module->addCell(remap_name(c->name), "$_NOT_");
629 cell->setPort("\\A", RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset));
630 cell->setPort("\\Y", RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset));
631 cell_stats[RTLIL::unescape_id(c->type)]++;
632 }
633 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
634 continue;
635 }
636
637 cell_stats[RTLIL::unescape_id(c->type)]++;
638 if (c->type == "\\ZERO" || c->type == "\\ONE") {
639 RTLIL::SigSig conn;
640 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
641 conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1);
642 module->connect(conn);
643 continue;
644 }
645 if (c->type == "\\BUF") {
646 RTLIL::SigSig conn;
647 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]);
648 conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]);
649 module->connect(conn);
650 continue;
651 }
652
653 if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" ||
654 c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") {
655 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
656 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
657 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
658 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
659 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
660 continue;
661 }
662 if (c->type == "\\MUX") {
663 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_");
664 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
665 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
666 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
667 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
668 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
669 continue;
670 }
671 if (c->type == "\\MUX4") {
672 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_");
673 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
674 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
675 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
676 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
677 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
678 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
679 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
680 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
681 continue;
682 }
683 if (c->type == "\\MUX8") {
684 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_");
685 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
686 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
687 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
688 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
689 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
690 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
691 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
692 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
693 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
694 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
695 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
696 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
697 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
698 continue;
699 }
700 if (c->type == "\\MUX16") {
701 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_");
702 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
703 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
704 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
705 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
706 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
707 cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)]));
708 cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)]));
709 cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)]));
710 cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)]));
711 cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)]));
712 cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)]));
713 cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)]));
714 cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)]));
715 cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)]));
716 cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)]));
717 cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)]));
718 cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)]));
719 cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)]));
720 cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)]));
721 cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)]));
722 cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)]));
723 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
724 continue;
725 }
726 if (c->type == "\\AOI3" || c->type == "\\OAI3") {
727 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
728 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
729 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
730 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
731 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
732 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
733 continue;
734 }
735 if (c->type == "\\AOI4" || c->type == "\\OAI4") {
736 RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_");
737 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
738 cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]));
739 cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)]));
740 cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)]));
741 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
742 cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]));
743 continue;
744 }
745 if (c->type == "\\DFF") {
746 log_assert(clk_sig.size() == 1);
747 RTLIL::Cell *cell;
748 if (en_sig.size() == 0) {
749 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
750 } else {
751 log_assert(en_sig.size() == 1);
752 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
753 cell->setPort("\\E", en_sig);
754 }
755 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
756 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
757 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
758 cell->setPort("\\C", clk_sig);
759 continue;
760 }
761 }
762 else
763 cell_stats[RTLIL::unescape_id(c->type)]++;
764
765 if (c->type == "\\_const0_" || c->type == "\\_const1_") {
766 RTLIL::SigSig conn;
767 conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
768 conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
769 module->connect(conn);
770 continue;
771 }
772
773 if (c->type == "\\_dff_") {
774 log_assert(clk_sig.size() == 1);
775 RTLIL::Cell *cell;
776 if (en_sig.size() == 0) {
777 cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
778 } else {
779 log_assert(en_sig.size() == 1);
780 cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
781 cell->setPort("\\E", en_sig);
782 }
783 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
784 cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
785 cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
786 cell->setPort("\\C", clk_sig);
787 continue;
788 }
789
790 if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
791 SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
792 SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
793 module->connect(my_y, my_a);
794 continue;
795 }
796
797 RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
798 if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
799 cell->parameters = c->parameters;
800 for (auto &conn : c->connections()) {
801 RTLIL::SigSpec newsig;
802 for (auto c : conn.second.chunks()) {
803 if (c.width == 0)
804 continue;
805 //log_assert(c.width == 1);
806 c.wire = module->wires_[remap_name(c.wire->name)];
807 newsig.append(c);
808 }
809 cell->setPort(conn.first, newsig);
810 }
811 }
812
813 // Copy connections (and rename) from mapped_mod to module
814 for (auto conn : mapped_mod->connections()) {
815 if (!conn.first.is_fully_const()) {
816 auto chunks = conn.first.chunks();
817 for (auto &c : chunks)
818 c.wire = module->wires_[remap_name(c.wire->name)];
819 conn.first = std::move(chunks);
820 }
821 if (!conn.second.is_fully_const()) {
822 auto chunks = conn.second.chunks();
823 for (auto &c : chunks)
824 if (c.wire)
825 c.wire = module->wires_[remap_name(c.wire->name)];
826 conn.second = std::move(chunks);
827 }
828 module->connect(conn);
829 }
830
831 if (recover_init)
832 for (auto wire : mapped_mod->wires()) {
833 if (wire->attributes.count("\\init")) {
834 Wire *w = module->wires_[remap_name(wire->name)];
835 log_assert(w->attributes.count("\\init") == 0);
836 w->attributes["\\init"] = wire->attributes.at("\\init");
837 }
838 }
839
840 for (auto &it : cell_stats)
841 log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
842 int in_wires = 0, out_wires = 0;
843 //for (auto &si : signal_list)
844 // if (si.is_port) {
845 // char buffer[100];
846 // snprintf(buffer, 100, "\\n%d", si.id);
847 // RTLIL::SigSig conn;
848 // if (si.type != G(NONE)) {
849 // conn.first = si.bit;
850 // conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
851 // out_wires++;
852 // } else {
853 // conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]);
854 // conn.second = si.bit;
855 // in_wires++;
856 // }
857 // module->connect(conn);
858 // }
859
860 // Go through all AND and NOT output connections,
861 // and for those output ports driving wires
862 // also driven by mapped_mod, disconnect them
863 for (auto cell : module->cells()) {
864 if (!cell->type.in("$_AND_", "$_NOT_"))
865 continue;
866 for (auto &it : cell->connections_) {
867 auto port_name = it.first;
868 if (!cell->output(port_name)) continue;
869 auto &signal = it.second;
870 auto bits = signal.bits();
871 for (auto &b : bits)
872 if (output_bits.count(b))
873 b = module->addWire(NEW_ID);
874 signal = std::move(bits);
875 }
876 }
877 // Do the same for module connections
878 for (auto &it : module->connections_) {
879 auto &signal = it.first;
880 auto bits = signal.bits();
881 for (auto &b : bits)
882 if (output_bits.count(b))
883 b = module->addWire(NEW_ID);
884 signal = std::move(bits);
885 }
886
887 // Stitch in mapped_mod's inputs/outputs into module
888 for (auto &it : mapped_mod->wires_) {
889 RTLIL::Wire *w = it.second;
890 if (!w->port_input && !w->port_output)
891 continue;
892 RTLIL::Wire *wire = module->wire(w->name);
893 RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
894 RTLIL::SigSpec signal;
895 if (wire) {
896 signal = RTLIL::SigSpec(wire, 0, GetSize(remap_wire));
897 }
898 else {
899 // Attempt another wideports_split here because there
900 // exists the possibility that different bits of a port
901 // could be an input and output, therefore parse_xiager()
902 // could not combine it into a wideport
903 auto r = wideports_split(w->name.str());
904 wire = module->wire(r.first);
905 log_assert(wire);
906 int i = r.second;
907 signal = RTLIL::SigSpec(wire, i);
908 }
909 log_assert(GetSize(signal) >= GetSize(remap_wire));
910
911 log_assert(w->port_input || w->port_output);
912 RTLIL::SigSig conn;
913 if (w->port_input) {
914 conn.first = remap_wire;
915 conn.second = signal;
916 in_wires++;
917 module->connect(conn);
918 }
919 if (w->port_output) {
920 conn.first = signal;
921 conn.second = remap_wire;
922 out_wires++;
923 module->connect(conn);
924 }
925 }
926
927 //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires);
928 log("ABC RESULTS: input signals: %8d\n", in_wires);
929 log("ABC RESULTS: output signals: %8d\n", out_wires);
930
931 delete mapped_design;
932 }
933 //else
934 //{
935 // log("Don't call ABC as there is nothing to map.\n");
936 //}
937
938 cleanup:
939 if (cleanup)
940 {
941 log("Removing temp directory.\n");
942 remove_directory(tempdir_name);
943 }
944
945 log_pop();
946 }
947
948 struct Abc9Pass : public Pass {
949 Abc9Pass() : Pass("abc9", "use ABC for technology mapping") { }
950 void help() YS_OVERRIDE
951 {
952 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
953 log("\n");
954 log(" abc9 [options] [selection]\n");
955 log("\n");
956 log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
957 log("library to a target architecture.\n");
958 log("\n");
959 log(" -exe <command>\n");
960 #ifdef ABCEXTERNAL
961 log(" use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
962 #else
963 log(" use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
964 #endif
965 log(" This can e.g. be used to call a specific version of ABC or a wrapper.\n");
966 log("\n");
967 log(" -script <file>\n");
968 log(" use the specified ABC script file instead of the default script.\n");
969 log("\n");
970 log(" if <file> starts with a plus sign (+), then the rest of the filename\n");
971 log(" string is interpreted as the command string to be passed to ABC. The\n");
972 log(" leading plus sign is removed and all commas (,) in the string are\n");
973 log(" replaced with blanks before the string is passed to ABC.\n");
974 log("\n");
975 log(" if no -script parameter is given, the following scripts are used:\n");
976 log("\n");
977 log(" for -liberty without -constr:\n");
978 log("%s\n", fold_abc_cmd(ABC_COMMAND_LIB).c_str());
979 log("\n");
980 log(" for -liberty with -constr:\n");
981 log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
982 log("\n");
983 log(" for -lut/-luts (only one LUT size):\n");
984 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack {S}").c_str());
985 log("\n");
986 log(" for -lut/-luts (different LUT sizes):\n");
987 log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
988 log("\n");
989 log(" for -sop:\n");
990 log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
991 log("\n");
992 log(" otherwise:\n");
993 log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
994 log("\n");
995 log(" -fast\n");
996 log(" use different default scripts that are slightly faster (at the cost\n");
997 log(" of output quality):\n");
998 log("\n");
999 log(" for -liberty without -constr:\n");
1000 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LIB).c_str());
1001 log("\n");
1002 log(" for -liberty with -constr:\n");
1003 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
1004 log("\n");
1005 log(" for -lut/-luts:\n");
1006 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
1007 log("\n");
1008 log(" for -sop:\n");
1009 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
1010 log("\n");
1011 log(" otherwise:\n");
1012 log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
1013 log("\n");
1014 log(" -liberty <file>\n");
1015 log(" generate netlists for the specified cell library (using the liberty\n");
1016 log(" file format).\n");
1017 log("\n");
1018 log(" -constr <file>\n");
1019 log(" pass this file with timing constraints to ABC. Use with -liberty.\n");
1020 log("\n");
1021 log(" a constr file contains two lines:\n");
1022 log(" set_driving_cell <cell_name>\n");
1023 log(" set_load <floating_point_number>\n");
1024 log("\n");
1025 log(" the set_driving_cell statement defines which cell type is assumed to\n");
1026 log(" drive the primary inputs and the set_load statement sets the load in\n");
1027 log(" femtofarads for each primary output.\n");
1028 log("\n");
1029 log(" -D <picoseconds>\n");
1030 log(" set delay target. the string {D} in the default scripts above is\n");
1031 log(" replaced by this option when used, and an empty string otherwise.\n");
1032 log(" this also replaces 'dretime' with 'dretime; retime -o {D}' in the\n");
1033 log(" default scripts above.\n");
1034 log("\n");
1035 log(" -I <num>\n");
1036 log(" maximum number of SOP inputs.\n");
1037 log(" (replaces {I} in the default scripts above)\n");
1038 log("\n");
1039 log(" -P <num>\n");
1040 log(" maximum number of SOP products.\n");
1041 log(" (replaces {P} in the default scripts above)\n");
1042 log("\n");
1043 log(" -S <num>\n");
1044 log(" maximum number of LUT inputs shared.\n");
1045 log(" (replaces {S} in the default scripts above, default: -S 1)\n");
1046 log("\n");
1047 log(" -lut <width>\n");
1048 log(" generate netlist using luts of (max) the specified width.\n");
1049 log("\n");
1050 log(" -lut <w1>:<w2>\n");
1051 log(" generate netlist using luts of (max) the specified width <w2>. All\n");
1052 log(" luts with width <= <w1> have constant cost. for luts larger than <w1>\n");
1053 log(" the area cost doubles with each additional input bit. the delay cost\n");
1054 log(" is still constant for all lut widths.\n");
1055 log("\n");
1056 log(" -lut <file>\n");
1057 log(" pass this file with lut library to ABC.\n");
1058 log("\n");
1059 log(" -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..\n");
1060 log(" generate netlist using luts. Use the specified costs for luts with 1,\n");
1061 log(" 2, 3, .. inputs.\n");
1062 log("\n");
1063 log(" -sop\n");
1064 log(" map to sum-of-product cells and inverters\n");
1065 log("\n");
1066 // log(" -mux4, -mux8, -mux16\n");
1067 // log(" try to extract 4-input, 8-input, and/or 16-input muxes\n");
1068 // log(" (ignored when used with -liberty or -lut)\n");
1069 // log("\n");
1070 log(" -g type1,type2,...\n");
1071 log(" Map to the specified list of gate types. Supported gates types are:\n");
1072 log(" AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.\n");
1073 log(" (The NOT gate is always added to this list automatically.)\n");
1074 log("\n");
1075 log(" The following aliases can be used to reference common sets of gate types:\n");
1076 log(" simple: AND OR XOR MUX\n");
1077 log(" cmos2: NAND NOR\n");
1078 log(" cmos3: NAND NOR AOI3 OAI3\n");
1079 log(" cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4\n");
1080 log(" gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT\n");
1081 log(" aig: AND NAND OR NOR ANDNOT ORNOT\n");
1082 log("\n");
1083 log(" Prefix a gate type with a '-' to remove it from the list. For example\n");
1084 log(" the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.\n");
1085 log("\n");
1086 log(" -dff\n");
1087 log(" also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many\n");
1088 log(" clock domains are automatically partitioned in clock domains and each\n");
1089 log(" domain is passed through ABC independently.\n");
1090 log("\n");
1091 log(" -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]\n");
1092 log(" use only the specified clock domain. this is like -dff, but only FF\n");
1093 log(" cells that belong to the specified clock domain are used.\n");
1094 log("\n");
1095 log(" -keepff\n");
1096 log(" set the \"keep\" attribute on flip-flop output wires. (and thus preserve\n");
1097 log(" them, for example for equivalence checking.)\n");
1098 log("\n");
1099 log(" -nocleanup\n");
1100 log(" when this option is used, the temporary files created by this pass\n");
1101 log(" are not removed. this is useful for debugging.\n");
1102 log("\n");
1103 log(" -showtmp\n");
1104 log(" print the temp dir name in log. usually this is suppressed so that the\n");
1105 log(" command output is identical across runs.\n");
1106 log("\n");
1107 log(" -markgroups\n");
1108 log(" set a 'abcgroup' attribute on all objects created by ABC. The value of\n");
1109 log(" this attribute is a unique integer for each ABC process started. This\n");
1110 log(" is useful for debugging the partitioning of clock domains.\n");
1111 log("\n");
1112 log(" -box <file>\n");
1113 log(" pass this file with box library to ABC. Use with -lut.\n");
1114 log("\n");
1115 log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
1116 log("loaded into ABC before the ABC script is executed.\n");
1117 log("\n");
1118 log("Note that this is a logic optimization pass within Yosys that is calling ABC\n");
1119 log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
1120 log("ABC on logic snippets extracted from your design. You will not get any useful\n");
1121 log("output when passing an ABC script that writes a file. Instead write your full\n");
1122 log("design as BLIF file with write_blif and the load that into ABC externally if\n");
1123 log("you want to use ABC to convert your design into another format.\n");
1124 log("\n");
1125 log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
1126 log("\n");
1127 }
1128 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1129 {
1130 log_header(design, "Executing ABC9 pass (technology mapping using ABC).\n");
1131 log_push();
1132
1133 assign_map.clear();
1134 signal_map.clear();
1135 signal_init.clear();
1136 pi_map.clear();
1137 po_map.clear();
1138
1139 #ifdef ABCEXTERNAL
1140 std::string exe_file = ABCEXTERNAL;
1141 #else
1142 std::string exe_file = proc_self_dirname() + "yosys-abc";
1143 #endif
1144 std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file;
1145 std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
1146 bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
1147 bool show_tempdir = false, sop_mode = false;
1148 vector<int> lut_costs;
1149 markgroups = false;
1150
1151 map_mux4 = false;
1152 map_mux8 = false;
1153 map_mux16 = false;
1154 enabled_gates.clear();
1155
1156 #ifdef _WIN32
1157 #ifndef ABCEXTERNAL
1158 if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
1159 exe_file = proc_self_dirname() + "..\\yosys-abc";
1160 #endif
1161 #endif
1162
1163 size_t argidx;
1164 char pwd [PATH_MAX];
1165 if (!getcwd(pwd, sizeof(pwd))) {
1166 log_cmd_error("getcwd failed: %s\n", strerror(errno));
1167 log_abort();
1168 }
1169 for (argidx = 1; argidx < args.size(); argidx++) {
1170 std::string arg = args[argidx];
1171 if (arg == "-exe" && argidx+1 < args.size()) {
1172 exe_file = args[++argidx];
1173 continue;
1174 }
1175 if (arg == "-script" && argidx+1 < args.size()) {
1176 script_file = args[++argidx];
1177 rewrite_filename(script_file);
1178 if (!script_file.empty() && !is_absolute_path(script_file) && script_file[0] != '+')
1179 script_file = std::string(pwd) + "/" + script_file;
1180 continue;
1181 }
1182 if (arg == "-liberty" && argidx+1 < args.size()) {
1183 liberty_file = args[++argidx];
1184 rewrite_filename(liberty_file);
1185 if (!liberty_file.empty() && !is_absolute_path(liberty_file))
1186 liberty_file = std::string(pwd) + "/" + liberty_file;
1187 continue;
1188 }
1189 if (arg == "-constr" && argidx+1 < args.size()) {
1190 constr_file = args[++argidx];
1191 rewrite_filename(constr_file);
1192 if (!constr_file.empty() && !is_absolute_path(constr_file))
1193 constr_file = std::string(pwd) + "/" + constr_file;
1194 continue;
1195 }
1196 if (arg == "-D" && argidx+1 < args.size()) {
1197 delay_target = "-D " + args[++argidx];
1198 continue;
1199 }
1200 if (arg == "-I" && argidx+1 < args.size()) {
1201 sop_inputs = "-I " + args[++argidx];
1202 continue;
1203 }
1204 if (arg == "-P" && argidx+1 < args.size()) {
1205 sop_products = "-P " + args[++argidx];
1206 continue;
1207 }
1208 if (arg == "-S" && argidx+1 < args.size()) {
1209 lutin_shared = "-S " + args[++argidx];
1210 continue;
1211 }
1212 if (arg == "-lut" && argidx+1 < args.size()) {
1213 string arg = args[++argidx];
1214 size_t pos = arg.find_first_of(':');
1215 int lut_mode = 0, lut_mode2 = 0;
1216 if (pos != string::npos) {
1217 lut_mode = atoi(arg.substr(0, pos).c_str());
1218 lut_mode2 = atoi(arg.substr(pos+1).c_str());
1219 } else {
1220 pos = arg.find_first_of('.');
1221 if (pos != string::npos) {
1222 lut_file = arg;
1223 rewrite_filename(lut_file);
1224 if (!lut_file.empty() && !is_absolute_path(lut_file))
1225 lut_file = std::string(pwd) + "/" + lut_file;
1226 }
1227 else {
1228 lut_mode = atoi(arg.c_str());
1229 lut_mode2 = lut_mode;
1230 }
1231 }
1232 lut_costs.clear();
1233 for (int i = 0; i < lut_mode; i++)
1234 lut_costs.push_back(1);
1235 for (int i = lut_mode; i < lut_mode2; i++)
1236 lut_costs.push_back(2 << (i - lut_mode));
1237 continue;
1238 }
1239 if (arg == "-luts" && argidx+1 < args.size()) {
1240 lut_costs.clear();
1241 for (auto &tok : split_tokens(args[++argidx], ",")) {
1242 auto parts = split_tokens(tok, ":");
1243 if (GetSize(parts) == 0 && !lut_costs.empty())
1244 lut_costs.push_back(lut_costs.back());
1245 else if (GetSize(parts) == 1)
1246 lut_costs.push_back(atoi(parts.at(0).c_str()));
1247 else if (GetSize(parts) == 2)
1248 while (GetSize(lut_costs) < atoi(parts.at(0).c_str()))
1249 lut_costs.push_back(atoi(parts.at(1).c_str()));
1250 else
1251 log_cmd_error("Invalid -luts syntax.\n");
1252 }
1253 continue;
1254 }
1255 if (arg == "-sop") {
1256 sop_mode = true;
1257 continue;
1258 }
1259 if (arg == "-mux4") {
1260 map_mux4 = true;
1261 continue;
1262 }
1263 if (arg == "-mux8") {
1264 map_mux8 = true;
1265 continue;
1266 }
1267 if (arg == "-mux16") {
1268 map_mux16 = true;
1269 continue;
1270 }
1271 if (arg == "-dress") {
1272 // TODO
1273 //abc_dress = true;
1274 continue;
1275 }
1276 if (arg == "-g" && argidx+1 < args.size()) {
1277 for (auto g : split_tokens(args[++argidx], ",")) {
1278 vector<string> gate_list;
1279 bool remove_gates = false;
1280 if (GetSize(g) > 0 && g[0] == '-') {
1281 remove_gates = true;
1282 g = g.substr(1);
1283 }
1284 if (g == "AND") goto ok_gate;
1285 if (g == "NAND") goto ok_gate;
1286 if (g == "OR") goto ok_gate;
1287 if (g == "NOR") goto ok_gate;
1288 if (g == "XOR") goto ok_gate;
1289 if (g == "XNOR") goto ok_gate;
1290 if (g == "ANDNOT") goto ok_gate;
1291 if (g == "ORNOT") goto ok_gate;
1292 if (g == "MUX") goto ok_gate;
1293 if (g == "AOI3") goto ok_gate;
1294 if (g == "OAI3") goto ok_gate;
1295 if (g == "AOI4") goto ok_gate;
1296 if (g == "OAI4") goto ok_gate;
1297 if (g == "simple") {
1298 gate_list.push_back("AND");
1299 gate_list.push_back("OR");
1300 gate_list.push_back("XOR");
1301 gate_list.push_back("MUX");
1302 goto ok_alias;
1303 }
1304 if (g == "cmos2") {
1305 gate_list.push_back("NAND");
1306 gate_list.push_back("NOR");
1307 goto ok_alias;
1308 }
1309 if (g == "cmos3") {
1310 gate_list.push_back("NAND");
1311 gate_list.push_back("NOR");
1312 gate_list.push_back("AOI3");
1313 gate_list.push_back("OAI3");
1314 goto ok_alias;
1315 }
1316 if (g == "cmos4") {
1317 gate_list.push_back("NAND");
1318 gate_list.push_back("NOR");
1319 gate_list.push_back("AOI3");
1320 gate_list.push_back("OAI3");
1321 gate_list.push_back("AOI4");
1322 gate_list.push_back("OAI4");
1323 goto ok_alias;
1324 }
1325 if (g == "gates") {
1326 gate_list.push_back("AND");
1327 gate_list.push_back("NAND");
1328 gate_list.push_back("OR");
1329 gate_list.push_back("NOR");
1330 gate_list.push_back("XOR");
1331 gate_list.push_back("XNOR");
1332 gate_list.push_back("ANDNOT");
1333 gate_list.push_back("ORNOT");
1334 goto ok_alias;
1335 }
1336 if (g == "aig") {
1337 gate_list.push_back("AND");
1338 gate_list.push_back("NAND");
1339 gate_list.push_back("OR");
1340 gate_list.push_back("NOR");
1341 gate_list.push_back("ANDNOT");
1342 gate_list.push_back("ORNOT");
1343 goto ok_alias;
1344 }
1345 cmd_error(args, argidx, stringf("Unsupported gate type: %s", g.c_str()));
1346 ok_gate:
1347 gate_list.push_back(g);
1348 ok_alias:
1349 for (auto gate : gate_list) {
1350 if (remove_gates)
1351 enabled_gates.erase(gate);
1352 else
1353 enabled_gates.insert(gate);
1354 }
1355 }
1356 continue;
1357 }
1358 if (arg == "-fast") {
1359 fast_mode = true;
1360 continue;
1361 }
1362 if (arg == "-dff") {
1363 dff_mode = true;
1364 continue;
1365 }
1366 if (arg == "-clk" && argidx+1 < args.size()) {
1367 clk_str = args[++argidx];
1368 dff_mode = true;
1369 continue;
1370 }
1371 if (arg == "-keepff") {
1372 keepff = true;
1373 continue;
1374 }
1375 if (arg == "-nocleanup") {
1376 cleanup = false;
1377 continue;
1378 }
1379 if (arg == "-showtmp") {
1380 show_tempdir = true;
1381 continue;
1382 }
1383 if (arg == "-markgroups") {
1384 markgroups = true;
1385 continue;
1386 }
1387 if (arg == "-box" && argidx+1 < args.size()) {
1388 box_file = args[++argidx];
1389 rewrite_filename(box_file);
1390 if (!box_file.empty() && !is_absolute_path(box_file))
1391 box_file = std::string(pwd) + "/" + box_file;
1392 continue;
1393 }
1394 break;
1395 }
1396 extra_args(args, argidx, design);
1397
1398 if ((!lut_costs.empty() || !lut_file.empty()) && !liberty_file.empty())
1399 log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n");
1400 if (!constr_file.empty() && liberty_file.empty())
1401 log_cmd_error("Got -constr but no -liberty!\n");
1402
1403 for (auto mod : design->selected_modules())
1404 {
1405 if (mod->attributes.count("\\abc_box_id"))
1406 continue;
1407
1408 if (mod->processes.size() > 0) {
1409 log("Skipping module %s as it contains processes.\n", log_id(mod));
1410 continue;
1411 }
1412
1413 assign_map.set(mod);
1414 signal_init.clear();
1415
1416 for (Wire *wire : mod->wires())
1417 if (wire->attributes.count("\\init")) {
1418 SigSpec initsig = assign_map(wire);
1419 Const initval = wire->attributes.at("\\init");
1420 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
1421 switch (initval[i]) {
1422 case State::S0:
1423 signal_init[initsig[i]] = State::S0;
1424 break;
1425 case State::S1:
1426 signal_init[initsig[i]] = State::S0;
1427 break;
1428 default:
1429 break;
1430 }
1431 }
1432
1433 if (!dff_mode || !clk_str.empty()) {
1434 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
1435 delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode,
1436 box_file, lut_file);
1437 continue;
1438 }
1439
1440 CellTypes ct(design);
1441
1442 std::vector<RTLIL::Cell*> all_cells = mod->selected_cells();
1443 std::set<RTLIL::Cell*> unassigned_cells(all_cells.begin(), all_cells.end());
1444
1445 std::set<RTLIL::Cell*> expand_queue, next_expand_queue;
1446 std::set<RTLIL::Cell*> expand_queue_up, next_expand_queue_up;
1447 std::set<RTLIL::Cell*> expand_queue_down, next_expand_queue_down;
1448
1449 typedef tuple<bool, RTLIL::SigSpec, bool, RTLIL::SigSpec> clkdomain_t;
1450 std::map<clkdomain_t, std::vector<RTLIL::Cell*>> assigned_cells;
1451 std::map<RTLIL::Cell*, clkdomain_t> assigned_cells_reverse;
1452
1453 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
1454 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
1455
1456 for (auto cell : all_cells)
1457 {
1458 clkdomain_t key;
1459
1460 for (auto &conn : cell->connections())
1461 for (auto bit : conn.second) {
1462 bit = assign_map(bit);
1463 if (bit.wire != nullptr) {
1464 cell_to_bit[cell].insert(bit);
1465 bit_to_cell[bit].insert(cell);
1466 if (ct.cell_input(cell->type, conn.first)) {
1467 cell_to_bit_up[cell].insert(bit);
1468 bit_to_cell_down[bit].insert(cell);
1469 }
1470 if (ct.cell_output(cell->type, conn.first)) {
1471 cell_to_bit_down[cell].insert(bit);
1472 bit_to_cell_up[bit].insert(cell);
1473 }
1474 }
1475 }
1476
1477 if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_")
1478 {
1479 key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
1480 }
1481 else
1482 if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")
1483 {
1484 bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_";
1485 bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_";
1486 key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
1487 }
1488 else
1489 continue;
1490
1491 unassigned_cells.erase(cell);
1492 expand_queue.insert(cell);
1493 expand_queue_up.insert(cell);
1494 expand_queue_down.insert(cell);
1495
1496 assigned_cells[key].push_back(cell);
1497 assigned_cells_reverse[cell] = key;
1498 }
1499
1500 while (!expand_queue_up.empty() || !expand_queue_down.empty())
1501 {
1502 if (!expand_queue_up.empty())
1503 {
1504 RTLIL::Cell *cell = *expand_queue_up.begin();
1505 clkdomain_t key = assigned_cells_reverse.at(cell);
1506 expand_queue_up.erase(cell);
1507
1508 for (auto bit : cell_to_bit_up[cell])
1509 for (auto c : bit_to_cell_up[bit])
1510 if (unassigned_cells.count(c)) {
1511 unassigned_cells.erase(c);
1512 next_expand_queue_up.insert(c);
1513 assigned_cells[key].push_back(c);
1514 assigned_cells_reverse[c] = key;
1515 expand_queue.insert(c);
1516 }
1517 }
1518
1519 if (!expand_queue_down.empty())
1520 {
1521 RTLIL::Cell *cell = *expand_queue_down.begin();
1522 clkdomain_t key = assigned_cells_reverse.at(cell);
1523 expand_queue_down.erase(cell);
1524
1525 for (auto bit : cell_to_bit_down[cell])
1526 for (auto c : bit_to_cell_down[bit])
1527 if (unassigned_cells.count(c)) {
1528 unassigned_cells.erase(c);
1529 next_expand_queue_up.insert(c);
1530 assigned_cells[key].push_back(c);
1531 assigned_cells_reverse[c] = key;
1532 expand_queue.insert(c);
1533 }
1534 }
1535
1536 if (expand_queue_up.empty() && expand_queue_down.empty()) {
1537 expand_queue_up.swap(next_expand_queue_up);
1538 expand_queue_down.swap(next_expand_queue_down);
1539 }
1540 }
1541
1542 while (!expand_queue.empty())
1543 {
1544 RTLIL::Cell *cell = *expand_queue.begin();
1545 clkdomain_t key = assigned_cells_reverse.at(cell);
1546 expand_queue.erase(cell);
1547
1548 for (auto bit : cell_to_bit.at(cell)) {
1549 for (auto c : bit_to_cell[bit])
1550 if (unassigned_cells.count(c)) {
1551 unassigned_cells.erase(c);
1552 next_expand_queue.insert(c);
1553 assigned_cells[key].push_back(c);
1554 assigned_cells_reverse[c] = key;
1555 }
1556 bit_to_cell[bit].clear();
1557 }
1558
1559 if (expand_queue.empty())
1560 expand_queue.swap(next_expand_queue);
1561 }
1562
1563 clkdomain_t key(true, RTLIL::SigSpec(), true, RTLIL::SigSpec());
1564 for (auto cell : unassigned_cells) {
1565 assigned_cells[key].push_back(cell);
1566 assigned_cells_reverse[cell] = key;
1567 }
1568
1569 log_header(design, "Summary of detected clock domains:\n");
1570 for (auto &it : assigned_cells)
1571 log(" %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
1572 std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
1573 std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
1574
1575 for (auto &it : assigned_cells) {
1576 clk_polarity = std::get<0>(it.first);
1577 clk_sig = assign_map(std::get<1>(it.first));
1578 en_polarity = std::get<2>(it.first);
1579 en_sig = assign_map(std::get<3>(it.first));
1580 abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
1581 keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode,
1582 box_file, lut_file);
1583 assign_map.set(mod);
1584 }
1585 }
1586
1587 Pass::call(design, "clean");
1588
1589 assign_map.clear();
1590 signal_map.clear();
1591 signal_init.clear();
1592 pi_map.clear();
1593 po_map.clear();
1594
1595 log_pop();
1596 }
1597 } Abc9Pass;
1598
1599 PRIVATE_NAMESPACE_END